From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: [PATCH v4 04/10] target/riscv: Add the lowRISC Ibex CPU
Date: Wed, 27 May 2020 09:50:23 -0700 [thread overview]
Message-ID: <7477d159ddc39758d60f5c68b99052dd30441ea4.1590598125.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1590598125.git.alistair.francis@wdc.com>
Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.
For more details on lowRISC see here:
https://github.com/lowRISC/ibex
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0e7f5b9c5..8733d7467f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -35,6 +35,7 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
+#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8deba3d16d..4761ebad42 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -154,6 +154,16 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
set_feature(env, RISCV_FEATURE_PMP);
}
+static void rv32imcu_nommu_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+ set_priv_version(env, PRIV_VERSION_1_10_0);
+ set_resetvec(env, 0x8090);
+ set_feature(env, RISCV_FEATURE_PMP);
+ qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
+
static void rv32imacu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -618,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
--
2.26.2
next prev parent reply other threads:[~2020-05-27 17:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-27 16:50 [PATCH v4 00/10] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-27 16:50 ` [PATCH v4 01/10] riscv/boot: Add a missing header include Alistair Francis
2020-05-27 16:50 ` [PATCH v4 02/10] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-27 16:50 ` [PATCH v4 03/10] target/riscv: Disable the MMU correctly Alistair Francis
2020-05-28 2:32 ` Bin Meng
2020-05-28 18:14 ` Alistair Francis
2020-05-27 16:50 ` Alistair Francis [this message]
2020-05-27 16:50 ` [PATCH v4 05/10] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-05-27 16:50 ` [PATCH v4 06/10] hw/char: Initial commit of Ibex UART Alistair Francis
2020-05-27 16:50 ` [PATCH v4 07/10] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-27 16:50 ` [PATCH v4 08/10] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-27 16:50 ` [PATCH v4 09/10] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-27 16:50 ` [PATCH v4 10/10] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-05-28 2:34 ` Bin Meng
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