From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: [PATCH v4 00/10] RISC-V Add the OpenTitan Machine
Date: Wed, 27 May 2020 09:50:11 -0700 [thread overview]
Message-ID: <cover.1590598125.git.alistair.francis@wdc.com> (raw)
OpenTitan is an open source silicon Root of Trust (RoT) project. This
series adds initial support for the OpenTitan machine to QEMU.
This series add the Ibex CPU to the QEMU RISC-V target. It then adds the
OpenTitan machine, the Ibex UART and the Ibex PLIC.
The UART has been tested sending and receiving data.
With this series QEMU can boot the OpenTitan ROM, Tock OS and a Tock
userspace app.
The Ibex PLIC is similar to the RISC-V PLIC (and is based on the QEMU
implementation) with some differences. The hope is that the Ibex PLIC
will converge to follow the RISC-V spec. As that happens I want to
update the QEMU Ibex PLIC and hopefully eventually replace the current
PLIC as the implementation is a little overlay complex.
For more details on OpenTitan, see here: https://docs.opentitan.org/
v4:
- Don't set the reset vector in realise
- Fix a bug where the MMU is always enabled
- Fixup the PMP/MMU size logic
v3:
- Small fixes pointed out in review
v2:
- Rebase on master
- Get uart receive working
Alistair Francis (10):
riscv/boot: Add a missing header include
target/riscv: Don't overwrite the reset vector
target/riscv: Disable the MMU correctly
target/riscv: Add the lowRISC Ibex CPU
riscv: Initial commit of OpenTitan machine
hw/char: Initial commit of Ibex UART
hw/intc: Initial commit of lowRISC Ibex PLIC
riscv/opentitan: Connect the PLIC device
riscv/opentitan: Connect the UART device
target/riscv: Use a smaller guess size for no-MMU PMP
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 11 +-
include/hw/char/ibex_uart.h | 110 +++++++
include/hw/intc/ibex_plic.h | 63 ++++
include/hw/riscv/boot.h | 1 +
include/hw/riscv/opentitan.h | 79 +++++
target/riscv/cpu.h | 1 +
hw/char/ibex_uart.c | 492 ++++++++++++++++++++++++++++
hw/intc/ibex_plic.c | 261 +++++++++++++++
hw/riscv/opentitan.c | 204 ++++++++++++
target/riscv/cpu.c | 21 +-
target/riscv/pmp.c | 14 +-
MAINTAINERS | 13 +
hw/char/Makefile.objs | 1 +
hw/intc/Makefile.objs | 1 +
hw/riscv/Kconfig | 9 +
hw/riscv/Makefile.objs | 1 +
17 files changed, 1272 insertions(+), 11 deletions(-)
create mode 100644 include/hw/char/ibex_uart.h
create mode 100644 include/hw/intc/ibex_plic.h
create mode 100644 include/hw/riscv/opentitan.h
create mode 100644 hw/char/ibex_uart.c
create mode 100644 hw/intc/ibex_plic.c
create mode 100644 hw/riscv/opentitan.c
--
2.26.2
next reply other threads:[~2020-05-27 16:59 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-27 16:50 Alistair Francis [this message]
2020-05-27 16:50 ` [PATCH v4 01/10] riscv/boot: Add a missing header include Alistair Francis
2020-05-27 16:50 ` [PATCH v4 02/10] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-27 16:50 ` [PATCH v4 03/10] target/riscv: Disable the MMU correctly Alistair Francis
2020-05-28 2:32 ` Bin Meng
2020-05-28 18:14 ` Alistair Francis
2020-05-27 16:50 ` [PATCH v4 04/10] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-27 16:50 ` [PATCH v4 05/10] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-05-27 16:50 ` [PATCH v4 06/10] hw/char: Initial commit of Ibex UART Alistair Francis
2020-05-27 16:50 ` [PATCH v4 07/10] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-27 16:50 ` [PATCH v4 08/10] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-27 16:50 ` [PATCH v4 09/10] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-27 16:50 ` [PATCH v4 10/10] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-05-28 2:34 ` Bin Meng
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