From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alex.bennee@linaro.org
Subject: Re: [PATCH v4 06/40] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask
Date: Tue, 3 Dec 2019 07:25:08 +0100 [thread overview]
Message-ID: <82c07397-e462-9408-67eb-09ba089b5f39@redhat.com> (raw)
In-Reply-To: <20191203022937.1474-7-richard.henderson@linaro.org>
On 12/3/19 3:29 AM, Richard Henderson wrote:
> No functional change, but unify code sequences.
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Easier to review in 2 patches: vae1_tlbmask first, then vmalle1_tlbmask.
If you need to respin, the 2 patches are welcome. Regardless:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 118 ++++++++++++++------------------------------
> 1 file changed, 37 insertions(+), 81 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 731507a82f..0b0130d814 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3890,70 +3890,61 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
> * Page D4-1736 (DDI0487A.b)
> */
>
> +static int vae1_tlbmask(CPUARMState *env)
> +{
> + if (arm_is_secure_below_el3(env)) {
> + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
> + } else {
> + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
> + }
> +}
> +
> static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> CPUState *cs = env_cpu(env);
> - bool sec = arm_is_secure_below_el3(env);
> + int mask = vae1_tlbmask(env);
>
> - if (sec) {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
> }
>
> static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> CPUState *cs = env_cpu(env);
> + int mask = vae1_tlbmask(env);
>
> if (tlb_force_broadcast(env)) {
> tlbi_aa64_vmalle1is_write(env, NULL, value);
> return;
> }
>
> + tlb_flush_by_mmuidx(cs, mask);
> +}
> +
> +static int vmalle1_tlbmask(CPUARMState *env)
> +{
> + /*
> + * Note that the 'ALL' scope must invalidate both stage 1 and
> + * stage 2 translations, whereas most other scopes only invalidate
> + * stage 1 translations.
> + */
> if (arm_is_secure_below_el3(env)) {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
> + } else if (arm_feature(env, ARM_FEATURE_EL2)) {
> + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
> } else {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
> }
> }
>
> static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - /* Note that the 'ALL' scope must invalidate both stage 1 and
> - * stage 2 translations, whereas most other scopes only invalidate
> - * stage 1 translations.
> - */
> - ARMCPU *cpu = env_archcpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> + int mask = vmalle1_tlbmask(env);
>
> - if (arm_is_secure_below_el3(env)) {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - if (arm_feature(env, ARM_FEATURE_EL2)) {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0 |
> - ARMMMUIdxBit_S2NS);
> - } else {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> - }
> + tlb_flush_by_mmuidx(cs, mask);
> }
>
> static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3977,28 +3968,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - /* Note that the 'ALL' scope must invalidate both stage 1 and
> - * stage 2 translations, whereas most other scopes only invalidate
> - * stage 1 translations.
> - */
> CPUState *cs = env_cpu(env);
> - bool sec = arm_is_secure_below_el3(env);
> - bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
> + int mask = vmalle1_tlbmask(env);
>
> - if (sec) {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else if (has_el2) {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0 |
> - ARMMMUIdxBit_S2NS);
> - } else {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
> }
>
> static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4048,20 +4021,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = env_archcpu(env);
> - CPUState *cs = CPU(cpu);
> - bool sec = arm_is_secure_below_el3(env);
> + CPUState *cs = env_cpu(env);
> + int mask = vae1_tlbmask(env);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> - if (sec) {
> - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
> }
>
> static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4072,8 +4036,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * since we don't support flush-for-specific-ASID-only or
> * flush-last-level-only.
> */
> - ARMCPU *cpu = env_archcpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> + int mask = vae1_tlbmask(env);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> if (tlb_force_broadcast(env)) {
> @@ -4081,15 +4045,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> return;
> }
>
> - if (arm_is_secure_below_el3(env)) {
> - tlb_flush_page_by_mmuidx(cs, pageaddr,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - tlb_flush_page_by_mmuidx(cs, pageaddr,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
> }
>
> static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>
next prev parent reply other threads:[~2019-12-03 6:26 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 2:28 [PATCH v4 00/40] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-12-03 2:28 ` [PATCH v4 01/40] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-12-03 2:28 ` [PATCH v4 02/40] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-12-03 2:29 ` [PATCH v4 03/40] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-12-03 2:29 ` [PATCH v4 04/40] target/arm: Add TTBR1_EL2 Richard Henderson
2019-12-10 9:14 ` Laurent Desnogues
2019-12-03 2:29 ` [PATCH v4 05/40] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-12-03 2:29 ` [PATCH v4 06/40] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-12-03 6:25 ` Philippe Mathieu-Daudé [this message]
2019-12-03 22:01 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 07/40] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-12-03 2:29 ` [PATCH v4 08/40] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2019-12-04 10:38 ` Alex Bennée
2019-12-06 15:45 ` Peter Maydell
2019-12-06 18:00 ` Richard Henderson
2019-12-06 18:01 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 09/40] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2019-12-04 10:40 ` Alex Bennée
2019-12-06 15:46 ` Peter Maydell
2019-12-06 18:05 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 10/40] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2019-12-04 11:00 ` Alex Bennée
2019-12-06 15:47 ` Peter Maydell
2019-12-06 18:20 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 11/40] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* Richard Henderson
2019-12-04 11:01 ` Alex Bennée
2019-12-06 15:47 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 12/40] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2019-12-04 11:02 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2019-12-04 11:03 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 14/40] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2019-12-04 11:43 ` Alex Bennée
2019-12-04 14:27 ` Richard Henderson
2019-12-04 15:53 ` Alex Bennée
2019-12-04 16:19 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2019-12-04 11:48 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 16/40] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2019-12-04 11:56 ` Alex Bennée
2019-12-04 16:01 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2019-12-03 6:27 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 18/40] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-12-04 13:44 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 19/40] target/arm: Add regime_has_2_ranges Richard Henderson
2019-12-04 14:16 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 20/40] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-12-04 14:37 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 21/40] target/arm: Update arm_sctlr " Richard Henderson
2019-12-03 2:29 ` [PATCH v4 22/40] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2019-12-04 15:01 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 23/40] target/arm: Update ctr_el0_access " Richard Henderson
2019-12-04 16:11 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 24/40] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-12-03 2:29 ` [PATCH v4 25/40] target/arm: Update timer access for VHE Richard Henderson
2019-12-04 18:35 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2019-12-04 18:58 ` Alex Bennée
2019-12-04 19:47 ` Richard Henderson
2019-12-04 22:38 ` Alex Bennée
2019-12-05 15:09 ` Richard Henderson
2019-12-06 15:53 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 27/40] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-12-06 17:24 ` Peter Maydell
2019-12-06 18:36 ` Richard Henderson
2019-12-06 18:41 ` Peter Maydell
2019-12-06 18:53 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 28/40] target/arm: Add VHE timer " Richard Henderson
2019-12-06 17:33 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2019-12-06 17:05 ` Peter Maydell
2020-01-28 0:04 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 30/40] target/arm: Flush tlbs for E2&0 " Richard Henderson
2019-12-06 17:14 ` Peter Maydell
2020-01-29 17:05 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 31/40] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-12-06 16:59 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 32/40] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2019-12-06 16:50 ` [PATCH v4 32/40] target/arm: Update {fp, sve}_exception_el " Peter Maydell
2019-12-03 2:29 ` [PATCH v4 33/40] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2019-12-06 16:08 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 34/40] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2019-12-06 16:46 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 35/40] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2019-12-06 16:03 ` Peter Maydell
2019-12-06 18:51 ` Richard Henderson
2019-12-06 19:15 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-12-06 15:57 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 37/40] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2019-12-03 6:28 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 38/40] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2019-12-03 6:29 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 39/40] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2019-12-03 6:30 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 40/40] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
2019-12-06 15:57 ` Peter Maydell
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