* [PATCH] Target/arm: Implement Cortex-A5
@ 2021-12-13 18:24 Byron Lathi
2021-12-13 20:06 ` Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Byron Lathi @ 2021-12-13 18:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, Byron Lathi
Add support for the Cortex-A5. These changes are based off of the A7 and
A9 init functions, using the appropriate values from the technical
reference manual for the A5.
Signed-off-by: Byron Lathi <bslathi19@gmail.com>
---
target/arm/cpu_tcg.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 13d0e9b195..38f0fc3977 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -304,6 +304,42 @@ static void cortex_a8_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
}
+static void cortex_a5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a5";
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x410fc0f1;
+ cpu->reset_fpsid = 0x41023051;
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x11000011;
+ cpu->ctr = 0x83338003;
+ cpu->reset_sctlr = 0x00c50078;
+ cpu->isar.id_pfr0 = 0x00001231;
+ cpu->isar.id_pfr1 = 0x00000011;
+ cpu->isar.id_dfr0 = 0x02010444;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00100103;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01230000;
+ cpu->isar.id_mmfr3 = 0x00102211;
+ cpu->isar.id_isar0 = 0x00101111;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232041;
+ cpu->isar.id_isar3 = 0x11112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.dbgdidr = 0x1203f001;
+ cpu->clidr = 0x09200003;
+ cpu->ccsidr[0] = 0x701fe00a;
+ cpu->ccsidr[1] = 0x203fe00a;
+}
+
static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
/*
* power_control should be set to maximum latency. Again,
@@ -1019,6 +1055,7 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
{ .name = "arm1136", .initfn = arm1136_initfn },
{ .name = "arm1176", .initfn = arm1176_initfn },
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
+ { .name = "cortext-a5", .initfn = cortex_a5_initfn },
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] Target/arm: Implement Cortex-A5
2021-12-13 18:24 [PATCH] Target/arm: Implement Cortex-A5 Byron Lathi
@ 2021-12-13 20:06 ` Philippe Mathieu-Daudé
2021-12-13 20:46 ` Richard Henderson
2021-12-13 21:02 ` Alex Bennée
2 siblings, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-12-13 20:06 UTC (permalink / raw)
To: Byron Lathi, qemu-devel; +Cc: peter.maydell, qemu-arm
On 12/13/21 19:24, Byron Lathi wrote:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi <bslathi19@gmail.com>
> ---
> target/arm/cpu_tcg.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
> static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
> /*
> * power_control should be set to maximum latency. Again,
> @@ -1019,6 +1055,7 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
> { .name = "arm1136", .initfn = arm1136_initfn },
> { .name = "arm1176", .initfn = arm1176_initfn },
> { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
> + { .name = "cortext-a5", .initfn = cortex_a5_initfn },
Typo "cortex"?
> { .name = "cortex-a7", .initfn = cortex_a7_initfn },
> { .name = "cortex-a8", .initfn = cortex_a8_initfn },
> { .name = "cortex-a9", .initfn = cortex_a9_initfn },
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Target/arm: Implement Cortex-A5
2021-12-13 18:24 [PATCH] Target/arm: Implement Cortex-A5 Byron Lathi
2021-12-13 20:06 ` Philippe Mathieu-Daudé
@ 2021-12-13 20:46 ` Richard Henderson
2021-12-13 21:02 ` Alex Bennée
2 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2021-12-13 20:46 UTC (permalink / raw)
To: Byron Lathi, qemu-devel; +Cc: peter.maydell, qemu-arm
On 12/13/21 10:24 AM, Byron Lathi wrote:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi <bslathi19@gmail.com>
> ---
> target/arm/cpu_tcg.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index 13d0e9b195..38f0fc3977 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -304,6 +304,42 @@ static void cortex_a8_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
> }
>
> +static void cortex_a5_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,cortex-a5";
> + set_feature(&cpu->env, ARM_FEATURE_V7);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> + cpu->midr = 0x410fc0f1;
> + cpu->reset_fpsid = 0x41023051;
> + cpu->isar.mvfr0 = 0x10110221;
> + cpu->isar.mvfr1 = 0x11000011;
> + cpu->ctr = 0x83338003;
> + cpu->reset_sctlr = 0x00c50078;
> + cpu->isar.id_pfr0 = 0x00001231;
> + cpu->isar.id_pfr1 = 0x00000011;
> + cpu->isar.id_dfr0 = 0x02010444;
> + cpu->id_afr0 = 0x00000000;
> + cpu->isar.id_mmfr0 = 0x00100103;
> + cpu->isar.id_mmfr1 = 0x40000000;
> + cpu->isar.id_mmfr2 = 0x01230000;
> + cpu->isar.id_mmfr3 = 0x00102211;
> + cpu->isar.id_isar0 = 0x00101111;
> + cpu->isar.id_isar1 = 0x13112111;
> + cpu->isar.id_isar2 = 0x21232041;
> + cpu->isar.id_isar3 = 0x11112131;
> + cpu->isar.id_isar4 = 0x00011142;
> + cpu->isar.dbgdidr = 0x1203f001;
> + cpu->clidr = 0x09200003;
> + cpu->ccsidr[0] = 0x701fe00a;
> + cpu->ccsidr[1] = 0x203fe00a;
> +}
Looks ok.
> + { .name = "cortext-a5", .initfn = cortex_a5_initfn },
Typo.
In addition, you probably want to add the cortex-a5 to the list of cpus that are supported
by hw/arm/virt.c, and then you need to add this to docs/system/arm/virt.rst.
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Target/arm: Implement Cortex-A5
2021-12-13 18:24 [PATCH] Target/arm: Implement Cortex-A5 Byron Lathi
2021-12-13 20:06 ` Philippe Mathieu-Daudé
2021-12-13 20:46 ` Richard Henderson
@ 2021-12-13 21:02 ` Alex Bennée
2021-12-13 21:46 ` Richard Henderson
2 siblings, 1 reply; 7+ messages in thread
From: Alex Bennée @ 2021-12-13 21:02 UTC (permalink / raw)
To: Byron Lathi; +Cc: peter.maydell, qemu-arm, qemu-devel
Byron Lathi <bslathi19@gmail.com> writes:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi <bslathi19@gmail.com>
> ---
> target/arm/cpu_tcg.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index 13d0e9b195..38f0fc3977 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -304,6 +304,42 @@ static void cortex_a8_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
> }
>
> +static void cortex_a5_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,cortex-a5";
> + set_feature(&cpu->env, ARM_FEATURE_V7);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> + cpu->midr = 0x410fc0f1;
hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but
I can't find the actual value in the TRM.
> + cpu->reset_fpsid = 0x41023051;
I think for the a5 the FPU is optional so maybe we need a cpu option
here? Or maybe just assume it's enabled on QEMUs version?
> + cpu->isar.mvfr0 = 0x10110221;
> + cpu->isar.mvfr1 = 0x11000011;
> + cpu->ctr = 0x83338003;
> + cpu->reset_sctlr = 0x00c50078;
> + cpu->isar.id_pfr0 = 0x00001231;
> + cpu->isar.id_pfr1 = 0x00000011;
> + cpu->isar.id_dfr0 = 0x02010444;
> + cpu->id_afr0 = 0x00000000;
> + cpu->isar.id_mmfr0 = 0x00100103;
the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency not supported.
> + cpu->isar.id_mmfr1 = 0x40000000;
> + cpu->isar.id_mmfr2 = 0x01230000;
> + cpu->isar.id_mmfr3 = 0x00102211;
> + cpu->isar.id_isar0 = 0x00101111;
> + cpu->isar.id_isar1 = 0x13112111;
> + cpu->isar.id_isar2 = 0x21232041;
> + cpu->isar.id_isar3 = 0x11112131;
> + cpu->isar.id_isar4 = 0x00011142;
> + cpu->isar.dbgdidr = 0x1203f001;
> + cpu->clidr = 0x09200003;
I'm fairly sure these depend on the part as well although it makes no
difference to our emulation.
> + cpu->ccsidr[0] = 0x701fe00a;
> + cpu->ccsidr[1] = 0x203fe00a;
> +}
> +
> static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
> /*
> * power_control should be set to maximum latency. Again,
> @@ -1019,6 +1055,7 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
> { .name = "arm1136", .initfn = arm1136_initfn },
> { .name = "arm1176", .initfn = arm1176_initfn },
> { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
> + { .name = "cortext-a5", .initfn = cortex_a5_initfn },
Extra 't'
> { .name = "cortex-a7", .initfn = cortex_a7_initfn },
> { .name = "cortex-a8", .initfn = cortex_a8_initfn },
> { .name = "cortex-a9", .initfn = cortex_a9_initfn },
--
Alex Bennée
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Target/arm: Implement Cortex-A5
2021-12-13 21:02 ` Alex Bennée
@ 2021-12-13 21:46 ` Richard Henderson
2021-12-13 22:34 ` Byron Lathi
2021-12-17 18:12 ` Alex Bennée
0 siblings, 2 replies; 7+ messages in thread
From: Richard Henderson @ 2021-12-13 21:46 UTC (permalink / raw)
To: Alex Bennée, Byron Lathi; +Cc: peter.maydell, qemu-arm, qemu-devel
On 12/13/21 1:02 PM, Alex Bennée wrote:
>> + cpu->midr = 0x410fc0f1;
>
> hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but
> I can't find the actual value in the TRM.
https://developer.arm.com/documentation/ddi0434/c
has exactly this value at the top of table 4-9.
>> + cpu->reset_fpsid = 0x41023051;
>
> I think for the a5 the FPU is optional so maybe we need a cpu option
> here? Or maybe just assume it's enabled on QEMUs version?
Yeah, there's no entry for fpsid in the above manual.
>> + cpu->isar.id_mmfr0 = 0x00100103;
>
> the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency not supported.
Again, this does match table 4-9.
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Target/arm: Implement Cortex-A5
2021-12-13 21:46 ` Richard Henderson
@ 2021-12-13 22:34 ` Byron Lathi
2021-12-17 18:12 ` Alex Bennée
1 sibling, 0 replies; 7+ messages in thread
From: Byron Lathi @ 2021-12-13 22:34 UTC (permalink / raw)
To: Richard Henderson; +Cc: peter.maydell, qemu-arm, Alex Bennée, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1055 bytes --]
The goal for me was to eventually add the SAMA5D, so I might have made some
assumptions that were not correct for all devices. My apologies for the
typos.
I will add those changes and re-submit.
On Mon, Dec 13, 2021 at 3:46 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 12/13/21 1:02 PM, Alex Bennée wrote:
> >> + cpu->midr = 0x410fc0f1;
> >
> > hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but
> > I can't find the actual value in the TRM.
>
> https://developer.arm.com/documentation/ddi0434/c
>
> has exactly this value at the top of table 4-9.
>
> >> + cpu->reset_fpsid = 0x41023051;
> >
> > I think for the a5 the FPU is optional so maybe we need a cpu option
> > here? Or maybe just assume it's enabled on QEMUs version?
>
> Yeah, there's no entry for fpsid in the above manual.
>
> >> + cpu->isar.id_mmfr0 = 0x00100103;
> >
> > the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency not
> supported.
>
> Again, this does match table 4-9.
>
>
> r~
>
[-- Attachment #2: Type: text/html, Size: 1593 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Target/arm: Implement Cortex-A5
2021-12-13 21:46 ` Richard Henderson
2021-12-13 22:34 ` Byron Lathi
@ 2021-12-17 18:12 ` Alex Bennée
1 sibling, 0 replies; 7+ messages in thread
From: Alex Bennée @ 2021-12-17 18:12 UTC (permalink / raw)
To: Richard Henderson; +Cc: peter.maydell, qemu-arm, qemu-devel, Byron Lathi
Richard Henderson <richard.henderson@linaro.org> writes:
> On 12/13/21 1:02 PM, Alex Bennée wrote:
>>> + cpu->midr = 0x410fc0f1;
>> hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f)
>> but
>> I can't find the actual value in the TRM.
>
> https://developer.arm.com/documentation/ddi0434/c
>
> has exactly this value at the top of table 4-9.
Ahh good find - 0x410FC051 it is.
>
>>> + cpu->reset_fpsid = 0x41023051;
>> I think for the a5 the FPU is optional so maybe we need a cpu option
>> here? Or maybe just assume it's enabled on QEMUs version?
>
> Yeah, there's no entry for fpsid in the above manual.
>
>>> + cpu->isar.id_mmfr0 = 0x00100103;
>> the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency
>> not supported.
>
> Again, this does match table 4-9.
0x00100003
>
>
> r~
--
Alex Bennée
^ permalink raw reply [flat|nested] 7+ messages in thread
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2021-12-13 18:24 [PATCH] Target/arm: Implement Cortex-A5 Byron Lathi
2021-12-13 20:06 ` Philippe Mathieu-Daudé
2021-12-13 20:46 ` Richard Henderson
2021-12-13 21:02 ` Alex Bennée
2021-12-13 21:46 ` Richard Henderson
2021-12-13 22:34 ` Byron Lathi
2021-12-17 18:12 ` Alex Bennée
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