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* [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled
@ 2021-05-29 16:54 Philippe Mathieu-Daudé
  2021-05-30  0:54 ` Richard Henderson
  2021-06-19 18:01 ` Philippe Mathieu-Daudé
  0 siblings, 2 replies; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-29 16:54 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Jia Liu, Richard Henderson,
	Philippe Mathieu-Daudé,
	Aurelien Jarno

Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":

  If the Module/ASE is not implemented, executing such an instruction
  must cause a Reserved Instruction Exception.

The DINSV instruction lists the following exceptions:
- Reserved Instruction
- DSP Disabled

If the MIPS core doesn't support the DSP module, or the DSP is
disabled, do not handle the '$rt = $0' case as a no-op but raise
the proper exception instead.

Cc: Jia Liu <proljc@gmail.com>
Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c03a8ae1fed..6ccba34c050 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -24373,10 +24373,11 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
         {
             TCGv t0, t1;
 
+            check_dsp(ctx);
+
             if (rt == 0) {
                 break;
             }
-            check_dsp(ctx);
 
             t0 = tcg_temp_new();
             t1 = tcg_temp_new();
-- 
2.26.3



^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled
  2021-05-29 16:54 [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled Philippe Mathieu-Daudé
@ 2021-05-30  0:54 ` Richard Henderson
  2021-06-19 18:01 ` Philippe Mathieu-Daudé
  1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2021-05-30  0:54 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, Aurelien Jarno, Jia Liu

On 5/29/21 9:54 AM, Philippe Mathieu-Daudé wrote:
> Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
> Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
> 
>    If the Module/ASE is not implemented, executing such an instruction
>    must cause a Reserved Instruction Exception.
> 
> The DINSV instruction lists the following exceptions:
> - Reserved Instruction
> - DSP Disabled
> 
> If the MIPS core doesn't support the DSP module, or the DSP is
> disabled, do not handle the '$rt = $0' case as a no-op but raise
> the proper exception instead.
> 
> Cc: Jia Liu<proljc@gmail.com>
> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled
  2021-05-29 16:54 [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled Philippe Mathieu-Daudé
  2021-05-30  0:54 ` Richard Henderson
@ 2021-06-19 18:01 ` Philippe Mathieu-Daudé
  1 sibling, 0 replies; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-19 18:01 UTC (permalink / raw)
  To: qemu-devel; +Cc: Aleksandar Rikalo, Richard Henderson, Jia Liu, Aurelien Jarno

On 5/29/21 6:54 PM, Philippe Mathieu-Daudé wrote:
> Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
> Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
> 
>   If the Module/ASE is not implemented, executing such an instruction
>   must cause a Reserved Instruction Exception.
> 
> The DINSV instruction lists the following exceptions:
> - Reserved Instruction
> - DSP Disabled
> 
> If the MIPS core doesn't support the DSP module, or the DSP is
> disabled, do not handle the '$rt = $0' case as a no-op but raise
> the proper exception instead.
> 
> Cc: Jia Liu <proljc@gmail.com>
> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tcg/translate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Thanks, applied to mips-next.


^ permalink raw reply	[flat|nested] 3+ messages in thread

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2021-05-29 16:54 [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled Philippe Mathieu-Daudé
2021-05-30  0:54 ` Richard Henderson
2021-06-19 18:01 ` Philippe Mathieu-Daudé

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