From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"bmeng.cn@gmail.com" <bmeng.cn@gmail.com>,
"palmer@sifive.com" <palmer@sifive.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate()
Date: Mon, 26 Aug 2019 21:36:41 +0000 [thread overview]
Message-ID: <9802ed171372b72228fb12b1d225a43fd064d694.camel@wdc.com> (raw)
In-Reply-To: <1566537069-22741-13-git-send-email-bmeng.cn@gmail.com>
On Thu, 2019-08-22 at 22:10 -0700, Bin Meng wrote:
> Use create_unimplemented_device() instead.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common
> place"
> - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"
>
> hw/riscv/sifive_e.c | 23 ++++++++---------------
> 1 file changed, 8 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 2d67670..040d59f 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -37,6 +37,7 @@
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> #include "hw/char/serial.h"
> +#include "hw/misc/unimp.h"
> #include "target/riscv/cpu.h"
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_plic.h"
> @@ -74,14 +75,6 @@ static const struct MemmapEntry {
> [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
> };
>
> -static void sifive_mmio_emulate(MemoryRegion *parent, const char
> *name,
> - uintptr_t offset, uintptr_t length)
> -{
> - MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
> - memory_region_init_ram(mock_mmio, NULL, name, length,
> &error_fatal);
> - memory_region_add_subregion(parent, offset, mock_mmio);
> -}
> -
> static void riscv_sifive_e_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
> @@ -172,7 +165,7 @@ static void
> riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
> memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
> + create_unimplemented_device("riscv.sifive.e.aon",
> memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
>
> @@ -199,19 +192,19 @@ static void
> riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
>
> sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
> serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic),
> SIFIVE_E_UART0_IRQ));
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
> + create_unimplemented_device("riscv.sifive.e.qspi0",
> memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
> + create_unimplemented_device("riscv.sifive.e.pwm0",
> memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
> sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
> SIFIVE_E_UART1_IRQ));
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
> + create_unimplemented_device("riscv.sifive.e.qspi1",
> memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
> + create_unimplemented_device("riscv.sifive.e.pwm1",
> memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
> + create_unimplemented_device("riscv.sifive.e.qspi2",
> memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
> + create_unimplemented_device("riscv.sifive.e.pwm2",
> memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
>
> /* Flash memory */
prev parent reply other threads:[~2019-08-26 21:38 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 5:10 [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-08-23 17:38 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-08-23 17:38 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-23 18:31 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-23 17:36 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-23 18:34 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-23 23:45 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-23 23:52 ` Alistair Francis
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
2019-08-23 17:24 ` [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Alistair Francis
2019-08-24 5:07 ` Bin Meng
2019-08-26 21:33 ` Alistair Francis
2019-08-23 17:40 ` Alistair Francis
[not found] ` <1566537069-22741-13-git-send-email-bmeng.cn@gmail.com>
2019-08-26 21:36 ` Alistair Francis [this message]
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