qemu-devel.nongnu.org archive mirror

 messages from 2021-10-15 04:15:12 to 2021-10-15 09:02:05 UTC [more...]

[RFC PATCH v4 00/20] vDPA shadow virtqueue
 2021-10-15  8:37 UTC  (24+ messages)
` [RFC PATCH v4 11/20] vhost: Route host->guest notification through "
` [RFC PATCH v4 15/20] vhost: Shadow virtqueue buffers forwarding
` [RFC PATCH v4 16/20] vhost: Check for device VRING_USED_F_NO_NOTIFY at shadow virtqueue kick
` [RFC PATCH v4 17/20] vhost: Use VRING_AVAIL_F_NO_INTERRUPT at device call on shadow virtqueue
` [RFC PATCH v4 20/20] vdpa: Add custom IOTLB translations to SVQ

[PATCH v8 00/78] support vector extension v1.0
 2021-10-15  7:46 UTC  (82+ messages)
` [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
` [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support
` [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field
` [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field
` [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus "
` [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field
` [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status
` [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
` [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register
` [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register
` [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
` [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations
` [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL
` [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA
` [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions
` [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions
` [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function
` [PATCH 18/76] target/riscv: rvv-1.0: configure instructions
` [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions
` [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions
` [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions
` [PATCH 20/76] target/riscv: rvv-1.0: index "
` [PATCH v8 20/78] target/riscv: rvv-1.0: stride "
` [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
` [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions
` [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load
` [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
` [PATCH 23/76] target/riscv: rvv-1.0: amo operations
` [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load
` [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions
` [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
` [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
` [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction
` [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions
` [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction
` [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction
` [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction
` [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions
` [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction
` [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction
` [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended
` [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions
` [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions
` [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction
` [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions
` [PATCH v8 39/78] target/riscv: rvv-1.0: whole register "
` [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions
` [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
` [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions
` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
` [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions
` [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions
` [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
` [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions
` [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions
` [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions
` [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions
` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point "
` [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
` [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction
` [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions
` [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions
` [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
` [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
` [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction
` [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions
` [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum
` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert
` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function
` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
` [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR
` [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
` [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32
` [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs
` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
` [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment

[PATCH v4 0/3] vdpa: Check iova range on memory regions ops
 2021-10-15  8:12 UTC  (3+ messages)
` [PATCH v4 3/3] vdpa: Check for iova range at mappings changes

Is the ppc440 "bamboo" board in QEMU still of any use?
 2021-10-15  8:17 UTC  (10+ messages)

[PATCH v3] tests: qtest: Add virtio-iommu test
 2021-10-15  7:17 UTC  (3+ messages)

[PATCH 0/8] q800: GLUE updates for A/UX mode
 2021-10-15  7:17 UTC  (12+ messages)
` [PATCH 1/8] mac_via: update comment for VIA1B_vMystery bit
` [PATCH 2/8] q800: move VIA1 IRQ from level 1 to level 6
` [PATCH 3/8] q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs
` [PATCH 4/8] mac_via: add GPIO for A/UX mode
` [PATCH 5/8] q800: wire up auxmode GPIO to GLUE

[PATCH 0/6] Misc pegasos2 patches
 2021-10-15  3:20 UTC  (14+ messages)
` [PATCH 4/6] ppc/pegasos2: Access MV64361 registers via their memory region
` [PATCH 1/6] ppc/pegasos2: Restrict memory to 2 gigabytes
` [PATCH 5/6] ppc/pegasos2: Add constants for PCI config addresses
` [PATCH 3/6] ppc/pegasos2: Implement get-time-of-day RTAS function with VOF
` [PATCH 6/6] ppc/pegasos2: Implement power-off "
` [PATCH 2/6] ppc/pegasos2: Warn when using VOF but no kernel is specified

[PATCH v3 00/22] target/ppc: DFP instructions using decodetree
 2021-10-15  3:15 UTC  (4+ messages)

[PATCH v2 00/15] qdev: Add JSON -device
 2021-10-15  7:24 UTC  (6+ messages)
` [PATCH v2 09/15] softmmu/qdev-monitor: add error handling in qdev_set_id

[PATCH v2] hw/elf_ops.h: switch to ssize_t for elf loader return type
 2021-10-15  7:23 UTC  (2+ messages)

[PATCH v2 0/6] target/riscv: support Zfh, Zfhmin extension v0.1
 2021-10-15  7:03 UTC  (7+ messages)
` [PATCH v2 1/6] target/riscv: zfh: half-precision load and store
` [PATCH v2 2/6] target/riscv: zfh: half-precision computational
` [PATCH v2 3/6] target/riscv: zfh: half-precision convert and move
` [PATCH v2 4/6] target/riscv: zfh: half-precision floating-point compare
` [PATCH v2 5/6] target/riscv: zfh: half-precision floating-point classify
` [PATCH v2 6/6] target/riscv: zfh: implement zfhmin extension

[PATCH RESEND v3 0/2] add APIs to handle alternative sNaN propagation for fmax/fmin
 2021-10-15  6:54 UTC  (3+ messages)
` [PATCH v3 1/2] softfloat: "
` [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

[PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
 2021-10-15  6:52 UTC  (4+ messages)
` [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

[PATCH v2 00/22] QEMU RISC-V AIA support
 2021-10-15  6:24 UTC  (7+ messages)
` [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts

[PATCH 0/3] Postcopy migration: Add userfaultfd- user-mode-only capability
 2021-10-15  6:12 UTC  (4+ messages)

[PATCH] target/riscv: Fix orc.b implementation
 2021-10-15  5:28 UTC  (2+ messages)

[PATCH] microvm: add device tree support
 2021-10-15  5:26 UTC  (2+ messages)

[PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length
 2021-10-15  5:21 UTC  (15+ messages)
` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64

[PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling
 2021-10-15  4:10 UTC  (65+ messages)
` [PATCH v5 02/67] accel/tcg: Move clear_helper_retaddr to cpu loop
` [PATCH v5 03/67] accel/tcg: Split out handle_sigsegv_accerr_write
` [PATCH v5 06/67] linux-user: Reorg handling for SIGSEGV
` [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h
` [PATCH v5 08/67] linux-user/host/ppc: "
` [PATCH v5 09/67] linux-user/host/alpha: "
` [PATCH v5 10/67] linux-user/host/sparc: "
` [PATCH v5 11/67] linux-user/host/arm: "
` [PATCH v5 12/67] linux-user/host/aarch64: "
` [PATCH v5 13/67] linux-user/host/s390: "
` [PATCH v5 14/67] linux-user/host/mips: "
` [PATCH v5 15/67] linux-user/host/riscv: "
` [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal
` [PATCH v5 17/67] linux-user/host/riscv: Improve host_signal_write
` [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER
` [PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv
` [PATCH v5 20/67] linux-user: Add cpu_loop_exit_sigsegv
` [PATCH v5 21/67] target/alpha: Implement alpha_cpu_record_sigsegv
` [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup
` [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv
` [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only
` [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill
` [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only
` [PATCH v5 27/67] target/i386: Implement x86_cpu_record_sigsegv
` [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only
` [PATCH v5 29/67] target/microblaze: Make mb_cpu_tlb_fill "
` [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill "
` [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv
` [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE
` [PATCH v5 33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only
` [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv
` [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only
` [PATCH v5 36/67] target/s390x: Use probe_access_flags in s390_probe_access
` [PATCH v5 37/67] target/s390x: Implement s390_cpu_record_sigsegv
` [PATCH v5 38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only
` [PATCH v5 39/67] target/sparc: Make sparc_cpu_tlb_fill "
` [PATCH v5 40/67] target/xtensa: Make xtensa_cpu_tlb_fill "
` [PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu
` [PATCH v5 42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
` [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus
` [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus
` [PATCH v5 45/67] target/alpha: Implement alpha_cpu_record_sigbus
` [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus
` [PATCH v5 47/67] linux-user/hppa: Remove EXCP_UNALIGN handling
` [PATCH v5 48/67] target/microblaze: Do not set MO_ALIGN for user-only
` [PATCH v5 49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp
` [PATCH v5 50/67] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
` [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu
` [PATCH v5 52/67] target/s390x: Implement s390x_cpu_record_sigbus
` [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling
` [PATCH v5 54/67] target/sh4: Set fault address in superh_cpu_do_unaligned_access
` [PATCH v5 55/67] target/sparc: Remove DEBUG_UNALIGNED
` [PATCH v5 56/67] target/sparc: Split out build_sfsr
` [PATCH v5 57/67] target/sparc: Set fault address in sparc_cpu_do_unaligned_access
` [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only
` [PATCH v5 59/67] accel/tcg: Report unaligned load/store "
` [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus
` [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler
` [PATCH v5 62/67] linux-user: Split out do_prctl and subroutines
` [PATCH v5 63/67] linux-user: Disable more prctl subcodes
` [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN
` [PATCH v5 65/67] target/alpha: Implement prctl_unalign_sigbus
` [PATCH v5 66/67] target/hppa: "
` [PATCH v5 67/67] target/sh4: "