From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Alistair Francis <alistair23@gmail.com>,
Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v11 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
Date: Tue, 28 Sep 2021 20:45:46 +0200 [thread overview]
Message-ID: <CAAeLtUCiOFKN=xoJSJyuNHF2Yvc0pYb0ef3L3kB6NtGPQQ5h2w@mail.gmail.com> (raw)
In-Reply-To: <1dcc5800-a3e6-d1b8-c2e5-0ccf2d724c30@linaro.org>
On Tue, 28 Sept 2021 at 20:45, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/28/21 11:45 AM, Philipp Tomsich wrote:
> > The dup_const macro is returning an unsigned long long, which probably
> > should be fixed on the tcg.h-level instead of forcing a cast to target_long
> > at the call site.
>
> No, dup_const is first and primarily for vector support, and therefore must return a
> 64-bit constant.
>
> > Or should we introduce a dup_const_tl?
>
> Maybe. I guess that could be a bit better than the cast.
I'll provide a patch that wraps dup_const in a dup_const_tl.
Philipp.
next prev parent reply other threads:[~2021-09-28 18:48 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-11 14:00 [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
2021-09-14 9:15 ` LIU Zhiwei
2021-09-14 10:24 ` Philipp Tomsich
2021-09-15 8:11 ` LIU Zhiwei
2021-09-11 14:00 ` [PATCH v11 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-09-28 7:06 ` Alistair Francis
2021-09-28 15:45 ` Philipp Tomsich
2021-09-28 18:45 ` Richard Henderson
2021-09-28 18:45 ` Philipp Tomsich [this message]
2021-09-28 21:00 ` Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
2021-09-23 21:31 ` [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-24 3:02 ` Alistair Francis
[not found] ` <20210927200139.I7eoEgfBhWG60vy4RMFlcC9T5M5sfPH_jDWgYVbPfAE@z>
2021-09-27 20:01 ` Vineet Gupta
2021-09-27 20:23 ` Jim Wilson
2021-09-27 21:54 ` Vineet Gupta
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