* [PATCH v6 0/3] RTC support for QEMU RISC-V virt machine
@ 2019-11-03 7:55 Anup Patel
2019-11-03 7:55 ` [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device Anup Patel
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Anup Patel @ 2019-11-03 7:55 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable it in Kconfig for RISCV and also update Linux
defconfigs.
We have tested this series with Linux-5.4-rc4 plus defconfig changes
available in 'goldfish_rtc_v2' branch of:
https://github.com/avpatel/linux.git
Changes since v5:
- Rebased on latest QEMU master
- Added maintainer entry for Goldfish RTC
Changes since v4:
- Fixed typo in trace event usage
- Moved goldfish_rtc.h to correct location
Changes since v3:
- Address all nit comments from Alistair
Changes since v2:
- Rebased on RTC code refactoring
Changes since v1:
- Implemented VMState save/restore callbacks
Anup Patel (3):
hw: rtc: Add Goldfish RTC device
riscv: virt: Use Goldfish RTC device
MAINTAINERS: Add maintainer entry for Goldfish RTC
MAINTAINERS | 7 +
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c | 15 ++
hw/rtc/Kconfig | 3 +
hw/rtc/Makefile.objs | 1 +
hw/rtc/goldfish_rtc.c | 288 ++++++++++++++++++++++++++++++++++
hw/rtc/trace-events | 4 +
include/hw/riscv/virt.h | 2 +
include/hw/rtc/goldfish_rtc.h | 46 ++++++
9 files changed, 367 insertions(+)
create mode 100644 hw/rtc/goldfish_rtc.c
create mode 100644 include/hw/rtc/goldfish_rtc.h
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device 2019-11-03 7:55 [PATCH v6 0/3] RTC support for QEMU RISC-V virt machine Anup Patel @ 2019-11-03 7:55 ` Anup Patel 2019-11-05 23:24 ` Philippe Mathieu-Daudé 2019-11-03 7:55 ` [PATCH v6 2/3] riscv: virt: Use " Anup Patel 2019-11-03 7:55 ` [PATCH v6 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC Anup Patel 2 siblings, 1 reply; 7+ messages in thread From: Anup Patel @ 2019-11-03 7:55 UTC (permalink / raw) To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel This patch adds model for Google Goldfish virtual platform RTC device. We will be adding Goldfish RTC device to the QEMU RISC-V virt machine for providing real date-time to Guest Linux. The corresponding Linux driver for Goldfish RTC device is already available in upstream Linux. For now, VM migration support is available but untested for Goldfish RTC device. It will be hardened in-future when we implement VM migration for KVM RISC-V. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- hw/rtc/Kconfig | 3 + hw/rtc/Makefile.objs | 1 + hw/rtc/goldfish_rtc.c | 288 ++++++++++++++++++++++++++++++++++ hw/rtc/trace-events | 4 + include/hw/rtc/goldfish_rtc.h | 46 ++++++ 5 files changed, 342 insertions(+) create mode 100644 hw/rtc/goldfish_rtc.c create mode 100644 include/hw/rtc/goldfish_rtc.h diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig index 45daa8d655..bafe6ac2c9 100644 --- a/hw/rtc/Kconfig +++ b/hw/rtc/Kconfig @@ -21,3 +21,6 @@ config MC146818RTC config SUN4V_RTC bool + +config GOLDFISH_RTC + bool diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs index 8dc9fcd3a9..aa208d0d10 100644 --- a/hw/rtc/Makefile.objs +++ b/hw/rtc/Makefile.objs @@ -11,3 +11,4 @@ common-obj-$(CONFIG_EXYNOS4) += exynos4210_rtc.o obj-$(CONFIG_MC146818RTC) += mc146818rtc.o common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o +common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c new file mode 100644 index 0000000000..f71f6eaab0 --- /dev/null +++ b/hw/rtc/goldfish_rtc.c @@ -0,0 +1,288 @@ +/* + * Goldfish virtual platform RTC + * + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * For more details on Google Goldfish virtual platform refer: + * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/rtc/goldfish_rtc.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" +#include "qemu/cutils.h" +#include "qemu/log.h" + +#include "trace.h" + +#define RTC_TIME_LOW 0x00 +#define RTC_TIME_HIGH 0x04 +#define RTC_ALARM_LOW 0x08 +#define RTC_ALARM_HIGH 0x0c +#define RTC_IRQ_ENABLED 0x10 +#define RTC_CLEAR_ALARM 0x14 +#define RTC_ALARM_STATUS 0x18 +#define RTC_CLEAR_INTERRUPT 0x1c + +static void goldfish_rtc_update(GoldfishRTCState *s) +{ + qemu_set_irq(s->irq, (s->irq_pending & s->irq_enabled) ? 1 : 0); +} + +static void goldfish_rtc_interrupt(void *opaque) +{ + GoldfishRTCState *s = (GoldfishRTCState *)opaque; + + s->alarm_running = 0; + s->irq_pending = 1; + goldfish_rtc_update(s); +} + +static uint64_t goldfish_rtc_get_count(GoldfishRTCState *s) +{ + return s->tick_offset + (uint64_t)qemu_clock_get_ns(rtc_clock); +} + +static void goldfish_rtc_clear_alarm(GoldfishRTCState *s) +{ + timer_del(s->timer); + s->alarm_running = 0; +} + +static void goldfish_rtc_set_alarm(GoldfishRTCState *s) +{ + uint64_t ticks = goldfish_rtc_get_count(s); + uint64_t event = s->alarm_next; + + if (event <= ticks) { + goldfish_rtc_clear_alarm(s); + goldfish_rtc_interrupt(s); + } else { + /* + * We should be setting timer expiry to: + * qemu_clock_get_ns(rtc_clock) + (event - ticks) + * but this is equivalent to: + * event - s->tick_offset + */ + timer_mod(s->timer, event - s->tick_offset); + s->alarm_running = 1; + } +} + +static uint64_t goldfish_rtc_read(void *opaque, hwaddr offset, + unsigned size) +{ + GoldfishRTCState *s = opaque; + uint64_t r = 0; + + switch (offset) { + case RTC_TIME_LOW: + r = goldfish_rtc_get_count(s) & 0xffffffff; + break; + case RTC_TIME_HIGH: + r = goldfish_rtc_get_count(s) >> 32; + break; + case RTC_ALARM_LOW: + r = s->alarm_next & 0xffffffff; + break; + case RTC_ALARM_HIGH: + r = s->alarm_next >> 32; + break; + case RTC_IRQ_ENABLED: + r = s->irq_enabled; + break; + case RTC_ALARM_STATUS: + r = s->alarm_running; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%x\n", __func__, (uint32_t)offset); + break; + } + + trace_goldfish_rtc_read(offset, r); + + return r; +} + +static void goldfish_rtc_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + GoldfishRTCState *s = opaque; + uint64_t current_tick, new_tick; + + switch (offset) { + case RTC_TIME_LOW: + current_tick = goldfish_rtc_get_count(s); + new_tick = current_tick & (0xffffffffULL << 32); + new_tick |= value; + s->tick_offset += new_tick - current_tick; + break; + case RTC_TIME_HIGH: + current_tick = goldfish_rtc_get_count(s); + new_tick = current_tick & 0xffffffffULL; + new_tick |= (value << 32); + s->tick_offset += new_tick - current_tick; + break; + case RTC_ALARM_LOW: + s->alarm_next &= (0xffffffffULL << 32); + s->alarm_next |= value; + goldfish_rtc_set_alarm(s); + break; + case RTC_ALARM_HIGH: + s->alarm_next &= 0xffffffffULL; + s->alarm_next |= (value << 32); + break; + case RTC_IRQ_ENABLED: + s->irq_enabled = (uint32_t)(value & 0x1); + goldfish_rtc_update(s); + break; + case RTC_CLEAR_ALARM: + goldfish_rtc_clear_alarm(s); + break; + case RTC_CLEAR_INTERRUPT: + s->irq_pending = 0; + goldfish_rtc_update(s); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%x\n", __func__, (uint32_t)offset); + break; + } + + trace_goldfish_rtc_write(offset, value); +} + +static int goldfish_rtc_pre_save(void *opaque) +{ + uint64_t delta; + GoldfishRTCState *s = opaque; + + /* + * We want to migrate this offset, which sounds straightforward. + * Unfortunately, we cannot directly pass tick_offset because + * rtc_clock on destination Host might not be same source Host. + * + * To tackle, this we pass tick_offset relative to vm_clock from + * source Host and make it relative to rtc_clock at destination Host. + */ + delta = qemu_clock_get_ns(rtc_clock) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->tick_offset_vmstate = s->tick_offset + delta; + + return 0; +} + +static int goldfish_rtc_post_load(void *opaque, int version_id) +{ + uint64_t delta; + GoldfishRTCState *s = opaque; + + /* + * We extract tick_offset from tick_offset_vmstate by doing + * reverse math compared to pre_save() function. + */ + delta = qemu_clock_get_ns(rtc_clock) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->tick_offset = s->tick_offset_vmstate - delta; + + return 0; +} + +static const MemoryRegionOps goldfish_rtc_ops = { + .read = goldfish_rtc_read, + .write = goldfish_rtc_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static const VMStateDescription goldfish_rtc_vmstate = { + .name = TYPE_GOLDFISH_RTC, + .version_id = 1, + .pre_save = goldfish_rtc_pre_save, + .post_load = goldfish_rtc_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT64(tick_offset_vmstate, GoldfishRTCState), + VMSTATE_UINT64(alarm_next, GoldfishRTCState), + VMSTATE_UINT32(alarm_running, GoldfishRTCState), + VMSTATE_UINT32(irq_pending, GoldfishRTCState), + VMSTATE_UINT32(irq_enabled, GoldfishRTCState), + VMSTATE_END_OF_LIST() + } +}; + +static void goldfish_rtc_reset(DeviceState *dev) +{ + GoldfishRTCState *s = GOLDFISH_RTC(dev); + struct tm tm; + + timer_del(s->timer); + + qemu_get_timedate(&tm, 0); + s->tick_offset = mktimegm(&tm); + s->tick_offset *= NANOSECONDS_PER_SECOND; + s->tick_offset -= qemu_clock_get_ns(rtc_clock); + s->tick_offset_vmstate = 0; + s->alarm_next = 0; + s->alarm_running = 0; + s->irq_pending = 0; + s->irq_enabled = 0; +} + +static void goldfish_rtc_realize(DeviceState *d, Error **errp) +{ + SysBusDevice *dev = SYS_BUS_DEVICE(d); + GoldfishRTCState *s = GOLDFISH_RTC(d); + + memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s, + "goldfish_rtc", 0x1000); + sysbus_init_mmio(dev, &s->iomem); + + sysbus_init_irq(dev, &s->irq); + + s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s); +} + +static void goldfish_rtc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = goldfish_rtc_realize; + dc->reset = goldfish_rtc_reset; + dc->vmsd = &goldfish_rtc_vmstate; +} + +static const TypeInfo goldfish_rtc_info = { + .name = TYPE_GOLDFISH_RTC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GoldfishRTCState), + .class_init = goldfish_rtc_class_init, +}; + +static void goldfish_rtc_register_types(void) +{ + type_register_static(&goldfish_rtc_info); +} + +type_init(goldfish_rtc_register_types) diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events index d6749f4616..0bfaa26cb8 100644 --- a/hw/rtc/trace-events +++ b/hw/rtc/trace-events @@ -17,3 +17,7 @@ pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks" # aspeed-rtc.c aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 + +# goldfish_rtc.c +goldfish_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 +goldfish_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h new file mode 100644 index 0000000000..3be586bdcb --- /dev/null +++ b/include/hw/rtc/goldfish_rtc.h @@ -0,0 +1,46 @@ +/* + * Goldfish virtual platform RTC + * + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * For more details on Google Goldfish virtual platform refer: + * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_RTC_GOLDFISH_RTC_H +#define HW_RTC_GOLDFISH_RTC_H + +#include "hw/sysbus.h" + +#define TYPE_GOLDFISH_RTC "goldfish_rtc" +#define GOLDFISH_RTC(obj) \ +OBJECT_CHECK(GoldfishRTCState, (obj), TYPE_GOLDFISH_RTC) + +typedef struct GoldfishRTCState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + QEMUTimer *timer; + qemu_irq irq; + + uint64_t tick_offset; + uint64_t tick_offset_vmstate; + uint64_t alarm_next; + uint32_t alarm_running; + uint32_t irq_pending; + uint32_t irq_enabled; +} GoldfishRTCState; + +#endif -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device 2019-11-03 7:55 ` [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device Anup Patel @ 2019-11-05 23:24 ` Philippe Mathieu-Daudé 2019-11-06 6:39 ` Anup Patel 0 siblings, 1 reply; 7+ messages in thread From: Philippe Mathieu-Daudé @ 2019-11-05 23:24 UTC (permalink / raw) To: Anup Patel, Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann Cc: Atish Patra, qemu-riscv, qemu-devel, Anup Patel Hi Anup, On 11/3/19 8:55 AM, Anup Patel wrote: > This patch adds model for Google Goldfish virtual platform RTC device. > > We will be adding Goldfish RTC device to the QEMU RISC-V virt machine > for providing real date-time to Guest Linux. The corresponding Linux > driver for Goldfish RTC device is already available in upstream Linux. > > For now, VM migration support is available but untested for Goldfish RTC > device. It will be hardened in-future when we implement VM migration for > KVM RISC-V. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/rtc/Kconfig | 3 + > hw/rtc/Makefile.objs | 1 + > hw/rtc/goldfish_rtc.c | 288 ++++++++++++++++++++++++++++++++++ > hw/rtc/trace-events | 4 + > include/hw/rtc/goldfish_rtc.h | 46 ++++++ Correct path, thanks :) > 5 files changed, 342 insertions(+) > create mode 100644 hw/rtc/goldfish_rtc.c > create mode 100644 include/hw/rtc/goldfish_rtc.h > > diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig > index 45daa8d655..bafe6ac2c9 100644 > --- a/hw/rtc/Kconfig > +++ b/hw/rtc/Kconfig > @@ -21,3 +21,6 @@ config MC146818RTC > > config SUN4V_RTC > bool > + > +config GOLDFISH_RTC > + bool > diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs > index 8dc9fcd3a9..aa208d0d10 100644 > --- a/hw/rtc/Makefile.objs > +++ b/hw/rtc/Makefile.objs > @@ -11,3 +11,4 @@ common-obj-$(CONFIG_EXYNOS4) += exynos4210_rtc.o > obj-$(CONFIG_MC146818RTC) += mc146818rtc.o > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o > common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o > +common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o > diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c > new file mode 100644 > index 0000000000..f71f6eaab0 > --- /dev/null > +++ b/hw/rtc/goldfish_rtc.c > @@ -0,0 +1,288 @@ > +/* > + * Goldfish virtual platform RTC > + * > + * Copyright (C) 2019 Western Digital Corporation or its affiliates. > + * > + * For more details on Google Goldfish virtual platform refer: > + * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT I'd use a (fixed) release tag, and not the (unstable) master branch: https://android.googlesource.com/platform/external/qemu/+/refs/heads/emu-2.0-release/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "hw/rtc/goldfish_rtc.h" > +#include "migration/vmstate.h" > +#include "hw/irq.h" > +#include "hw/qdev-properties.h" > +#include "hw/sysbus.h" > +#include "qemu/timer.h" > +#include "sysemu/sysemu.h" > +#include "qemu/cutils.h" > +#include "qemu/log.h" > + > +#include "trace.h" > + > +#define RTC_TIME_LOW 0x00 > +#define RTC_TIME_HIGH 0x04 > +#define RTC_ALARM_LOW 0x08 > +#define RTC_ALARM_HIGH 0x0c > +#define RTC_IRQ_ENABLED 0x10 > +#define RTC_CLEAR_ALARM 0x14 > +#define RTC_ALARM_STATUS 0x18 > +#define RTC_CLEAR_INTERRUPT 0x1c > + > +static void goldfish_rtc_update(GoldfishRTCState *s) > +{ > + qemu_set_irq(s->irq, (s->irq_pending & s->irq_enabled) ? 1 : 0); > +} > + > +static void goldfish_rtc_interrupt(void *opaque) > +{ > + GoldfishRTCState *s = (GoldfishRTCState *)opaque; > + > + s->alarm_running = 0; > + s->irq_pending = 1; > + goldfish_rtc_update(s); > +} > + > +static uint64_t goldfish_rtc_get_count(GoldfishRTCState *s) > +{ > + return s->tick_offset + (uint64_t)qemu_clock_get_ns(rtc_clock); > +} > + > +static void goldfish_rtc_clear_alarm(GoldfishRTCState *s) > +{ > + timer_del(s->timer); > + s->alarm_running = 0; > +} > + > +static void goldfish_rtc_set_alarm(GoldfishRTCState *s) > +{ > + uint64_t ticks = goldfish_rtc_get_count(s); > + uint64_t event = s->alarm_next; > + > + if (event <= ticks) { > + goldfish_rtc_clear_alarm(s); > + goldfish_rtc_interrupt(s); > + } else { > + /* > + * We should be setting timer expiry to: > + * qemu_clock_get_ns(rtc_clock) + (event - ticks) > + * but this is equivalent to: > + * event - s->tick_offset > + */ > + timer_mod(s->timer, event - s->tick_offset); > + s->alarm_running = 1; > + } > +} > + > +static uint64_t goldfish_rtc_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + GoldfishRTCState *s = opaque; > + uint64_t r = 0; > + > + switch (offset) { > + case RTC_TIME_LOW: > + r = goldfish_rtc_get_count(s) & 0xffffffff; > + break; > + case RTC_TIME_HIGH: > + r = goldfish_rtc_get_count(s) >> 32; > + break; > + case RTC_ALARM_LOW: > + r = s->alarm_next & 0xffffffff; > + break; > + case RTC_ALARM_HIGH: > + r = s->alarm_next >> 32; > + break; > + case RTC_IRQ_ENABLED: > + r = s->irq_enabled; > + break; > + case RTC_ALARM_STATUS: > + r = s->alarm_running; > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Bad offset 0x%x\n", __func__, (uint32_t)offset); Hmm 0x20 is UNIMP. > + break; > + } > + > + trace_goldfish_rtc_read(offset, r); > + > + return r; > +} > + > +static void goldfish_rtc_write(void *opaque, hwaddr offset, > + uint64_t value, unsigned size) > +{ > + GoldfishRTCState *s = opaque; > + uint64_t current_tick, new_tick; > + > + switch (offset) { > + case RTC_TIME_LOW: > + current_tick = goldfish_rtc_get_count(s); FYI, this 2 lines ...: > + new_tick = current_tick & (0xffffffffULL << 32); > + new_tick |= value; ... can also be written as: new_tick = deposit64(current_tick, 0, 32, value); (I find this notation easier to review). > + s->tick_offset += new_tick - current_tick; > + break; > + case RTC_TIME_HIGH: > + current_tick = goldfish_rtc_get_count(s); > + new_tick = current_tick & 0xffffffffULL; > + new_tick |= (value << 32); > + s->tick_offset += new_tick - current_tick; > + break; > + case RTC_ALARM_LOW: > + s->alarm_next &= (0xffffffffULL << 32); > + s->alarm_next |= value; > + goldfish_rtc_set_alarm(s); > + break; > + case RTC_ALARM_HIGH: Ditto these ... > + s->alarm_next &= 0xffffffffULL; > + s->alarm_next |= (value << 32); ... as: s->alarm_next = deposit64(s->alarm_next, 32, 32, value); > + break; > + case RTC_IRQ_ENABLED: > + s->irq_enabled = (uint32_t)(value & 0x1); > + goldfish_rtc_update(s); > + break; > + case RTC_CLEAR_ALARM: > + goldfish_rtc_clear_alarm(s); > + break; > + case RTC_CLEAR_INTERRUPT: > + s->irq_pending = 0; > + goldfish_rtc_update(s); > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Bad offset 0x%x\n", __func__, (uint32_t)offset); 0x20 is UNIMP. > + break; > + } > + > + trace_goldfish_rtc_write(offset, value); > +} > + > +static int goldfish_rtc_pre_save(void *opaque) > +{ > + uint64_t delta; > + GoldfishRTCState *s = opaque; > + > + /* > + * We want to migrate this offset, which sounds straightforward. > + * Unfortunately, we cannot directly pass tick_offset because > + * rtc_clock on destination Host might not be same source Host. > + * > + * To tackle, this we pass tick_offset relative to vm_clock from > + * source Host and make it relative to rtc_clock at destination Host. Hmm this is the fix from commit 032cfe6a79c. > + */ > + delta = qemu_clock_get_ns(rtc_clock) - > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + s->tick_offset_vmstate = s->tick_offset + delta; > + > + return 0; > +} > + > +static int goldfish_rtc_post_load(void *opaque, int version_id) > +{ > + uint64_t delta; > + GoldfishRTCState *s = opaque; > + > + /* > + * We extract tick_offset from tick_offset_vmstate by doing > + * reverse math compared to pre_save() function. > + */ > + delta = qemu_clock_get_ns(rtc_clock) - > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + s->tick_offset = s->tick_offset_vmstate - delta; > + > + return 0; > +} > + > +static const MemoryRegionOps goldfish_rtc_ops = { > + .read = goldfish_rtc_read, > + .write = goldfish_rtc_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4 OK. > + } > +}; > + > +static const VMStateDescription goldfish_rtc_vmstate = { > + .name = TYPE_GOLDFISH_RTC, > + .version_id = 1, > + .pre_save = goldfish_rtc_pre_save, > + .post_load = goldfish_rtc_post_load, > + .fields = (VMStateField[]) { > + VMSTATE_UINT64(tick_offset_vmstate, GoldfishRTCState), > + VMSTATE_UINT64(alarm_next, GoldfishRTCState), > + VMSTATE_UINT32(alarm_running, GoldfishRTCState), > + VMSTATE_UINT32(irq_pending, GoldfishRTCState), > + VMSTATE_UINT32(irq_enabled, GoldfishRTCState), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void goldfish_rtc_reset(DeviceState *dev) > +{ > + GoldfishRTCState *s = GOLDFISH_RTC(dev); > + struct tm tm; > + > + timer_del(s->timer); > + > + qemu_get_timedate(&tm, 0); > + s->tick_offset = mktimegm(&tm); > + s->tick_offset *= NANOSECONDS_PER_SECOND; > + s->tick_offset -= qemu_clock_get_ns(rtc_clock); > + s->tick_offset_vmstate = 0; > + s->alarm_next = 0; > + s->alarm_running = 0; > + s->irq_pending = 0; > + s->irq_enabled = 0; > +} > + > +static void goldfish_rtc_realize(DeviceState *d, Error **errp) > +{ > + SysBusDevice *dev = SYS_BUS_DEVICE(d); > + GoldfishRTCState *s = GOLDFISH_RTC(d); > + > + memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s, > + "goldfish_rtc", 0x1000); The spec says this device's io region is 0x24 bytes. 0x1000 might be your SoC mapping. Restricting it to the spec allow other targets to use this device. > + sysbus_init_mmio(dev, &s->iomem); > + > + sysbus_init_irq(dev, &s->irq); > + > + s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s); > +} > + > +static void goldfish_rtc_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = goldfish_rtc_realize; > + dc->reset = goldfish_rtc_reset; > + dc->vmsd = &goldfish_rtc_vmstate; > +} > + > +static const TypeInfo goldfish_rtc_info = { > + .name = TYPE_GOLDFISH_RTC, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(GoldfishRTCState), > + .class_init = goldfish_rtc_class_init, > +}; > + > +static void goldfish_rtc_register_types(void) > +{ > + type_register_static(&goldfish_rtc_info); > +} > + > +type_init(goldfish_rtc_register_types) > diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events > index d6749f4616..0bfaa26cb8 100644 > --- a/hw/rtc/trace-events > +++ b/hw/rtc/trace-events > @@ -17,3 +17,7 @@ pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks" > # aspeed-rtc.c > aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 > aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 > + > +# goldfish_rtc.c > +goldfish_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 > +goldfish_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 You declared a region of 0x1000 bytes, shouldn't the address format be 0x%03? I'd rather use the correct region size and keep 0x02 which is enough. > diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h > new file mode 100644 > index 0000000000..3be586bdcb > --- /dev/null > +++ b/include/hw/rtc/goldfish_rtc.h > @@ -0,0 +1,46 @@ > +/* > + * Goldfish virtual platform RTC > + * > + * Copyright (C) 2019 Western Digital Corporation or its affiliates. > + * > + * For more details on Google Goldfish virtual platform refer: > + * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef HW_RTC_GOLDFISH_RTC_H > +#define HW_RTC_GOLDFISH_RTC_H > + > +#include "hw/sysbus.h" > + > +#define TYPE_GOLDFISH_RTC "goldfish_rtc" > +#define GOLDFISH_RTC(obj) \ > +OBJECT_CHECK(GoldfishRTCState, (obj), TYPE_GOLDFISH_RTC) Maybe insert some spaces before the macro to improve readability. > + > +typedef struct GoldfishRTCState { > + SysBusDevice parent_obj; > + > + MemoryRegion iomem; > + QEMUTimer *timer; > + qemu_irq irq; > + > + uint64_t tick_offset; > + uint64_t tick_offset_vmstate; > + uint64_t alarm_next; > + uint32_t alarm_running; > + uint32_t irq_pending; > + uint32_t irq_enabled; > +} GoldfishRTCState; > + > +#endif > Rest of the patch looks good. Regards, Phil. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device 2019-11-05 23:24 ` Philippe Mathieu-Daudé @ 2019-11-06 6:39 ` Anup Patel 0 siblings, 0 replies; 7+ messages in thread From: Anup Patel @ 2019-11-06 6:39 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: Peter Maydell, Palmer Dabbelt, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Anup Patel, qemu-devel, Atish Patra, Alistair Francis On Wed, Nov 6, 2019 at 4:54 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > Hi Anup, > > On 11/3/19 8:55 AM, Anup Patel wrote: > > This patch adds model for Google Goldfish virtual platform RTC device. > > > > We will be adding Goldfish RTC device to the QEMU RISC-V virt machine > > for providing real date-time to Guest Linux. The corresponding Linux > > driver for Goldfish RTC device is already available in upstream Linux. > > > > For now, VM migration support is available but untested for Goldfish RTC > > device. It will be hardened in-future when we implement VM migration for > > KVM RISC-V. > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > hw/rtc/Kconfig | 3 + > > hw/rtc/Makefile.objs | 1 + > > hw/rtc/goldfish_rtc.c | 288 ++++++++++++++++++++++++++++++++++ > > hw/rtc/trace-events | 4 + > > include/hw/rtc/goldfish_rtc.h | 46 ++++++ > > Correct path, thanks :) > > > 5 files changed, 342 insertions(+) > > create mode 100644 hw/rtc/goldfish_rtc.c > > create mode 100644 include/hw/rtc/goldfish_rtc.h > > > > diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig > > index 45daa8d655..bafe6ac2c9 100644 > > --- a/hw/rtc/Kconfig > > +++ b/hw/rtc/Kconfig > > @@ -21,3 +21,6 @@ config MC146818RTC > > > > config SUN4V_RTC > > bool > > + > > +config GOLDFISH_RTC > > + bool > > diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs > > index 8dc9fcd3a9..aa208d0d10 100644 > > --- a/hw/rtc/Makefile.objs > > +++ b/hw/rtc/Makefile.objs > > @@ -11,3 +11,4 @@ common-obj-$(CONFIG_EXYNOS4) += exynos4210_rtc.o > > obj-$(CONFIG_MC146818RTC) += mc146818rtc.o > > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o > > common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o > > +common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o > > diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c > > new file mode 100644 > > index 0000000000..f71f6eaab0 > > --- /dev/null > > +++ b/hw/rtc/goldfish_rtc.c > > @@ -0,0 +1,288 @@ > > +/* > > + * Goldfish virtual platform RTC > > + * > > + * Copyright (C) 2019 Western Digital Corporation or its affiliates. > > + * > > + * For more details on Google Goldfish virtual platform refer: > > + * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT > > I'd use a (fixed) release tag, and not the (unstable) master branch: > > https://android.googlesource.com/platform/external/qemu/+/refs/heads/emu-2.0-release/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT Sure, I will update the URL. > > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2 or later, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License along with > > + * this program. If not, see <http://www.gnu.org/licenses/>. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu-common.h" > > +#include "hw/rtc/goldfish_rtc.h" > > +#include "migration/vmstate.h" > > +#include "hw/irq.h" > > +#include "hw/qdev-properties.h" > > +#include "hw/sysbus.h" > > +#include "qemu/timer.h" > > +#include "sysemu/sysemu.h" > > +#include "qemu/cutils.h" > > +#include "qemu/log.h" > > + > > +#include "trace.h" > > + > > +#define RTC_TIME_LOW 0x00 > > +#define RTC_TIME_HIGH 0x04 > > +#define RTC_ALARM_LOW 0x08 > > +#define RTC_ALARM_HIGH 0x0c > > +#define RTC_IRQ_ENABLED 0x10 > > +#define RTC_CLEAR_ALARM 0x14 > > +#define RTC_ALARM_STATUS 0x18 > > +#define RTC_CLEAR_INTERRUPT 0x1c > > + > > +static void goldfish_rtc_update(GoldfishRTCState *s) > > +{ > > + qemu_set_irq(s->irq, (s->irq_pending & s->irq_enabled) ? 1 : 0); > > +} > > + > > +static void goldfish_rtc_interrupt(void *opaque) > > +{ > > + GoldfishRTCState *s = (GoldfishRTCState *)opaque; > > + > > + s->alarm_running = 0; > > + s->irq_pending = 1; > > + goldfish_rtc_update(s); > > +} > > + > > +static uint64_t goldfish_rtc_get_count(GoldfishRTCState *s) > > +{ > > + return s->tick_offset + (uint64_t)qemu_clock_get_ns(rtc_clock); > > +} > > + > > +static void goldfish_rtc_clear_alarm(GoldfishRTCState *s) > > +{ > > + timer_del(s->timer); > > + s->alarm_running = 0; > > +} > > + > > +static void goldfish_rtc_set_alarm(GoldfishRTCState *s) > > +{ > > + uint64_t ticks = goldfish_rtc_get_count(s); > > + uint64_t event = s->alarm_next; > > + > > + if (event <= ticks) { > > + goldfish_rtc_clear_alarm(s); > > + goldfish_rtc_interrupt(s); > > + } else { > > + /* > > + * We should be setting timer expiry to: > > + * qemu_clock_get_ns(rtc_clock) + (event - ticks) > > + * but this is equivalent to: > > + * event - s->tick_offset > > + */ > > + timer_mod(s->timer, event - s->tick_offset); > > + s->alarm_running = 1; > > + } > > +} > > + > > +static uint64_t goldfish_rtc_read(void *opaque, hwaddr offset, > > + unsigned size) > > +{ > > + GoldfishRTCState *s = opaque; > > + uint64_t r = 0; > > + > > + switch (offset) { > > + case RTC_TIME_LOW: > > + r = goldfish_rtc_get_count(s) & 0xffffffff; > > + break; > > + case RTC_TIME_HIGH: > > + r = goldfish_rtc_get_count(s) >> 32; > > + break; > > + case RTC_ALARM_LOW: > > + r = s->alarm_next & 0xffffffff; > > + break; > > + case RTC_ALARM_HIGH: > > + r = s->alarm_next >> 32; > > + break; > > + case RTC_IRQ_ENABLED: > > + r = s->irq_enabled; > > + break; > > + case RTC_ALARM_STATUS: > > + r = s->alarm_running; > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: Bad offset 0x%x\n", __func__, (uint32_t)offset); > > Hmm 0x20 is UNIMP. Sure, I will update. > > > + break; > > + } > > + > > + trace_goldfish_rtc_read(offset, r); > > + > > + return r; > > +} > > + > > +static void goldfish_rtc_write(void *opaque, hwaddr offset, > > + uint64_t value, unsigned size) > > +{ > > + GoldfishRTCState *s = opaque; > > + uint64_t current_tick, new_tick; > > + > > + switch (offset) { > > + case RTC_TIME_LOW: > > + current_tick = goldfish_rtc_get_count(s); > > FYI, this 2 lines ...: > > > + new_tick = current_tick & (0xffffffffULL << 32); > > + new_tick |= value; > > ... can also be written as: > > new_tick = deposit64(current_tick, 0, 32, value); > > (I find this notation easier to review). Sure, I will use deposite64() here and everywhere below. Thanks for this suggestion. > > > + s->tick_offset += new_tick - current_tick; > > + break; > > + case RTC_TIME_HIGH: > > + current_tick = goldfish_rtc_get_count(s); > > + new_tick = current_tick & 0xffffffffULL; > > + new_tick |= (value << 32); > > + s->tick_offset += new_tick - current_tick; > > + break; > > + case RTC_ALARM_LOW: > > + s->alarm_next &= (0xffffffffULL << 32); > > + s->alarm_next |= value; > > + goldfish_rtc_set_alarm(s); > > + break; > > + case RTC_ALARM_HIGH: > > Ditto these ... > > > + s->alarm_next &= 0xffffffffULL; > > + s->alarm_next |= (value << 32); > > ... as: > > s->alarm_next = deposit64(s->alarm_next, 32, 32, value); > > > + break; > > + case RTC_IRQ_ENABLED: > > + s->irq_enabled = (uint32_t)(value & 0x1); > > + goldfish_rtc_update(s); > > + break; > > + case RTC_CLEAR_ALARM: > > + goldfish_rtc_clear_alarm(s); > > + break; > > + case RTC_CLEAR_INTERRUPT: > > + s->irq_pending = 0; > > + goldfish_rtc_update(s); > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: Bad offset 0x%x\n", __func__, (uint32_t)offset); > > 0x20 is UNIMP. > > > + break; > > + } > > + > > + trace_goldfish_rtc_write(offset, value); > > +} > > + > > +static int goldfish_rtc_pre_save(void *opaque) > > +{ > > + uint64_t delta; > > + GoldfishRTCState *s = opaque; > > + > > + /* > > + * We want to migrate this offset, which sounds straightforward. > > + * Unfortunately, we cannot directly pass tick_offset because > > + * rtc_clock on destination Host might not be same source Host. > > + * > > + * To tackle, this we pass tick_offset relative to vm_clock from > > + * source Host and make it relative to rtc_clock at destination Host. > > Hmm this is the fix from commit 032cfe6a79c. > > > + */ > > + delta = qemu_clock_get_ns(rtc_clock) - > > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > > + s->tick_offset_vmstate = s->tick_offset + delta; > > + > > + return 0; > > +} > > + > > +static int goldfish_rtc_post_load(void *opaque, int version_id) > > +{ > > + uint64_t delta; > > + GoldfishRTCState *s = opaque; > > + > > + /* > > + * We extract tick_offset from tick_offset_vmstate by doing > > + * reverse math compared to pre_save() function. > > + */ > > + delta = qemu_clock_get_ns(rtc_clock) - > > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > > + s->tick_offset = s->tick_offset_vmstate - delta; > > + > > + return 0; > > +} > > + > > +static const MemoryRegionOps goldfish_rtc_ops = { > > + .read = goldfish_rtc_read, > > + .write = goldfish_rtc_write, > > + .endianness = DEVICE_LITTLE_ENDIAN, > > + .valid = { > > + .min_access_size = 4, > > + .max_access_size = 4 > > OK. > > > + } > > +}; > > + > > +static const VMStateDescription goldfish_rtc_vmstate = { > > + .name = TYPE_GOLDFISH_RTC, > > + .version_id = 1, > > + .pre_save = goldfish_rtc_pre_save, > > + .post_load = goldfish_rtc_post_load, > > + .fields = (VMStateField[]) { > > + VMSTATE_UINT64(tick_offset_vmstate, GoldfishRTCState), > > + VMSTATE_UINT64(alarm_next, GoldfishRTCState), > > + VMSTATE_UINT32(alarm_running, GoldfishRTCState), > > + VMSTATE_UINT32(irq_pending, GoldfishRTCState), > > + VMSTATE_UINT32(irq_enabled, GoldfishRTCState), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void goldfish_rtc_reset(DeviceState *dev) > > +{ > > + GoldfishRTCState *s = GOLDFISH_RTC(dev); > > + struct tm tm; > > + > > + timer_del(s->timer); > > + > > + qemu_get_timedate(&tm, 0); > > + s->tick_offset = mktimegm(&tm); > > + s->tick_offset *= NANOSECONDS_PER_SECOND; > > + s->tick_offset -= qemu_clock_get_ns(rtc_clock); > > + s->tick_offset_vmstate = 0; > > + s->alarm_next = 0; > > + s->alarm_running = 0; > > + s->irq_pending = 0; > > + s->irq_enabled = 0; > > +} > > + > > +static void goldfish_rtc_realize(DeviceState *d, Error **errp) > > +{ > > + SysBusDevice *dev = SYS_BUS_DEVICE(d); > > + GoldfishRTCState *s = GOLDFISH_RTC(d); > > + > > + memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s, > > + "goldfish_rtc", 0x1000); > > The spec says this device's io region is 0x24 bytes. 0x1000 might be > your SoC mapping. Restricting it to the spec allow other targets to use > this device. Sure, I will update this. > > > + sysbus_init_mmio(dev, &s->iomem); > > + > > + sysbus_init_irq(dev, &s->irq); > > + > > + s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s); > > +} > > + > > +static void goldfish_rtc_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc = DEVICE_CLASS(klass); > > + > > + dc->realize = goldfish_rtc_realize; > > + dc->reset = goldfish_rtc_reset; > > + dc->vmsd = &goldfish_rtc_vmstate; > > +} > > + > > +static const TypeInfo goldfish_rtc_info = { > > + .name = TYPE_GOLDFISH_RTC, > > + .parent = TYPE_SYS_BUS_DEVICE, > > + .instance_size = sizeof(GoldfishRTCState), > > + .class_init = goldfish_rtc_class_init, > > +}; > > + > > +static void goldfish_rtc_register_types(void) > > +{ > > + type_register_static(&goldfish_rtc_info); > > +} > > + > > +type_init(goldfish_rtc_register_types) > > diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events > > index d6749f4616..0bfaa26cb8 100644 > > --- a/hw/rtc/trace-events > > +++ b/hw/rtc/trace-events > > @@ -17,3 +17,7 @@ pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks" > > # aspeed-rtc.c > > aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 > > aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 > > + > > +# goldfish_rtc.c > > +goldfish_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 > > +goldfish_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64 > > You declared a region of 0x1000 bytes, shouldn't the address format be > 0x%03? I'd rather use the correct region size and keep 0x02 which is enough. I will update the region size so we don't need to change here. > > > diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h > > new file mode 100644 > > index 0000000000..3be586bdcb > > --- /dev/null > > +++ b/include/hw/rtc/goldfish_rtc.h > > @@ -0,0 +1,46 @@ > > +/* > > + * Goldfish virtual platform RTC > > + * > > + * Copyright (C) 2019 Western Digital Corporation or its affiliates. > > + * > > + * For more details on Google Goldfish virtual platform refer: > > + * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2 or later, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License along with > > + * this program. If not, see <http://www.gnu.org/licenses/>. > > + */ > > + > > +#ifndef HW_RTC_GOLDFISH_RTC_H > > +#define HW_RTC_GOLDFISH_RTC_H > > + > > +#include "hw/sysbus.h" > > + > > +#define TYPE_GOLDFISH_RTC "goldfish_rtc" > > +#define GOLDFISH_RTC(obj) \ > > +OBJECT_CHECK(GoldfishRTCState, (obj), TYPE_GOLDFISH_RTC) > > Maybe insert some spaces before the macro to improve readability. Okay. > > > + > > +typedef struct GoldfishRTCState { > > + SysBusDevice parent_obj; > > + > > + MemoryRegion iomem; > > + QEMUTimer *timer; > > + qemu_irq irq; > > + > > + uint64_t tick_offset; > > + uint64_t tick_offset_vmstate; > > + uint64_t alarm_next; > > + uint32_t alarm_running; > > + uint32_t irq_pending; > > + uint32_t irq_enabled; > > +} GoldfishRTCState; > > + > > +#endif > > > > Rest of the patch looks good. Thanks, Anup ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v6 2/3] riscv: virt: Use Goldfish RTC device 2019-11-03 7:55 [PATCH v6 0/3] RTC support for QEMU RISC-V virt machine Anup Patel 2019-11-03 7:55 ` [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device Anup Patel @ 2019-11-03 7:55 ` Anup Patel 2019-11-03 7:55 ` [PATCH v6 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC Anup Patel 2 siblings, 0 replies; 7+ messages in thread From: Anup Patel @ 2019-11-03 7:55 UTC (permalink / raw) To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Acked-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 15 +++++++++++++++ include/hw/riscv/virt.h | 2 ++ 3 files changed, 18 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index b12660b9f8..ff9fbe958a 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -34,6 +34,7 @@ config RISCV_VIRT select PCI select HART select SERIAL + select GOLDFISH_RTC select VIRTIO_MMIO select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cc8f311e6b..818678a4b2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -58,6 +58,7 @@ static const struct MemmapEntry { [VIRT_DEBUG] = { 0x0, 0x100 }, [VIRT_MROM] = { 0x1000, 0x11000 }, [VIRT_TEST] = { 0x100000, 0x1000 }, + [VIRT_RTC] = { 0x101000, 0x1000 }, [VIRT_CLINT] = { 0x2000000, 0x10000 }, [VIRT_PLIC] = { 0xc000000, 0x4000000 }, [VIRT_UART0] = { 0x10000000, 0x100 }, @@ -376,6 +377,17 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); + nodename = g_strdup_printf("/rtc@%lx", + (long)memmap[VIRT_RTC].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "google,goldfish-rtc"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[VIRT_RTC].base, + 0x0, memmap[VIRT_RTC].size); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ); + qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); if (cmdline) { @@ -579,6 +591,9 @@ static void riscv_virt_board_init(MachineState *machine) 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); + sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, + qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ)); + virt_flash_create(s); for (i = 0; i < ARRAY_SIZE(s->flash); i++) { diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b17048a93a..e69355efaf 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -44,6 +44,7 @@ enum { VIRT_DEBUG, VIRT_MROM, VIRT_TEST, + VIRT_RTC, VIRT_CLINT, VIRT_PLIC, VIRT_UART0, @@ -57,6 +58,7 @@ enum { enum { UART0_IRQ = 10, + RTC_IRQ = 11, VIRTIO_IRQ = 1, /* 1 to 8 */ VIRTIO_COUNT = 8, PCIE_IRQ = 0x20, /* 32 to 35 */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v6 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC 2019-11-03 7:55 [PATCH v6 0/3] RTC support for QEMU RISC-V virt machine Anup Patel 2019-11-03 7:55 ` [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device Anup Patel 2019-11-03 7:55 ` [PATCH v6 2/3] riscv: virt: Use " Anup Patel @ 2019-11-03 7:55 ` Anup Patel 2019-11-04 22:34 ` Alistair Francis 2 siblings, 1 reply; 7+ messages in thread From: Anup Patel @ 2019-11-03 7:55 UTC (permalink / raw) To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel Add myself as Goldfish RTC maintainer until someone else is willing to maintain it. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c2a68555ae..f200e985da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -558,6 +558,13 @@ F: include/hw/arm/digic.h F: hw/*/digic* F: include/hw/*/digic* +Goldfish RTC +M: Anup Patel <anup.patel@wdc.com> +L: qemu-riscv@nongnu.org +S: Maintained +F: hw/rtc/goldfish_rtc.c +F: include/hw/rtc/goldfish_rtc.h + Gumstix M: Peter Maydell <peter.maydell@linaro.org> R: Philippe Mathieu-Daud?? <f4bug@amsat.org> -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v6 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC 2019-11-03 7:55 ` [PATCH v6 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC Anup Patel @ 2019-11-04 22:34 ` Alistair Francis 0 siblings, 0 replies; 7+ messages in thread From: Alistair Francis @ 2019-11-04 22:34 UTC (permalink / raw) To: Anup Patel Cc: Peter Maydell, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, qemu-devel, Atish Patra, Alistair Francis, Anup Patel On Sun, Nov 3, 2019 at 12:55 AM Anup Patel <Anup.Patel@wdc.com> wrote: > > Add myself as Goldfish RTC maintainer until someone else is > willing to maintain it. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > MAINTAINERS | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index c2a68555ae..f200e985da 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -558,6 +558,13 @@ F: include/hw/arm/digic.h > F: hw/*/digic* > F: include/hw/*/digic* > > +Goldfish RTC > +M: Anup Patel <anup.patel@wdc.com> > +L: qemu-riscv@nongnu.org > +S: Maintained > +F: hw/rtc/goldfish_rtc.c > +F: include/hw/rtc/goldfish_rtc.h > + > Gumstix > M: Peter Maydell <peter.maydell@linaro.org> > R: Philippe Mathieu-Daud?? <f4bug@amsat.org> > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-11-06 6:40 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-11-03 7:55 [PATCH v6 0/3] RTC support for QEMU RISC-V virt machine Anup Patel 2019-11-03 7:55 ` [PATCH v6 1/3] hw: rtc: Add Goldfish RTC device Anup Patel 2019-11-05 23:24 ` Philippe Mathieu-Daudé 2019-11-06 6:39 ` Anup Patel 2019-11-03 7:55 ` [PATCH v6 2/3] riscv: virt: Use " Anup Patel 2019-11-03 7:55 ` [PATCH v6 3/3] MAINTAINERS: Add maintainer entry for Goldfish RTC Anup Patel 2019-11-04 22:34 ` Alistair Francis
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