* [ PATCH v3 00/10] Improve PMU support
@ 2021-10-25 19:55 Atish Patra
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
` (9 more replies)
0 siblings, 10 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension[2] allows the perf like tool to handle overflow interrupts and
filtering support.
This series implements full PMU infrastructure to support
PMU in virt machine. This will allow us to add any PMU events in future.
Currently, this series enables the following omu events.
1. cycle count
2. instruction count
3. DTLB load/store miss
4. ITLB prefetch miss
The first two are computed using host ticks while last three are counted during
cpu_tlb_fill. We can do both sampling and count from guest userspace.
This series has been tested on both RV64 and RV32. Both Linux[3] and Opensbi[4]
patches are required to get the perf working.
Here is an output of perf stat/report while running hackbench with OpenSBI & Linux
kernel patches applied [3].
Perf stat:
==========
[root@fedora-riscv riscv]# perf stat -e r8000000000000005 -e r8000000000000007 \
-e r8000000000000006 -e r0000000000020002 -e r0000000000020004 -e branch-misses \
-e cache-misses -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses \
-e cycles -e instructions perf bench sched messaging -g 15 -l 10 \
Running with 15*40 (== 600) tasks.
Time: 6.578
Performance counter stats for './hackbench -pipe 15 process':
1,794 r8000000000000005 (52.59%) --> SBI_PMU_FW_SET_TIMER
2,859 r8000000000000007 (60.74%) --> SBI_PMU_FW_IPI_RECVD
4,205 r8000000000000006 (68.71%) --> SBI_PMU_FW_IPI_SENT
0 r0000000000020002 (81.69%)
<not counted> r0000000000020004 (0.00%)
<not counted> branch-misses (0.00%)
<not counted> cache-misses (0.00%)
7,878,328 dTLB-load-misses (15.60%)
680,270 dTLB-store-misses (28.45%)
8,287,931 iTLB-load-misses (39.24%)
20,008,506,675 cycles (48.60%)
21,484,427,932 instructions # 1.07 insn per cycle (56.60%)
1.681344735 seconds time elapsed
0.614460000 seconds user
8.313254000 seconds sys
Perf record:
============
[root@fedora-riscv riscv]# perf record -e cycles -e instructions \
-e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses -c 10000 \
perf bench sched messaging -g 15 -l 10
# Running 'sched/messaging' benchmark:
# 20 sender and receiver processes per group
# 15 groups == 600 processes run
Total time: 1.261 [sec]
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.101 MB perf.data (845 samples) ]
[root@fedora-riscv riscv]# perf report
Available samples
407 cycles _
407 instructions _
18 dTLB-load-misses _
2 dTLB-store-misses _
11 iTLB-load-misses _
..
Changes from v2->v3:
1. Addressed all the comments on PATCH1-4.
2. Split patch1 into two separate patches.
3. Added explicit comments to explain the event types in DT node.
4. Rebased on latest Qemu.
Changes from v1->v2:
1. Dropped the ACks from v1 as signficant changes happened after v1.
2. sscofpmf support.
3. A generic counter management framework.
[1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
[2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit
[3] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
[3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
[4] https://github.com/atishp04/qemu/tree/riscv_pmu_v3
Atish Patra (10):
target/riscv: Fix PMU CSR predicate function
target/riscv: Implement PMU CSR predicate function for
target/riscv: pmu: Rename the counters extension to pmu
target/riscv: pmu: Make number of counters configurable
target/riscv: Implement mcountinhibit CSR
target/riscv: Add support for hpmcounters/hpmevents
target/riscv: Support mcycle/minstret write operation
target/riscv: Add sscofpmf extension support
target/riscv: Add few cache related PMU events
hw/riscv: virt: Add PMU DT node to the device tree
hw/riscv/virt.c | 36 ++
target/riscv/cpu.c | 14 +-
target/riscv/cpu.h | 51 ++-
target/riscv/cpu_bits.h | 59 +++
target/riscv/cpu_helper.c | 26 ++
target/riscv/csr.c | 827 +++++++++++++++++++++++++++++---------
target/riscv/machine.c | 30 +-
target/riscv/meson.build | 1 +
target/riscv/pmp.c | 1 +
target/riscv/pmu.c | 434 ++++++++++++++++++++
target/riscv/pmu.h | 37 ++
11 files changed, 1332 insertions(+), 184 deletions(-)
create mode 100644 target/riscv/pmu.c
create mode 100644 target/riscv/pmu.h
--
2.31.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-11-03 5:40 ` Alistair Francis
2021-11-04 11:00 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for Atish Patra
` (8 subsequent siblings)
9 siblings, 2 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/csr.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 23fbbd32162a..1ec776013435 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -89,8 +89,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
@@ -116,8 +117,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-11-03 5:43 ` Alistair Francis
2021-11-04 11:07 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
` (7 subsequent siblings)
9 siblings, 2 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1ec776013435..de484c74d3b4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
+ int ctr_index;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_is_32bit(env)) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
2021-10-25 19:55 ` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-11-03 5:47 ` Alistair Francis
2021-11-04 11:10 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Atish Patra
` (6 subsequent siblings)
9 siblings, 2 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e63..3b55f5ed0036 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9e55b2f5b170..ebc1a8754032 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -294,7 +294,7 @@ struct RISCVCPU {
bool ext_zbb;
bool ext_zbc;
bool ext_zbs;
- bool ext_counters;
+ bool ext_pmu;
bool ext_ifencei;
bool ext_icsr;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index de484c74d3b4..c486eeaffeb8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
- if (!cpu->cfg.ext_counters) {
+ if (!cpu->cfg.ext_pmu) {
/* The Counters extensions is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
` (2 preceding siblings ...)
2021-10-25 19:55 ` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-11-03 5:50 ` Alistair Francis
2021-11-04 11:45 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR Atish Patra
` (5 subsequent siblings)
9 siblings, 2 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented by the cpu.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++----------------
3 files changed, 65 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3b55f5ed0036..aec94101a4c0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
- DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
+ DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ebc1a8754032..d0a722e7cbe1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -294,10 +294,10 @@ struct RISCVCPU {
bool ext_zbb;
bool ext_zbc;
bool ext_zbs;
- bool ext_pmu;
bool ext_ifencei;
bool ext_icsr;
+ uint8_t pmu_num;
char *priv_spec;
char *user_spec;
char *bext_spec;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c486eeaffeb8..a7249eaf917f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -57,15 +57,45 @@ static RISCVException vs(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+static RISCVException mctr(CPURISCVState *env, int csrno)
+{
+#if !defined(CONFIG_USER_ONLY)
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ int ctr_index;
+ int base_csrno = CSR_MHPMCOUNTER3;
+
+ if (riscv_cpu_is_32bit(env) && csrno >= CSR_MCYCLEH) {
+ /* Offset for RV32 mhpmcounternh counters */
+ base_csrno += 0x80;
+ }
+ ctr_index = csrno - base_csrno;
+ if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
+ /* The PMU is not enabled or counter is out of range*/
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return RISCV_EXCP_NONE;
+#endif
+}
+
static RISCVException ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
+ int base_csrno = CSR_CYCLE;
+ bool brv32 = riscv_cpu_is_32bit(env);
+
+ if (brv32 && csrno >= CSR_CYCLEH) {
+ /* Offset for RV32 hpmcounternh counters */
+ base_csrno += 0x80;
+ }
+ ctr_index = csrno - base_csrno;
- if (!cpu->cfg.ext_pmu) {
- /* The Counters extensions is not enabled */
+ if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
+ /* The PMU is not enabled or counter is out of range */
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -93,7 +123,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (brv32) {
switch (csrno) {
case CSR_CYCLEH:
if (!get_field(env->mcounteren, COUNTEREN_CY)) {
@@ -148,7 +178,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (brv32) {
switch (csrno) {
case CSR_CYCLEH:
if (!get_field(env->hcounteren, COUNTEREN_CY) &&
@@ -1720,35 +1750,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
[CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
- [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
- [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
- [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
- [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
- [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
- [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
- [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
- [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
- [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
- [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
- [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
- [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
- [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
- [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
- [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
- [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
- [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
- [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
- [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
- [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
- [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
- [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
- [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
- [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
- [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
- [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
- [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
- [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
- [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
` (3 preceding siblings ...)
2021-10-25 19:55 ` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-11-03 5:51 ` Alistair Francis
2021-11-04 11:49 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
` (4 subsequent siblings)
9 siblings, 2 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 4 ++++
target/riscv/csr.c | 25 +++++++++++++++++++++++++
target/riscv/machine.c | 5 +++--
4 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0a722e7cbe1..b421eefa623f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -217,6 +217,8 @@ struct CPURISCVState {
target_ulong scounteren;
target_ulong mcounteren;
+ target_ulong mcountinhibit;
+
target_ulong sscratch;
target_ulong mscratch;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee2d..72b1485e621f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -275,6 +275,10 @@
#define CSR_MHPMCOUNTER29 0xb1d
#define CSR_MHPMCOUNTER30 0xb1e
#define CSR_MHPMCOUNTER31 0xb1f
+
+/* Machine counter-inhibit register */
+#define CSR_MCOUNTINHIBIT 0x320
+
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a7249eaf917f..faf02e12ec34 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -766,6 +766,28 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ *val = env->mcountinhibit;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ env->mcountinhibit = val;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1780,6 +1802,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
[CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
+ write_mcountinhibit },
+
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 16a08302daff..20dea0843604 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mtval, RISCVCPU),
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
` (4 preceding siblings ...)
2021-10-25 19:55 ` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation Atish Patra
` (3 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu.h | 12 ++
target/riscv/csr.c | 468 ++++++++++++++++++++++++++++-------------
target/riscv/machine.c | 3 +
3 files changed, 331 insertions(+), 152 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b421eefa623f..e7dc90d001ac 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -103,6 +103,9 @@ typedef struct CPURISCVState CPURISCVState;
#define RV_VLEN_MAX 256
+#define RV_MAX_MHPMEVENTS 29
+#define RV_MAX_MHPMCOUNTERS 32
+
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
@@ -219,6 +222,15 @@ struct CPURISCVState {
target_ulong mcountinhibit;
+ /* PMU counter configured values */
+ target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS];
+
+ /* for RV32 */
+ target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS];
+
+ /* PMU event selector configured values */
+ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
+
target_ulong sscratch;
target_ulong mscratch;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index faf02e12ec34..6757543090be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -79,6 +79,15 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
#endif
}
+static RISCVException mctr32(CPURISCVState *env, int csrno)
+{
+ if (!riscv_cpu_is_32bit(env)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return mctr(env, csrno);
+}
+
static RISCVException ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
@@ -426,6 +435,7 @@ static RISCVException read_instret(CPURISCVState *env, int csrno,
#else
*val = cpu_get_host_ticks();
#endif
+
return RISCV_EXCP_NONE;
}
@@ -441,9 +451,76 @@ static RISCVException read_instreth(CPURISCVState *env, int csrno,
#else
*val = cpu_get_host_ticks() >> 32;
#endif
+
+ return RISCV_EXCP_NONE;
+}
+
+static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int evt_index = csrno - CSR_MHPMEVENT3;
+
+ *val = env->mhpmevent_val[evt_index];
+
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
+{
+ int evt_index = csrno - CSR_MHPMEVENT3;
+
+ env->mhpmevent_val[evt_index] = val;
+
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
+{
+ int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
+
+ env->mhpmcounter_val[ctr_index] = val;
+
return RISCV_EXCP_NONE;
}
+static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
+{
+ int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
+
+ env->mhpmcounterh_val[ctr_index] = val;
+
+ return RISCV_EXCP_NONE;
+}
+
+static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int ctr_index;
+
+ if (env->priv == PRV_M) {
+ ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
+ } else {
+ ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
+ }
+ *val = env->mhpmcounter_val[ctr_index];
+
+ return RISCV_EXCP_NONE;
+}
+
+static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int ctr_index;
+
+ if (env->priv == PRV_M) {
+ ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
+ } else {
+ ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
+ }
+
+ *val = env->mhpmcounterh_val[ctr_index];
+
+ return RISCV_EXCP_NONE;
+}
+
+
#if defined(CONFIG_USER_ONLY)
static RISCVException read_time(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -1742,157 +1819,244 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
/* Performance Counters */
- [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
- [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
- [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
- [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
- [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
- [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
- [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
- [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
- [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
- [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
- [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
- [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
- [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
- [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
- [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
- [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
- [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
- [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
- [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
- [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
- [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
- [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
- [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
- [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
- [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
- [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
- [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
- [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
- [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
-
- [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
- [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
- [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
- [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
- [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
- [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
- [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
- [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
- [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
- [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
- [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
- [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
- [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
- [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
- [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
- [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
- [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
- [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
- [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
- [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
- [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
- [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
- [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
- [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
- [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
- [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
- [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
- [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
- [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
-
- [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
- write_mcountinhibit },
-
- [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
- [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
- [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
- [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
- [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
- [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
- [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
- [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
- [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
- [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
- [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
- [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
- [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
- [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
- [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
- [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
- [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
- [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
- [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
- [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
- [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
- [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
- [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
- [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
- [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
- [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
- [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
- [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
- [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
-
- [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
- [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
- [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
- [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
- [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
- [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
- [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
- [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
- [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
- [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
- [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
- [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
- [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
- [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
- [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
- [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
- [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
- [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
- [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
- [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
- [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
- [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
- [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
- [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
- [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
- [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
- [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
- [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
- [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
-
- [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
- [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
- [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
- [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
- [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
- [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
- [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
- [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
- [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
- [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
- [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
- [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
- [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
- [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
- [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
- [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
- [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
- [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
- [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
- [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
- [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
- [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
- [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
- [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
- [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
- [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
- [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
- [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
- [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
+ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter },
+
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter,
+ write_mhpmcounter },
+
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
+ write_mcountinhibit },
+
+ [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
+ write_mhpmevent },
+
+ [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh },
+
+ [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 20dea0843604..a2b32064b07a 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -178,6 +178,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
+ VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
` (5 preceding siblings ...)
2021-10-25 19:55 ` [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support Atish Patra
` (2 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret through generic counter infrastructure.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu.h | 24 +++++--
target/riscv/csr.c | 144 ++++++++++++++++++++++++++-------------
target/riscv/machine.c | 26 ++++++-
target/riscv/meson.build | 1 +
target/riscv/pmu.c | 32 +++++++++
target/riscv/pmu.h | 28 ++++++++
6 files changed, 200 insertions(+), 55 deletions(-)
create mode 100644 target/riscv/pmu.c
create mode 100644 target/riscv/pmu.h
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e7dc90d001ac..da34614ad788 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -103,7 +103,7 @@ typedef struct CPURISCVState CPURISCVState;
#define RV_VLEN_MAX 256
-#define RV_MAX_MHPMEVENTS 29
+#define RV_MAX_MHPMEVENTS 32
#define RV_MAX_MHPMCOUNTERS 32
FIELD(VTYPE, VLMUL, 0, 2)
@@ -112,6 +112,19 @@ FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
+typedef struct PMUCTRState PMUCTRState;
+struct PMUCTRState {
+ /* Current value of a counter */
+ target_ulong mhpmcounter_val;
+ /* Current value of a counter in RV32*/
+ target_ulong mhpmcounterh_val;
+ /* Snapshot values of counter */
+ target_ulong mhpmcounter_prev;
+ /* Snapshort value of a counter in RV32 */
+ target_ulong mhpmcounterh_prev;
+ bool started;
+};
+
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
@@ -222,13 +235,10 @@ struct CPURISCVState {
target_ulong mcountinhibit;
- /* PMU counter configured values */
- target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS];
-
- /* for RV32 */
- target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS];
+ /* PMU counter state */
+ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
- /* PMU event selector configured values */
+ /* PMU event selector configured values. First three are unused*/
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
target_ulong sscratch;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6757543090be..1ce1bb0868d7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "pmu.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
@@ -423,41 +424,33 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno,
}
/* User Timers and Counters */
-static RISCVException read_instret(CPURISCVState *env, int csrno,
- target_ulong *val)
+static target_ulong get_icount_ticks(bool brv32)
{
+ int64_t val;
+ target_ulong result;
+
#if !defined(CONFIG_USER_ONLY)
if (icount_enabled()) {
- *val = icount_get();
+ val = icount_get();
} else {
- *val = cpu_get_host_ticks();
+ val = cpu_get_host_ticks();
}
#else
- *val = cpu_get_host_ticks();
+ val = cpu_get_host_ticks();
#endif
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_instreth(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
-#if !defined(CONFIG_USER_ONLY)
- if (icount_enabled()) {
- *val = icount_get() >> 32;
+ if (brv32) {
+ result = val >> 32;
} else {
- *val = cpu_get_host_ticks() >> 32;
+ result = val;
}
-#else
- *val = cpu_get_host_ticks() >> 32;
-#endif
- return RISCV_EXCP_NONE;
+ return result;
}
static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
{
- int evt_index = csrno - CSR_MHPMEVENT3;
+ int evt_index = csrno - CSR_MCOUNTINHIBIT;
*val = env->mhpmevent_val[evt_index];
@@ -466,7 +459,7 @@ static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
{
- int evt_index = csrno - CSR_MHPMEVENT3;
+ int evt_index = csrno - CSR_MCOUNTINHIBIT;
env->mhpmevent_val[evt_index] = val;
@@ -475,52 +468,99 @@ static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
{
- int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
+ int ctr_idx = csrno - CSR_MCYCLE;
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
- env->mhpmcounter_val[ctr_index] = val;
+ counter->mhpmcounter_val = val;
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
+ counter->mhpmcounter_prev = get_icount_ticks(false);
+ } else {
+ /* Other counters can keep incrementing from the given value */
+ counter->mhpmcounter_prev = val;
+ }
- return RISCV_EXCP_NONE;
+ return RISCV_EXCP_NONE;
}
static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
{
- int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
+ int ctr_idx = csrno - CSR_MCYCLEH;
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
+
+ counter->mhpmcounterh_val = val;
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
+ counter->mhpmcounterh_prev = get_icount_ticks(false);
+ } else {
+ counter->mhpmcounterh_prev = val;
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
+ bool is_uh, uint32_t ctr_idx)
+{
+ PMUCTRState counter = env->pmu_ctrs[ctr_idx];
+ target_ulong ctr_prev = is_uh ? counter.mhpmcounterh_prev :
+ counter.mhpmcounter_prev;
+ target_ulong ctr_val = is_uh ? counter.mhpmcounterh_val :
+ counter.mhpmcounter_val;
- env->mhpmcounterh_val[ctr_index] = val;
+ if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
+ /**
+ * Counter should not increment if inhibit bit is set. We can't really
+ * stop the icount counting. Just return the previous value to indicate
+ * that counter was not incremented.
+ */
+ if (!counter.started) {
+ *val = ctr_val;
+ return RISCV_EXCP_NONE;
+ } else {
+ /* Mark that the counter has been stopped */
+ counter.started = false;
+ }
+ }
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
+ *val = get_icount_ticks(is_uh);
+ } else {
+ *val = ctr_val;
+ }
+
+ /* No need to handle the overflow here */
+ *val = *val - ctr_prev + ctr_val;
return RISCV_EXCP_NONE;
}
static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
{
- int ctr_index;
+ uint16_t ctr_index;
if (env->priv == PRV_M) {
- ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
+ ctr_index = csrno - CSR_MCYCLE;
} else {
- ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
+ ctr_index = csrno - CSR_CYCLE;
}
- *val = env->mhpmcounter_val[ctr_index];
- return RISCV_EXCP_NONE;
+ return riscv_pmu_read_ctr(env, val, false, ctr_index);
}
static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
{
- int ctr_index;
+ uint16_t ctr_index;
if (env->priv == PRV_M) {
- ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
+ ctr_index = csrno - CSR_MCYCLEH;
} else {
- ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
+ ctr_index = csrno - CSR_CYCLEH;
}
- *val = env->mhpmcounterh_val[ctr_index];
-
- return RISCV_EXCP_NONE;
+ return riscv_pmu_read_ctr(env, val, true, ctr_index);
}
-
#if defined(CONFIG_USER_ONLY)
static RISCVException read_time(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -857,11 +897,23 @@ static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
target_ulong val)
{
+ int cidx;
+ PMUCTRState *counter;
+
if (env->priv_ver < PRIV_VERSION_1_11_0) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->mcountinhibit = val;
+
+ /* Check if any other counter is also monitoring cycles/instructions */
+ for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
+ if (!get_field(env->mcountinhibit, BIT(cidx))) {
+ counter = &env->pmu_ctrs[cidx];
+ counter->started = true;
+ }
+ }
+
return RISCV_EXCP_NONE;
}
@@ -1708,10 +1760,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
/* User Timers and Counters */
- [CSR_CYCLE] = { "cycle", ctr, read_instret },
- [CSR_INSTRET] = { "instret", ctr, read_instret },
- [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
- [CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
+ [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
+ [CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
+ [CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh },
+ [CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh },
/*
* In privileged mode, the monitor will have to emulate TIME CSRs only if
@@ -1722,10 +1774,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
- [CSR_MCYCLE] = { "mcycle", any, read_instret },
- [CSR_MINSTRET] = { "minstret", any, read_instret },
- [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
- [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
+ [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter},
+ [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter},
+ [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh},
+ [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh},
/* Machine Information Registers */
[CSR_MVENDORID] = { "mvendorid", any, read_zero },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index a2b32064b07a..e0a489c20e67 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -84,6 +84,13 @@ static bool vector_needed(void *opaque)
return riscv_has_ext(env, RVV);
}
+static bool pmu_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+
+ return cpu->cfg.ext_pmu;
+}
+
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
.version_id = 1,
@@ -138,6 +145,21 @@ static const VMStateDescription vmstate_hyper = {
}
};
+static const VMStateDescription vmstate_pmu_ctr_state = {
+ .name = "cpu/pmu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pmu_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
+ VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
+ VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
+ VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
+ VMSTATE_BOOL(started, PMUCTRState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
@@ -178,8 +200,8 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
- VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
- VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
+ VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
+ vmstate_pmu_ctr_state, PMUCTRState),
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index d5e0bc93ea9c..992122c4d6f5 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -24,6 +24,7 @@ riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
'arch_dump.c',
'pmp.c',
+ 'pmu.c',
'monitor.c',
'machine.c'
))
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
new file mode 100644
index 000000000000..000fe8da45ef
--- /dev/null
+++ b/target/riscv/pmu.c
@@ -0,0 +1,32 @@
+/*
+ * RISC-V PMU file.
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "pmu.h"
+
+bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
+ uint32_t target_ctr)
+{
+ return (target_ctr == 0) ? true : false;
+}
+
+bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
+{
+ return (target_ctr == 2) ? true : false;
+}
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
new file mode 100644
index 000000000000..58a5bc3a4089
--- /dev/null
+++ b/target/riscv/pmu.h
@@ -0,0 +1,28 @@
+/*
+ * RISC-V PMU header file.
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "cpu.h"
+#include "qemu/main-loop.h"
+#include "exec/exec-all.h"
+
+bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
+ uint32_t target_ctr);
+bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
+ uint32_t target_ctr);
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
` (6 preceding siblings ...)
2021-10-25 19:55 ` [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation Atish Patra
@ 2021-10-25 19:55 ` Atish Patra
2021-12-27 4:37 ` Frank Chang
2021-10-25 19:56 ` [ PATCH v3 09/10] target/riscv: Add few cache related PMU events Atish Patra
2021-10-25 19:56 ` [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
9 siblings, 1 reply; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:55 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension. As the extension doesn't have any
provision for the overflow bit for fixed counters, the fixed events
can also be monitoring using programmable counters. The underlying
counters for cycle and instruction counters are always running. Thus,
a separate timer device is programmed to handle the overflow.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu.c | 12 ++
target/riscv/cpu.h | 25 +++
target/riscv/cpu_bits.h | 55 +++++++
target/riscv/csr.c | 150 +++++++++++++++++-
target/riscv/machine.c | 2 +-
target/riscv/pmu.c | 343 +++++++++++++++++++++++++++++++++++++++-
target/riscv/pmu.h | 9 ++
7 files changed, 589 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aec94101a4c0..757c646037bb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -22,6 +22,7 @@
#include "qemu/ctype.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "pmu.h"
#include "internals.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
@@ -535,6 +536,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_misa(env, target_misa);
}
+ if (cpu->cfg.pmu_num) {
+ if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscof) {
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ riscv_pmu_timer_cb, cpu);
+ if (!cpu->pmu_timer) {
+ cpu->cfg.ext_sscof = false;
+ }
+ }
+ }
+
riscv_cpu_register_gdb_regs_for_features(cs);
qemu_init_vcpu(cs);
@@ -599,6 +610,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
+ DEFINE_PROP_BOOL("sscof", RISCVCPU, cfg.ext_sscof, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index da34614ad788..b66d8acff109 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -123,6 +123,8 @@ struct PMUCTRState {
/* Snapshort value of a counter in RV32 */
target_ulong mhpmcounterh_prev;
bool started;
+ /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
+ target_ulong irq_overflow_left;
};
struct CPURISCVState {
@@ -241,6 +243,9 @@ struct CPURISCVState {
/* PMU event selector configured values. First three are unused*/
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
+ /* PMU event selector configured values for RV32*/
+ target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
+
target_ulong sscratch;
target_ulong mscratch;
@@ -320,6 +325,7 @@ struct RISCVCPU {
bool ext_zbs;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_sscof;
uint8_t pmu_num;
char *priv_spec;
@@ -333,6 +339,12 @@ struct RISCVCPU {
bool epmp;
uint64_t resetvec;
} cfg;
+
+ QEMUTimer *pmu_timer;
+ /* A bitmask of Available programmable counters */
+ uint32_t pmu_avail_ctrs;
+ /* Mapping of events to counters */
+ GHashTable *pmu_event_ctr_map;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
@@ -528,6 +540,19 @@ enum {
CSR_TABLE_SIZE = 0x1000
};
+/**
+ * The event id are encoded based on the encoding specified in the
+ * SBI specification v0.3
+ */
+
+enum riscv_pmu_event_idx {
+ RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
+ RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
+ RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
+ RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
+ RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
+};
+
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 72b1485e621f..cd6523c1c6ee 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -308,6 +308,37 @@
#define CSR_MHPMEVENT29 0x33d
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
+
+#define CSR_MHPMEVENT3H 0x723
+#define CSR_MHPMEVENT4H 0x724
+#define CSR_MHPMEVENT5H 0x725
+#define CSR_MHPMEVENT6H 0x726
+#define CSR_MHPMEVENT7H 0x727
+#define CSR_MHPMEVENT8H 0x728
+#define CSR_MHPMEVENT9H 0x729
+#define CSR_MHPMEVENT10H 0x72a
+#define CSR_MHPMEVENT11H 0x72b
+#define CSR_MHPMEVENT12H 0x72c
+#define CSR_MHPMEVENT13H 0x72d
+#define CSR_MHPMEVENT14H 0x72e
+#define CSR_MHPMEVENT15H 0x72f
+#define CSR_MHPMEVENT16H 0x730
+#define CSR_MHPMEVENT17H 0x731
+#define CSR_MHPMEVENT18H 0x732
+#define CSR_MHPMEVENT19H 0x733
+#define CSR_MHPMEVENT20H 0x734
+#define CSR_MHPMEVENT21H 0x735
+#define CSR_MHPMEVENT22H 0x736
+#define CSR_MHPMEVENT23H 0x737
+#define CSR_MHPMEVENT24H 0x738
+#define CSR_MHPMEVENT25H 0x739
+#define CSR_MHPMEVENT26H 0x73a
+#define CSR_MHPMEVENT27H 0x73b
+#define CSR_MHPMEVENT28H 0x73c
+#define CSR_MHPMEVENT29H 0x73d
+#define CSR_MHPMEVENT30H 0x73e
+#define CSR_MHPMEVENT31H 0x73f
+
#define CSR_MHPMCOUNTER3H 0xb83
#define CSR_MHPMCOUNTER4H 0xb84
#define CSR_MHPMCOUNTER5H 0xb85
@@ -338,6 +369,8 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+#define CSR_SCOUNTOVF 0xda0
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -508,6 +541,7 @@ typedef enum RISCVException {
#define IRQ_S_EXT 9
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
+#define IRQ_PMU_OVF 13
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
@@ -522,11 +556,13 @@ typedef enum RISCVException {
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_VSEIP (1 << IRQ_VS_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
+#define MIP_LCOFIP (1 << IRQ_PMU_OVF)
/* sip masks */
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
#define SIP_SEIP MIP_SEIP
+#define SIP_LCOFIP MIP_LCOFIP
/* MIE masks */
#define MIE_SEIE (1 << IRQ_S_EXT)
@@ -535,4 +571,23 @@ typedef enum RISCVException {
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+#define MIE_LCOFIE (1 << IRQ_PMU_OVF)
+
+#define MHPMEVENT_BIT_OF BIT(63)
+#define MHPMEVENTH_BIT_OF BIT(31)
+#define MHPMEVENT_BIT_MINH BIT(62)
+#define MHPMEVENTH_BIT_MINH BIT(30)
+#define MHPMEVENT_BIT_SINH BIT(61)
+#define MHPMEVENTH_BIT_SINH BIT(29)
+#define MHPMEVENT_BIT_UINH BIT(60)
+#define MHPMEVENTH_BIT_UINH BIT(28)
+#define MHPMEVENT_BIT_VSINH BIT(59)
+#define MHPMEVENTH_BIT_VSINH BIT(27)
+#define MHPMEVENT_BIT_VUINH BIT(58)
+#define MHPMEVENTH_BIT_VUINH BIT(26)
+
+#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
+#define MHPMEVENT_IDX_MASK 0xFFFFF
+#define MHPMEVENT_SSCOF_RESVD 16
+
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1ce1bb0868d7..6a1580c4b6ce 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -89,6 +89,19 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
return mctr(env, csrno);
}
+static RISCVException sscof(CPURISCVState *env, int csrno)
+{
+ #if !defined(CONFIG_USER_ONLY)
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ if (!cpu->cfg.ext_sscof) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#endif
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
@@ -104,11 +117,18 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
ctr_index = csrno - base_csrno;
- if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
+ if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
+ (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
+ goto skip_ext_pmu_check;
+ }
+
+ if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) {
/* The PMU is not enabled or counter is out of range */
return RISCV_EXCP_ILLEGAL_INST;
}
+skip_ext_pmu_check:
+
if (env->priv == PRV_S) {
switch (csrno) {
case CSR_CYCLE:
@@ -424,7 +444,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno,
}
/* User Timers and Counters */
-static target_ulong get_icount_ticks(bool brv32)
+target_ulong get_icount_ticks(bool brv32)
{
int64_t val;
target_ulong result;
@@ -461,11 +481,36 @@ static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
{
int evt_index = csrno - CSR_MCOUNTINHIBIT;
+ if (!riscv_cpu_is_32bit(env)) {
+ riscv_pmu_update_event_map(env, val, evt_index);
+ }
env->mhpmevent_val[evt_index] = val;
return RISCV_EXCP_NONE;
}
+static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int evt_index = csrno - CSR_MHPMEVENT3H + 3;
+
+ *val = env->mhpmevent_val[evt_index];
+
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val)
+{
+ int evt_index = csrno - CSR_MHPMEVENT3H + 3;
+ uint64_t mhpmevth_val = val;
+ uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
+
+ mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
+ riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
+ env->mhpmeventh_val[evt_index] = val;
+
+ return RISCV_EXCP_NONE;
+}
+
static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
{
int ctr_idx = csrno - CSR_MCYCLE;
@@ -475,6 +520,9 @@ static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
counter->mhpmcounter_prev = get_icount_ticks(false);
+ if (ctr_idx > 2) {
+ riscv_pmu_setup_timer(env, val, ctr_idx);
+ }
} else {
/* Other counters can keep incrementing from the given value */
counter->mhpmcounter_prev = val;
@@ -487,11 +535,17 @@ static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
{
int ctr_idx = csrno - CSR_MCYCLEH;
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
+ uint64_t mhpmctr_val = counter->mhpmcounter_val;
+ uint64_t mhpmctrh_val = val;
counter->mhpmcounterh_val = val;
+ mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32);
if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
counter->mhpmcounterh_prev = get_icount_ticks(false);
+ if (ctr_idx > 2) {
+ riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);
+ }
} else {
counter->mhpmcounterh_prev = val;
}
@@ -561,6 +615,32 @@ static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
return riscv_pmu_read_ctr(env, val, true, ctr_index);
}
+static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
+ int i;
+ *val = 0;
+ target_ulong *mhpm_evt_val;
+ uint64_t of_bit_mask;
+
+ if (riscv_cpu_is_32bit(env)) {
+ mhpm_evt_val = env->mhpmeventh_val;
+ of_bit_mask = MHPMEVENTH_BIT_OF;
+ } else {
+ mhpm_evt_val = env->mhpmevent_val;
+ of_bit_mask = MHPMEVENT_BIT_OF;
+ }
+
+ for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
+ if ((get_field(env->mcounteren, BIT(i))) &&
+ (mhpm_evt_val[i] & of_bit_mask)) {
+ *val |= BIT(i);
+ }
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
#if defined(CONFIG_USER_ONLY)
static RISCVException read_time(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -607,7 +687,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
/* Machine constants */
#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
-#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
+#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP | MIP_LCOFIP)
#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
@@ -645,7 +725,8 @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR;
-static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
+static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
+ SIP_LCOFIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
@@ -2022,6 +2103,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
write_mhpmevent },
+ [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+ [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscof, read_mhpmeventh,
+ write_mhpmeventh},
+
[CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
[CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
[CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh },
@@ -2110,5 +2250,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
write_mhpmcounterh },
[CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
write_mhpmcounterh },
+ [CSR_SCOUNTOVF] = { "scountovf", sscof, read_scountovf },
+
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index e0a489c20e67..7b2ef17904a9 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -88,7 +88,7 @@ static bool pmu_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
- return cpu->cfg.ext_pmu;
+ return cpu->cfg.pmu_num;
}
static const VMStateDescription vmstate_vector = {
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 000fe8da45ef..25bdbdf48ff7 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -20,13 +20,352 @@
#include "cpu.h"
#include "pmu.h"
+#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
+
+static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
+{
+ if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||
+ !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx)
+{
+ CPURISCVState *env = &cpu->env;
+
+ if (!riscv_pmu_counter_valid(cpu, ctr_idx) ||
+ !get_field(env->mcounteren, BIT(ctr_idx))) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
+{
+ CPURISCVState *env = &cpu->env;
+ target_ulong max_val = UINT32_MAX;
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
+
+ /* Privilege mode filtering */
+ if ((env->priv == PRV_M &&
+ (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) ||
+ (env->priv == PRV_S &&
+ (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) ||
+ (env->priv == PRV_U &&
+ (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) {
+ return 0;
+ }
+
+ /* Handle the overflow scenario */
+ if (counter->mhpmcounter_val == max_val) {
+ if (counter->mhpmcounterh_val == max_val) {
+ counter->mhpmcounter_val = 0;
+ counter->mhpmcounterh_val = 0;
+ /* Generate interrupt only if OF bit is clear */
+ if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
+ env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
+ riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+ }
+ } else {
+ counter->mhpmcounterh_val++;
+ }
+ } else {
+ counter->mhpmcounter_val++;
+ }
+
+ return 0;
+}
+
+static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
+{
+ CPURISCVState *env = &cpu->env;
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
+ uint64_t max_val = UINT64_MAX;
+
+ /* Privilege mode filtering */
+ if ((env->priv == PRV_M &&
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) ||
+ (env->priv == PRV_S &&
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) ||
+ (env->priv == PRV_U &&
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) {
+ return 0;
+ }
+
+ /* Handle the overflow scenario */
+ if (counter->mhpmcounter_val == max_val) {
+ counter->mhpmcounter_val = 0;
+ /* Generate interrupt only if OF bit is clear */
+ if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
+ env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
+ riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+ }
+ } else {
+ counter->mhpmcounter_val++;
+ }
+ return 0;
+}
+
+int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)
+{
+ uint32_t ctr_idx;
+ int ret;
+ CPURISCVState *env = &cpu->env;
+ gpointer value;
+
+ value = g_hash_table_lookup(cpu->pmu_event_ctr_map,
+ GUINT_TO_POINTER(event_idx));
+ if (!value) {
+ return -1;
+ }
+
+ ctr_idx = GPOINTER_TO_UINT(value);
+ if (!riscv_pmu_counter_enabled(cpu, ctr_idx) ||
+ get_field(env->mcountinhibit, BIT(ctr_idx))) {
+ return -1;
+ }
+
+ if (riscv_cpu_is_32bit(env)) {
+ ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx);
+ } else {
+ ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx);
+ }
+
+ return ret;
+}
+
bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
uint32_t target_ctr)
{
- return (target_ctr == 0) ? true : false;
+ RISCVCPU *cpu;
+ uint32_t event_idx;
+ uint32_t ctr_idx;
+
+ /* Fixed instret counter */
+ if (target_ctr == 2) {
+ return true;
+ }
+
+ cpu = RISCV_CPU(env_cpu(env));
+ event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS;
+ ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
+ GUINT_TO_POINTER(event_idx)));
+ if (!ctr_idx) {
+ return false;
+ }
+
+ return target_ctr == ctr_idx ? true : false;
}
bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
{
- return (target_ctr == 2) ? true : false;
+ RISCVCPU *cpu;
+ uint32_t event_idx;
+ uint32_t ctr_idx;
+
+ /* Fixed mcycle counter */
+ if (target_ctr == 0) {
+ return true;
+ }
+
+ cpu = RISCV_CPU(env_cpu(env));
+ event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES;
+ ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
+ GUINT_TO_POINTER(event_idx)));
+
+ /* Counter zero is not used for event_ctr_map */
+ if (!ctr_idx) {
+ return false;
+ }
+
+ return (target_ctr == ctr_idx) ? true : false;
+}
+
+static gboolean pmu_remove_event_map(gpointer key, gpointer value,
+ gpointer udata)
+{
+ return (GPOINTER_TO_UINT(value) == GPOINTER_TO_UINT(udata)) ? true : false;
+}
+
+static int64_t pmu_icount_ticks_to_ns(int64_t value)
+{
+ int64_t ret = 0;
+
+ if (icount_enabled()) {
+ ret = icount_to_ns(value);
+ } else {
+ ret = (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value;
+ }
+
+ return ret;
+}
+
+int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
+ uint32_t ctr_idx)
+{
+ uint32_t event_idx;
+ RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+
+ if (!riscv_pmu_counter_valid(cpu, ctr_idx)) {
+ return -1;
+ }
+
+ /**
+ * Expected mhpmevent value is zero for reset case. Remove the current
+ * mapping.
+ */
+ if (!value) {
+ g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
+ pmu_remove_event_map,
+ GUINT_TO_POINTER(ctr_idx));
+ return 0;
+ }
+
+ event_idx = value & MHPMEVENT_IDX_MASK;
+ if (g_hash_table_lookup(cpu->pmu_event_ctr_map,
+ GUINT_TO_POINTER(event_idx))) {
+ return 0;
+ }
+
+ switch (event_idx) {
+ case RISCV_PMU_EVENT_HW_CPU_CYCLES:
+ case RISCV_PMU_EVENT_HW_INSTRUCTIONS:
+ case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS:
+ case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS:
+ case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS:
+ break;
+ default:
+ /* We don't support any raw events right now */
+ return -1;
+ }
+ g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx),
+ GUINT_TO_POINTER(ctr_idx));
+
+ return 0;
+}
+
+static void pmu_timer_trigger_irq(RISCVCPU *cpu,
+ enum riscv_pmu_event_idx evt_idx)
+{
+ uint32_t ctr_idx;
+ CPURISCVState *env = &cpu->env;
+ PMUCTRState *counter;
+ target_ulong *mhpmevent_val;
+ uint64_t of_bit_mask;
+ int64_t irq_trigger_at;
+
+ if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES &&
+ evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) {
+ return;
+ }
+
+ ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
+ GUINT_TO_POINTER(evt_idx)));
+ if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {
+ return;
+ }
+
+ if (riscv_cpu_is_32bit(env)) {
+ mhpmevent_val = &env->mhpmeventh_val[ctr_idx];
+ of_bit_mask = MHPMEVENTH_BIT_OF;
+ } else {
+ mhpmevent_val = &env->mhpmevent_val[ctr_idx];
+ of_bit_mask = MHPMEVENT_BIT_OF;
+ }
+
+ counter = &env->pmu_ctrs[ctr_idx];
+ if (counter->irq_overflow_left > 0) {
+ irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ counter->irq_overflow_left;
+ timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at);
+ counter->irq_overflow_left = 0;
+ return;
+ }
+
+ if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) {
+ /* Generate interrupt only if OF bit is clear */
+ if (!(*mhpmevent_val & of_bit_mask)) {
+ *mhpmevent_val |= of_bit_mask;
+ riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+ }
+ }
+}
+
+/* Timer callback for instret and cycle counter overflow */
+void riscv_pmu_timer_cb(void *priv)
+{
+ RISCVCPU *cpu = priv;
+
+ /* Timer event was triggered only for these events */
+ pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES);
+ pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS);
+}
+
+int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
+{
+ uint64_t overflow_delta, overflow_at;
+ int64_t overflow_ns, overflow_left = 0;
+ RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
+
+ if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscof) {
+ return -1;
+ }
+
+ if (value) {
+ overflow_delta = UINT64_MAX - value + 1;
+ } else {
+ overflow_delta = UINT64_MAX - value;
+ }
+
+ /**
+ * QEMU supports only int64_t timers while RISC-V counters are uint64_t.
+ * Compute the leftover and save it so that it can be reprogrammed again
+ * when timer expires.
+ */
+ if (overflow_delta > INT64_MAX) {
+ overflow_left = overflow_delta - INT64_MAX;
+ }
+
+ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
+ riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
+ overflow_ns = pmu_icount_ticks_to_ns((int64_t)overflow_delta);
+ overflow_left = pmu_icount_ticks_to_ns(overflow_left) ;
+ } else {
+ return -1;
+ }
+ overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
+
+ if (overflow_at > INT64_MAX) {
+ overflow_left += overflow_at - INT64_MAX;
+ counter->irq_overflow_left = overflow_left;
+ overflow_at = INT64_MAX;
+ }
+ timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
+
+ return 0;
+}
+
+
+int riscv_pmu_init(RISCVCPU *cpu, int num_counters)
+{
+ if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) {
+ return -1;
+ }
+
+ cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal);
+ if (!cpu->pmu_event_ctr_map) {
+ /* PMU support can not be enabled */
+ qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n");
+ cpu->cfg.pmu_num = 0;
+ return -1;
+ }
+
+ /* Create a bitmask of available programmable counters */
+ cpu->pmu_avail_ctrs = ~(-1 << (num_counters + 3)) & ~(0x07);
+ return 0;
}
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 58a5bc3a4089..af78da92e820 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -26,3 +26,12 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
uint32_t target_ctr);
bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
uint32_t target_ctr);
+void riscv_pmu_timer_cb(void *priv);
+int riscv_pmu_init(RISCVCPU *cpu, int num_counters);
+int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
+ uint32_t ctr_idx);
+int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
+void riscv_pmu_generate_fdt_node(void *fdt, char *pmu_name);
+target_ulong get_icount_ticks(bool brv32);
+int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
+ uint32_t ctr_idx);
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 09/10] target/riscv: Add few cache related PMU events
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
` (7 preceding siblings ...)
2021-10-25 19:55 ` [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support Atish Patra
@ 2021-10-25 19:56 ` Atish Patra
2021-10-25 19:56 ` [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
9 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:56 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d41d5cd27c14..66cdfca547cc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,10 +21,13 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "pmu.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "trace.h"
#include "semihosting/common-semi.h"
+#include "cpu.h"
+#include "cpu_bits.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@@ -750,6 +753,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
}
#endif /* !CONFIG_USER_ONLY */
+
+static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
+{
+ enum riscv_pmu_event_idx pmu_event_type;
+
+ switch (access_type) {
+ case MMU_INST_FETCH:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
+ break;
+ case MMU_DATA_LOAD:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
+ break;
+ case MMU_DATA_STORE:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
+ break;
+ default:
+ return;
+ }
+
+ riscv_pmu_incr_ctr(cpu, pmu_event_type);
+}
+
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -847,6 +872,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
}
} else {
+ pmu_tlb_fill_incr_ctr(cpu, access_type);
/* Single stage lookup */
ret = get_physical_address(env, &pa, &prot, address, NULL,
access_type, mmu_idx, true, false, false);
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
` (8 preceding siblings ...)
2021-10-25 19:56 ` [ PATCH v3 09/10] target/riscv: Add few cache related PMU events Atish Patra
@ 2021-10-25 19:56 ` Atish Patra
9 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2021-10-25 19:56 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Bin Meng, Alistair Francis, Palmer Dabbelt, qemu-riscv
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
hw/riscv/virt.c | 36 ++++++++++++++++++++++++++
target/riscv/pmp.c | 1 +
target/riscv/pmu.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 100 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ec0cb69b8c73..b246d2e339eb 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -28,6 +28,7 @@
#include "hw/qdev-properties.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
+#include "target/riscv/pmu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
@@ -406,6 +407,39 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
+static void create_fdt_socket_pmu(RISCVVirtState *s,
+ int socket, uint32_t *phandle,
+ uint32_t *intc_phandles)
+{
+ int cpu;
+ char *pmu_name;
+ RISCVCPU hart;
+ uint32_t *pmu_cells;
+ MachineState *mc = MACHINE(s);
+
+ pmu_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ pmu_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ pmu_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_PMU_OVF);
+ }
+
+ pmu_name = g_strdup_printf("/soc/pmu");
+ qemu_fdt_add_subnode(mc->fdt, pmu_name);
+ qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
+ hart = s->soc[0].harts[0];
+ if (hart.cfg.ext_sscof) {
+ qemu_fdt_setprop_cell(mc->fdt, pmu_name, "#interrupt-cells", 1);
+ qemu_fdt_setprop(mc->fdt, pmu_name, "interrupts-extended", pmu_cells,
+ s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ }
+ riscv_pmu_generate_fdt_node(mc->fdt, pmu_name);
+
+ g_free(pmu_name);
+ g_free(pmu_cells);
+}
+
+
static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
bool is_32_bit, uint32_t *phandle,
uint32_t *irq_mmio_phandle,
@@ -445,6 +479,8 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
create_fdt_socket_plic(s, memmap, socket, phandle,
intc_phandles, xplic_phandles);
+ create_fdt_socket_pmu(s, socket, phandle, intc_phandles);
+
g_free(intc_phandles);
g_free(clust_name);
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 54abf425835c..2e2145e51903 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -25,6 +25,7 @@
#include "cpu.h"
#include "trace.h"
#include "exec/exec-all.h"
+#include "sysemu/device_tree.h"
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 25bdbdf48ff7..9e11af85576d 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -19,9 +19,72 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "pmu.h"
+#include "sysemu/device_tree.h"
#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
+/**
+ * To keep it simple, any event can be mapped to any programmable counters in
+ * QEMU. The generic cycle & instruction count events can also be monitored
+ * using programmable counters. In that case, mcycle & minstret must continue
+ * to provide the correct value as well.
+ */
+void riscv_pmu_generate_fdt_node(void *fdt, char *pmu_name)
+{
+ uint32_t fdt_event_map[6] = {};
+ uint32_t fdt_event_ctr_map[20] = {};
+ uint32_t fdt_raw_event_ctr_map[6] = {};
+
+ /* Dummy event and mhpmevent values */
+ fdt_event_map[0] = cpu_to_be32(0x00000009);
+ fdt_event_map[1] = cpu_to_be32(0x00000000);
+ fdt_event_map[2] = cpu_to_be32(0x00000200);
+ fdt_event_map[3] = cpu_to_be32(0x00010000);
+ fdt_event_map[4] = cpu_to_be32(0x00000100);
+ fdt_event_map[5] = cpu_to_be32(0x00000002);
+ qemu_fdt_setprop(fdt, pmu_name, "pmu,event-to-mhpmevent",
+ fdt_event_map, sizeof(fdt_event_map));
+
+ /* SBI_PMU_HW_CPU_CYCLES */
+ fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);
+ fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);
+ fdt_event_ctr_map[2] = cpu_to_be32(0x00000FF9);
+
+ /* SBI_PMU_HW_INSTRUCTIONS */
+ fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);
+ fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
+ fdt_event_ctr_map[5] = cpu_to_be32(0x00000FFC);
+
+ /* SBI_PMU_HW_CACHE_DTLB : READ : MISS */
+ fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[8] = cpu_to_be32(0x00001F0);
+
+ /* SBI_PMU_HW_CACHE_DTLB : WRITE : MISS */
+ fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[11] = cpu_to_be32(0x00001F0);
+
+ /* SBI_PMU_HW_CACHE_ITLB : READ : MISS */
+ fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
+ fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
+ fdt_event_ctr_map[14] = cpu_to_be32(0x00001F0);
+
+ qemu_fdt_setprop(fdt, pmu_name, "pmu,event-to-mhpmcounters",
+ fdt_event_ctr_map, sizeof(fdt_event_ctr_map));
+
+ /* Dummy raw events */
+ fdt_raw_event_ctr_map[0] = cpu_to_be32(0x00000000);
+ fdt_raw_event_ctr_map[1] = cpu_to_be32(0x00020002);
+ fdt_raw_event_ctr_map[2] = cpu_to_be32(0x00000F00);
+ fdt_raw_event_ctr_map[3] = cpu_to_be32(0x00000000);
+ fdt_raw_event_ctr_map[4] = cpu_to_be32(0x00020003);
+ fdt_raw_event_ctr_map[5] = cpu_to_be32(0x000000F0);
+ qemu_fdt_setprop(fdt, pmu_name, "pmu,raw-event-to-mhpmcounters",
+ fdt_raw_event_ctr_map,
+ sizeof(fdt_raw_event_ctr_map));
+}
+
static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
{
if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||
--
2.31.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
@ 2021-11-03 5:40 ` Alistair Francis
2021-11-04 11:00 ` Bin Meng
1 sibling, 0 replies; 26+ messages in thread
From: Alistair Francis @ 2021-11-03 5:40 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 6:39 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The predicate function calculates the counter index incorrectly for
> hpmcounterx. Fix the counter index to reflect correct CSR number.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 23fbbd32162a..1ec776013435 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -89,8 +89,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> }
> break;
> case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
> - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
> + ctr_index = csrno - CSR_CYCLE;
> + if (!get_field(env->hcounteren, 1 << ctr_index) &&
> + get_field(env->mcounteren, 1 << ctr_index)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> @@ -116,8 +117,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> }
> break;
> case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
> - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
> + ctr_index = csrno - CSR_CYCLEH;
> + if (!get_field(env->hcounteren, 1 << ctr_index) &&
> + get_field(env->mcounteren, 1 << ctr_index)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
2021-10-25 19:55 ` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for Atish Patra
@ 2021-11-03 5:43 ` Alistair Francis
2021-11-04 11:07 ` Bin Meng
1 sibling, 0 replies; 26+ messages in thread
From: Alistair Francis @ 2021-11-03 5:43 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 5:56 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Currently, the predicate function for PMU related CSRs only works if
> virtualization is enabled. It also does not check mcounteren bits before
> before cycle/minstret/hpmcounterx access.
>
> Support supervisor mode access in the predicate function as well.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1ec776013435..de484c74d3b4 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> #if !defined(CONFIG_USER_ONLY)
> CPUState *cs = env_cpu(env);
> RISCVCPU *cpu = RISCV_CPU(cs);
> + int ctr_index;
>
> if (!cpu->cfg.ext_counters) {
> /* The Counters extensions is not enabled */
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + if (env->priv == PRV_S) {
> + switch (csrno) {
> + case CSR_CYCLE:
> + if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_TIME:
> + if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_INSTRET:
> + if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> + ctr_index = csrno - CSR_CYCLE;
> + if (!get_field(env->mcounteren, 1 << ctr_index)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + }
> + if (riscv_cpu_is_32bit(env)) {
> + switch (csrno) {
> + case CSR_CYCLEH:
> + if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_TIMEH:
> + if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_INSTRETH:
> + if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> + ctr_index = csrno - CSR_CYCLEH;
> + if (!get_field(env->mcounteren, 1 << ctr_index)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + }
> + }
> + }
> +
> if (riscv_cpu_virt_enabled(env)) {
> switch (csrno) {
> case CSR_CYCLE:
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
2021-10-25 19:55 ` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
@ 2021-11-03 5:47 ` Alistair Francis
2021-11-04 11:10 ` Bin Meng
1 sibling, 0 replies; 26+ messages in thread
From: Alistair Francis @ 2021-11-03 5:47 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 6:03 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The PMU counters are supported via cpu config "Counters" which doesn't
> indicate the correct purpose of those counters.
>
> Rename the config property to pmu to indicate that these counters
> are performance monitoring counters. This aligns with cpu options for
> ARM architecture as well.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 2 +-
> target/riscv/csr.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e63..3b55f5ed0036 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9e55b2f5b170..ebc1a8754032 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -294,7 +294,7 @@ struct RISCVCPU {
> bool ext_zbb;
> bool ext_zbc;
> bool ext_zbs;
> - bool ext_counters;
> + bool ext_pmu;
> bool ext_ifencei;
> bool ext_icsr;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index de484c74d3b4..c486eeaffeb8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> RISCVCPU *cpu = RISCV_CPU(cs);
> int ctr_index;
>
> - if (!cpu->cfg.ext_counters) {
> + if (!cpu->cfg.ext_pmu) {
> /* The Counters extensions is not enabled */
> return RISCV_EXCP_ILLEGAL_INST;
> }
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
2021-10-25 19:55 ` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Atish Patra
@ 2021-11-03 5:50 ` Alistair Francis
2021-11-04 11:45 ` Bin Meng
1 sibling, 0 replies; 26+ messages in thread
From: Alistair Francis @ 2021-11-03 5:50 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 6:41 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will indicate
> how many programmable counters should be implemented by the cpu.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 2 +-
> target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++----------------
> 3 files changed, 65 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3b55f5ed0036..aec94101a4c0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> - DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ebc1a8754032..d0a722e7cbe1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -294,10 +294,10 @@ struct RISCVCPU {
> bool ext_zbb;
> bool ext_zbc;
> bool ext_zbs;
> - bool ext_pmu;
> bool ext_ifencei;
> bool ext_icsr;
>
> + uint8_t pmu_num;
> char *priv_spec;
> char *user_spec;
> char *bext_spec;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c486eeaffeb8..a7249eaf917f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -57,15 +57,45 @@ static RISCVException vs(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> +static RISCVException mctr(CPURISCVState *env, int csrno)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + int ctr_index;
> + int base_csrno = CSR_MHPMCOUNTER3;
> +
> + if (riscv_cpu_is_32bit(env) && csrno >= CSR_MCYCLEH) {
> + /* Offset for RV32 mhpmcounternh counters */
> + base_csrno += 0x80;
> + }
> + ctr_index = csrno - base_csrno;
> + if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
> + /* The PMU is not enabled or counter is out of range*/
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return RISCV_EXCP_NONE;
> +#endif
This needs a return type for #if defined(CONFIG_USER_ONLY)
Alistair
> +}
> +
> static RISCVException ctr(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> CPUState *cs = env_cpu(env);
> RISCVCPU *cpu = RISCV_CPU(cs);
> int ctr_index;
> + int base_csrno = CSR_CYCLE;
> + bool brv32 = riscv_cpu_is_32bit(env);
> +
> + if (brv32 && csrno >= CSR_CYCLEH) {
> + /* Offset for RV32 hpmcounternh counters */
> + base_csrno += 0x80;
> + }
> + ctr_index = csrno - base_csrno;
>
> - if (!cpu->cfg.ext_pmu) {
> - /* The Counters extensions is not enabled */
> + if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
> + /* The PMU is not enabled or counter is out of range */
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -93,7 +123,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> }
> break;
> }
> - if (riscv_cpu_is_32bit(env)) {
> + if (brv32) {
> switch (csrno) {
> case CSR_CYCLEH:
> if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> @@ -148,7 +178,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> }
> break;
> }
> - if (riscv_cpu_is_32bit(env)) {
> + if (brv32) {
> switch (csrno) {
> case CSR_CYCLEH:
> if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> @@ -1720,35 +1750,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
> [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
>
> - [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
> - [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
> - [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
> - [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
> - [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
> - [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
> - [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
> - [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
> - [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
> - [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
> - [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
> - [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
> - [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
> - [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
> - [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
> - [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
> - [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
> - [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
> - [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
> - [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
> - [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
> - [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
> - [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
> - [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
> - [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
> - [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
> - [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
> - [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
> - [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
> + [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
> + [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
> + [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
> + [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
> + [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
> + [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
> + [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
> + [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
> + [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
> + [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
> + [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
> + [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
> + [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
> + [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
> + [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
> + [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
> + [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
> + [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
> + [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
> + [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
> + [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
> + [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
> + [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
> + [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
> + [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
> + [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
> + [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
> + [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
> + [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
>
> [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
> [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR
2021-10-25 19:55 ` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR Atish Patra
@ 2021-11-03 5:51 ` Alistair Francis
2021-11-04 11:49 ` Bin Meng
1 sibling, 0 replies; 26+ messages in thread
From: Alistair Francis @ 2021-11-03 5:51 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 6:05 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> As per the privilege specification v1.11, mcountinhibit allows to start/stop
> a pmu counter selectively.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 4 ++++
> target/riscv/csr.c | 25 +++++++++++++++++++++++++
> target/riscv/machine.c | 5 +++--
> 4 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d0a722e7cbe1..b421eefa623f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -217,6 +217,8 @@ struct CPURISCVState {
> target_ulong scounteren;
> target_ulong mcounteren;
>
> + target_ulong mcountinhibit;
> +
> target_ulong sscratch;
> target_ulong mscratch;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee2d..72b1485e621f 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -275,6 +275,10 @@
> #define CSR_MHPMCOUNTER29 0xb1d
> #define CSR_MHPMCOUNTER30 0xb1e
> #define CSR_MHPMCOUNTER31 0xb1f
> +
> +/* Machine counter-inhibit register */
> +#define CSR_MCOUNTINHIBIT 0x320
> +
> #define CSR_MHPMEVENT3 0x323
> #define CSR_MHPMEVENT4 0x324
> #define CSR_MHPMEVENT5 0x325
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index a7249eaf917f..faf02e12ec34 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -766,6 +766,28 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + if (env->priv_ver < PRIV_VERSION_1_11_0) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + *val = env->mcountinhibit;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> + if (env->priv_ver < PRIV_VERSION_1_11_0) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + env->mcountinhibit = val;
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -1780,6 +1802,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
> [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
>
> + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
> + write_mcountinhibit },
> +
> [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
> [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
> [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 16a08302daff..20dea0843604 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 2,
> - .minimum_version_id = 2,
> + .version_id = 3,
> + .minimum_version_id = 3,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> @@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
2021-11-03 5:40 ` Alistair Francis
@ 2021-11-04 11:00 ` Bin Meng
1 sibling, 0 replies; 26+ messages in thread
From: Bin Meng @ 2021-11-04 11:00 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 4:39 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The predicate function calculates the counter index incorrectly for
> hpmcounterx. Fix the counter index to reflect correct CSR number.
>
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/csr.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
2021-10-25 19:55 ` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for Atish Patra
2021-11-03 5:43 ` Alistair Francis
@ 2021-11-04 11:07 ` Bin Meng
2022-01-05 21:46 ` Atish Patra
1 sibling, 1 reply; 26+ messages in thread
From: Bin Meng @ 2021-11-04 11:07 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 3:56 AM Atish Patra <atish.patra@wdc.com> wrote:
>
The commit title is incomplete
> Currently, the predicate function for PMU related CSRs only works if
> virtualization is enabled. It also does not check mcounteren bits before
> before cycle/minstret/hpmcounterx access.
>
> Support supervisor mode access in the predicate function as well.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1ec776013435..de484c74d3b4 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> #if !defined(CONFIG_USER_ONLY)
> CPUState *cs = env_cpu(env);
> RISCVCPU *cpu = RISCV_CPU(cs);
> + int ctr_index;
>
> if (!cpu->cfg.ext_counters) {
> /* The Counters extensions is not enabled */
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + if (env->priv == PRV_S) {
> + switch (csrno) {
> + case CSR_CYCLE:
> + if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_TIME:
> + if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_INSTRET:
> + if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> + ctr_index = csrno - CSR_CYCLE;
> + if (!get_field(env->mcounteren, 1 << ctr_index)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
The above switch..case can be simplified with the logic of last case
as the same one applies to all cases.
> + }
> + if (riscv_cpu_is_32bit(env)) {
> + switch (csrno) {
> + case CSR_CYCLEH:
> + if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_TIMEH:
> + if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_INSTRETH:
> + if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + break;
> + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> + ctr_index = csrno - CSR_CYCLEH;
> + if (!get_field(env->mcounteren, 1 << ctr_index)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
ditto
> + break;
> + }
> + }
> + }
> +
> if (riscv_cpu_virt_enabled(env)) {
> switch (csrno) {
> case CSR_CYCLE:
>
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
2021-10-25 19:55 ` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2021-11-03 5:47 ` Alistair Francis
@ 2021-11-04 11:10 ` Bin Meng
2022-01-05 21:48 ` Atish Patra
1 sibling, 1 reply; 26+ messages in thread
From: Bin Meng @ 2021-11-04 11:10 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 4:02 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The PMU counters are supported via cpu config "Counters" which doesn't
> indicate the correct purpose of those counters.
>
> Rename the config property to pmu to indicate that these counters
> are performance monitoring counters. This aligns with cpu options for
> ARM architecture as well.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 2 +-
> target/riscv/csr.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e63..3b55f5ed0036 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9e55b2f5b170..ebc1a8754032 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -294,7 +294,7 @@ struct RISCVCPU {
> bool ext_zbb;
> bool ext_zbc;
> bool ext_zbs;
> - bool ext_counters;
> + bool ext_pmu;
> bool ext_ifencei;
> bool ext_icsr;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index de484c74d3b4..c486eeaffeb8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> RISCVCPU *cpu = RISCV_CPU(cs);
> int ctr_index;
>
> - if (!cpu->cfg.ext_counters) {
> + if (!cpu->cfg.ext_pmu) {
> /* The Counters extensions is not enabled */
%s/Counters extensions/PMU extension
> return RISCV_EXCP_ILLEGAL_INST;
> }
> --
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
2021-10-25 19:55 ` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Atish Patra
2021-11-03 5:50 ` Alistair Francis
@ 2021-11-04 11:45 ` Bin Meng
2022-01-05 21:51 ` Atish Patra
1 sibling, 1 reply; 26+ messages in thread
From: Bin Meng @ 2021-11-04 11:45 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 4:41 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will indicate
> how many programmable counters should be implemented by the cpu.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 2 +-
> target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++----------------
> 3 files changed, 65 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3b55f5ed0036..aec94101a4c0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> - DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ebc1a8754032..d0a722e7cbe1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -294,10 +294,10 @@ struct RISCVCPU {
> bool ext_zbb;
> bool ext_zbc;
> bool ext_zbs;
> - bool ext_pmu;
> bool ext_ifencei;
> bool ext_icsr;
>
> + uint8_t pmu_num;
> char *priv_spec;
> char *user_spec;
> char *bext_spec;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c486eeaffeb8..a7249eaf917f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -57,15 +57,45 @@ static RISCVException vs(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> +static RISCVException mctr(CPURISCVState *env, int csrno)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + int ctr_index;
> + int base_csrno = CSR_MHPMCOUNTER3;
> +
> + if (riscv_cpu_is_32bit(env) && csrno >= CSR_MCYCLEH) {
> + /* Offset for RV32 mhpmcounternh counters */
> + base_csrno += 0x80;
> + }
> + ctr_index = csrno - base_csrno;
> + if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
> + /* The PMU is not enabled or counter is out of range*/
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return RISCV_EXCP_NONE;
> +#endif
> +}
> +
> static RISCVException ctr(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> CPUState *cs = env_cpu(env);
> RISCVCPU *cpu = RISCV_CPU(cs);
> int ctr_index;
> + int base_csrno = CSR_CYCLE;
Use CSR_HPMCOUNTER3 here, for consistency with the mctr version
> + bool brv32 = riscv_cpu_is_32bit(env);
nits: the leading 'b' sounds useless. I would use rv32 instead.
> +
> + if (brv32 && csrno >= CSR_CYCLEH) {
> + /* Offset for RV32 hpmcounternh counters */
> + base_csrno += 0x80;
> + }
> + ctr_index = csrno - base_csrno;
>
> - if (!cpu->cfg.ext_pmu) {
> - /* The Counters extensions is not enabled */
> + if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
so we can use "ctr_index >= cpu->cfg.pmu_num" here
> + /* The PMU is not enabled or counter is out of range */
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -93,7 +123,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> }
> break;
> }
> - if (riscv_cpu_is_32bit(env)) {
> + if (brv32) {
> switch (csrno) {
> case CSR_CYCLEH:
> if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> @@ -148,7 +178,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> }
> break;
> }
> - if (riscv_cpu_is_32bit(env)) {
> + if (brv32) {
> switch (csrno) {
> case CSR_CYCLEH:
> if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> @@ -1720,35 +1750,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
> [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
>
> - [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
> - [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
> - [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
> - [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
> - [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
> - [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
> - [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
> - [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
> - [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
> - [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
> - [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
> - [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
> - [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
> - [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
> - [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
> - [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
> - [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
> - [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
> - [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
> - [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
> - [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
> - [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
> - [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
> - [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
> - [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
> - [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
> - [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
> - [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
> - [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
> + [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
> + [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
> + [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
> + [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
> + [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
> + [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
> + [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
> + [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
> + [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
> + [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
> + [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
> + [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
> + [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
> + [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
> + [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
> + [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
> + [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
> + [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
> + [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
> + [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
> + [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
> + [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
> + [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
> + [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
> + [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
> + [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
> + [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
> + [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
> + [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
>
> [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
> [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR
2021-10-25 19:55 ` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR Atish Patra
2021-11-03 5:51 ` Alistair Francis
@ 2021-11-04 11:49 ` Bin Meng
1 sibling, 0 replies; 26+ messages in thread
From: Bin Meng @ 2021-11-04 11:49 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Oct 26, 2021 at 4:05 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> As per the privilege specification v1.11, mcountinhibit allows to start/stop
> a pmu counter selectively.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 4 ++++
> target/riscv/csr.c | 25 +++++++++++++++++++++++++
> target/riscv/machine.c | 5 +++--
> 4 files changed, 34 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
2021-10-25 19:55 ` [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support Atish Patra
@ 2021-12-27 4:37 ` Frank Chang
2022-01-07 0:38 ` Atish Patra
0 siblings, 1 reply; 26+ messages in thread
From: Frank Chang @ 2021-12-27 4:37 UTC (permalink / raw)
To: Atish Patra
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
[-- Attachment #1: Type: text/plain, Size: 34121 bytes --]
Atish Patra <atish.patra@wdc.com> 於 2021年10月26日 週二 上午3:57寫道：
> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> extension allows the perf to handle overflow interrupts and filtering
> support. This patch provides a framework for programmable
> counters to leverage the extension. As the extension doesn't have any
> provision for the overflow bit for fixed counters, the fixed events
> can also be monitoring using programmable counters. The underlying
> counters for cycle and instruction counters are always running. Thus,
> a separate timer device is programmed to handle the overflow.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/cpu.c | 12 ++
> target/riscv/cpu.h | 25 +++
> target/riscv/cpu_bits.h | 55 +++++++
> target/riscv/csr.c | 150 +++++++++++++++++-
> target/riscv/machine.c | 2 +-
> target/riscv/pmu.c | 343 +++++++++++++++++++++++++++++++++++++++-
> target/riscv/pmu.h | 9 ++
> 7 files changed, 589 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index aec94101a4c0..757c646037bb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -22,6 +22,7 @@
> #include "qemu/ctype.h"
> #include "qemu/log.h"
> #include "cpu.h"
> +#include "pmu.h"
> #include "internals.h"
> #include "exec/exec-all.h"
> #include "qapi/error.h"
> @@ -535,6 +536,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> set_misa(env, target_misa);
> }
>
> + if (cpu->cfg.pmu_num) {
> + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscof)
> {
> + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> + riscv_pmu_timer_cb, cpu);
> + if (!cpu->pmu_timer) {
> + cpu->cfg.ext_sscof = false;
> + }
> + }
> + }
> +
> riscv_cpu_register_gdb_regs_for_features(cs);
>
> qemu_init_vcpu(cs);
> @@ -599,6 +610,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
> + DEFINE_PROP_BOOL("sscof", RISCVCPU, cfg.ext_sscof, false),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index da34614ad788..b66d8acff109 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -123,6 +123,8 @@ struct PMUCTRState {
> /* Snapshort value of a counter in RV32 */
> target_ulong mhpmcounterh_prev;
> bool started;
> + /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt
> trigger */
> + target_ulong irq_overflow_left;
> };
>
> struct CPURISCVState {
> @@ -241,6 +243,9 @@ struct CPURISCVState {
> /* PMU event selector configured values. First three are unused*/
> target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
>
> + /* PMU event selector configured values for RV32*/
> + target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
> +
> target_ulong sscratch;
> target_ulong mscratch;
>
> @@ -320,6 +325,7 @@ struct RISCVCPU {
> bool ext_zbs;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_sscof;
>
> uint8_t pmu_num;
> char *priv_spec;
> @@ -333,6 +339,12 @@ struct RISCVCPU {
> bool epmp;
> uint64_t resetvec;
> } cfg;
> +
> + QEMUTimer *pmu_timer;
> + /* A bitmask of Available programmable counters */
> + uint32_t pmu_avail_ctrs;
> + /* Mapping of events to counters */
> + GHashTable *pmu_event_ctr_map;
> };
>
> static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
> @@ -528,6 +540,19 @@ enum {
> CSR_TABLE_SIZE = 0x1000
> };
>
> +/**
> + * The event id are encoded based on the encoding specified in the
> + * SBI specification v0.3
> + */
> +
> +enum riscv_pmu_event_idx {
> + RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
> + RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
> + RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
> + RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
> + RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
> +};
> +
> /* CSR function table */
> extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 72b1485e621f..cd6523c1c6ee 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -308,6 +308,37 @@
> #define CSR_MHPMEVENT29 0x33d
> #define CSR_MHPMEVENT30 0x33e
> #define CSR_MHPMEVENT31 0x33f
> +
> +#define CSR_MHPMEVENT3H 0x723
> +#define CSR_MHPMEVENT4H 0x724
> +#define CSR_MHPMEVENT5H 0x725
> +#define CSR_MHPMEVENT6H 0x726
> +#define CSR_MHPMEVENT7H 0x727
> +#define CSR_MHPMEVENT8H 0x728
> +#define CSR_MHPMEVENT9H 0x729
> +#define CSR_MHPMEVENT10H 0x72a
> +#define CSR_MHPMEVENT11H 0x72b
> +#define CSR_MHPMEVENT12H 0x72c
> +#define CSR_MHPMEVENT13H 0x72d
> +#define CSR_MHPMEVENT14H 0x72e
> +#define CSR_MHPMEVENT15H 0x72f
> +#define CSR_MHPMEVENT16H 0x730
> +#define CSR_MHPMEVENT17H 0x731
> +#define CSR_MHPMEVENT18H 0x732
> +#define CSR_MHPMEVENT19H 0x733
> +#define CSR_MHPMEVENT20H 0x734
> +#define CSR_MHPMEVENT21H 0x735
> +#define CSR_MHPMEVENT22H 0x736
> +#define CSR_MHPMEVENT23H 0x737
> +#define CSR_MHPMEVENT24H 0x738
> +#define CSR_MHPMEVENT25H 0x739
> +#define CSR_MHPMEVENT26H 0x73a
> +#define CSR_MHPMEVENT27H 0x73b
> +#define CSR_MHPMEVENT28H 0x73c
> +#define CSR_MHPMEVENT29H 0x73d
> +#define CSR_MHPMEVENT30H 0x73e
> +#define CSR_MHPMEVENT31H 0x73f
> +
> #define CSR_MHPMCOUNTER3H 0xb83
> #define CSR_MHPMCOUNTER4H 0xb84
> #define CSR_MHPMCOUNTER5H 0xb85
> @@ -338,6 +369,8 @@
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
>
> +#define CSR_SCOUNTOVF 0xda0
> +
> /* mstatus CSR bits */
> #define MSTATUS_UIE 0x00000001
> #define MSTATUS_SIE 0x00000002
> @@ -508,6 +541,7 @@ typedef enum RISCVException {
> #define IRQ_S_EXT 9
> #define IRQ_VS_EXT 10
> #define IRQ_M_EXT 11
> +#define IRQ_PMU_OVF 13
>
> /* mip masks */
> #define MIP_USIP (1 << IRQ_U_SOFT)
> @@ -522,11 +556,13 @@ typedef enum RISCVException {
> #define MIP_SEIP (1 << IRQ_S_EXT)
> #define MIP_VSEIP (1 << IRQ_VS_EXT)
> #define MIP_MEIP (1 << IRQ_M_EXT)
> +#define MIP_LCOFIP (1 << IRQ_PMU_OVF)
>
> /* sip masks */
> #define SIP_SSIP MIP_SSIP
> #define SIP_STIP MIP_STIP
> #define SIP_SEIP MIP_SEIP
> +#define SIP_LCOFIP MIP_LCOFIP
>
> /* MIE masks */
> #define MIE_SEIE (1 << IRQ_S_EXT)
> @@ -535,4 +571,23 @@ typedef enum RISCVException {
> #define MIE_UTIE (1 << IRQ_U_TIMER)
> #define MIE_SSIE (1 << IRQ_S_SOFT)
> #define MIE_USIE (1 << IRQ_U_SOFT)
> +#define MIE_LCOFIE (1 << IRQ_PMU_OVF)
> +
> +#define MHPMEVENT_BIT_OF BIT(63)
> +#define MHPMEVENTH_BIT_OF BIT(31)
> +#define MHPMEVENT_BIT_MINH BIT(62)
> +#define MHPMEVENTH_BIT_MINH BIT(30)
> +#define MHPMEVENT_BIT_SINH BIT(61)
> +#define MHPMEVENTH_BIT_SINH BIT(29)
> +#define MHPMEVENT_BIT_UINH BIT(60)
> +#define MHPMEVENTH_BIT_UINH BIT(28)
> +#define MHPMEVENT_BIT_VSINH BIT(59)
> +#define MHPMEVENTH_BIT_VSINH BIT(27)
> +#define MHPMEVENT_BIT_VUINH BIT(58)
> +#define MHPMEVENTH_BIT_VUINH BIT(26)
> +
> +#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
> +#define MHPMEVENT_IDX_MASK 0xFFFFF
> +#define MHPMEVENT_SSCOF_RESVD 16
> +
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1ce1bb0868d7..6a1580c4b6ce 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -89,6 +89,19 @@ static RISCVException mctr32(CPURISCVState *env, int
> csrno)
> return mctr(env, csrno);
> }
>
> +static RISCVException sscof(CPURISCVState *env, int csrno)
> +{
> + #if !defined(CONFIG_USER_ONLY)
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + if (!cpu->cfg.ext_sscof) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +#endif
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException ctr(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -104,11 +117,18 @@ static RISCVException ctr(CPURISCVState *env, int
> csrno)
> }
> ctr_index = csrno - base_csrno;
>
> - if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
> + if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
> + (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
> + goto skip_ext_pmu_check;
> + }
> +
> + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) {
> /* The PMU is not enabled or counter is out of range */
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> +skip_ext_pmu_check:
> +
> if (env->priv == PRV_S) {
> switch (csrno) {
> case CSR_CYCLE:
> @@ -424,7 +444,7 @@ static RISCVException write_vstart(CPURISCVState *env,
> int csrno,
> }
>
> /* User Timers and Counters */
> -static target_ulong get_icount_ticks(bool brv32)
> +target_ulong get_icount_ticks(bool brv32)
> {
> int64_t val;
> target_ulong result;
> @@ -461,11 +481,36 @@ static int write_mhpmevent(CPURISCVState *env, int
> csrno, target_ulong val)
> {
> int evt_index = csrno - CSR_MCOUNTINHIBIT;
>
> + if (!riscv_cpu_is_32bit(env)) {
> + riscv_pmu_update_event_map(env, val, evt_index);
> + }
> env->mhpmevent_val[evt_index] = val;
>
> return RISCV_EXCP_NONE;
> }
>
> +static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong
> *val)
> +{
> + int evt_index = csrno - CSR_MHPMEVENT3H + 3;
> +
> + *val = env->mhpmevent_val[evt_index];
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> +static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong
> val)
> +{
> + int evt_index = csrno - CSR_MHPMEVENT3H + 3;
> + uint64_t mhpmevth_val = val;
> + uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
> +
> + mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
> + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
> + env->mhpmeventh_val[evt_index] = val;
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong
> val)
> {
> int ctr_idx = csrno - CSR_MCYCLE;
> @@ -475,6 +520,9 @@ static int write_mhpmcounter(CPURISCVState *env, int
> csrno, target_ulong val)
> if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
> riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
> counter->mhpmcounter_prev = get_icount_ticks(false);
> + if (ctr_idx > 2) {
> + riscv_pmu_setup_timer(env, val, ctr_idx);
> + }
> } else {
> /* Other counters can keep incrementing from the given value */
> counter->mhpmcounter_prev = val;
> @@ -487,11 +535,17 @@ static int write_mhpmcounterh(CPURISCVState *env,
> int csrno, target_ulong val)
> {
> int ctr_idx = csrno - CSR_MCYCLEH;
> PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
> + uint64_t mhpmctr_val = counter->mhpmcounter_val;
> + uint64_t mhpmctrh_val = val;
>
> counter->mhpmcounterh_val = val;
> + mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32);
> if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
> riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
> counter->mhpmcounterh_prev = get_icount_ticks(false);
> + if (ctr_idx > 2) {
> + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);
> + }
> } else {
> counter->mhpmcounterh_prev = val;
> }
> @@ -561,6 +615,32 @@ static int read_hpmcounterh(CPURISCVState *env, int
> csrno, target_ulong *val)
> return riscv_pmu_read_ctr(env, val, true, ctr_index);
> }
>
> +static int read_scountovf(CPURISCVState *env, int csrno, target_ulong
> *val)
> +{
> + int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
> + int i;
> + *val = 0;
> + target_ulong *mhpm_evt_val;
> + uint64_t of_bit_mask;
> +
> + if (riscv_cpu_is_32bit(env)) {
> + mhpm_evt_val = env->mhpmeventh_val;
> + of_bit_mask = MHPMEVENTH_BIT_OF;
> + } else {
> + mhpm_evt_val = env->mhpmevent_val;
> + of_bit_mask = MHPMEVENT_BIT_OF;
> + }
> +
> + for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
> + if ((get_field(env->mcounteren, BIT(i))) &&
> + (mhpm_evt_val[i] & of_bit_mask)) {
> + *val |= BIT(i);
> + }
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> #if defined(CONFIG_USER_ONLY)
> static RISCVException read_time(CPURISCVState *env, int csrno,
> target_ulong *val)
> @@ -607,7 +687,7 @@ static RISCVException read_timeh(CPURISCVState *env,
> int csrno,
> /* Machine constants */
>
> #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
> -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
> +#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP | MIP_LCOFIP)
> #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
>
> static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
> @@ -645,7 +725,8 @@ static const target_ulong vs_delegable_excps =
> DELEGABLE_EXCPS &
> static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE
> |
> SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
> SSTATUS_SUM | SSTATUS_MXR;
> -static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
> MIP_UEIP;
> +static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
> MIP_UEIP |
> + SIP_LCOFIP;
> static const target_ulong hip_writable_mask = MIP_VSSIP;
> static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
> MIP_VSEIP;
> static const target_ulong vsip_writable_mask = MIP_VSSIP;
> @@ -2022,6 +2103,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
> write_mhpmevent },
>
> + [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> + [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscof, read_mhpmeventh,
> + write_mhpmeventh},
> +
> [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
> [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
> [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh },
> @@ -2110,5 +2250,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> write_mhpmcounterh
> },
> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
> write_mhpmcounterh
> },
> + [CSR_SCOUNTOVF] = { "scountovf", sscof, read_scountovf },
> +
> #endif /* !CONFIG_USER_ONLY */
> };
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index e0a489c20e67..7b2ef17904a9 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -88,7 +88,7 @@ static bool pmu_needed(void *opaque)
> {
> RISCVCPU *cpu = opaque;
>
> - return cpu->cfg.ext_pmu;
> + return cpu->cfg.pmu_num;
> }
>
> static const VMStateDescription vmstate_vector = {
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index 000fe8da45ef..25bdbdf48ff7 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -20,13 +20,352 @@
> #include "cpu.h"
> #include "pmu.h"
>
> +#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
> +
> +static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
> +{
> + if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||
> + !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) {
> + return false;
> + } else {
> + return true;
> + }
> +}
> +
> +static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx)
> +{
> + CPURISCVState *env = &cpu->env;
> +
> + if (!riscv_pmu_counter_valid(cpu, ctr_idx) ||
> + !get_field(env->mcounteren, BIT(ctr_idx))) {
> + return false;
> + } else {
> + return true;
> + }
> +}
> +
> +static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
> +{
> + CPURISCVState *env = &cpu->env;
> + target_ulong max_val = UINT32_MAX;
> + PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
> +
> + /* Privilege mode filtering */
> + if ((env->priv == PRV_M &&
> + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) ||
> + (env->priv == PRV_S &&
> + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) ||
> + (env->priv == PRV_U &&
> + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) {
> + return 0;
> + }
> +
> + /* Handle the overflow scenario */
> + if (counter->mhpmcounter_val == max_val) {
> + if (counter->mhpmcounterh_val == max_val) {
> + counter->mhpmcounter_val = 0;
> + counter->mhpmcounterh_val = 0;
> + /* Generate interrupt only if OF bit is clear */
> + if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
> + env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
> + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> + }
> + } else {
> + counter->mhpmcounterh_val++;
> + }
> + } else {
> + counter->mhpmcounter_val++;
> + }
> +
> + return 0;
> +}
> +
> +static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
> +{
> + CPURISCVState *env = &cpu->env;
> + PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
> + uint64_t max_val = UINT64_MAX;
> +
> + /* Privilege mode filtering */
> + if ((env->priv == PRV_M &&
> + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) ||
> + (env->priv == PRV_S &&
> + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) ||
> + (env->priv == PRV_U &&
> + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) {
> + return 0;
> + }
> +
> + /* Handle the overflow scenario */
> + if (counter->mhpmcounter_val == max_val) {
> + counter->mhpmcounter_val = 0;
> + /* Generate interrupt only if OF bit is clear */
> + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
> + env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
> + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> + }
> + } else {
> + counter->mhpmcounter_val++;
> + }
> + return 0;
> +}
> +
> +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)
> +{
> + uint32_t ctr_idx;
> + int ret;
> + CPURISCVState *env = &cpu->env;
> + gpointer value;
> +
> + value = g_hash_table_lookup(cpu->pmu_event_ctr_map,
> + GUINT_TO_POINTER(event_idx));
> + if (!value) {
> + return -1;
> + }
> +
> + ctr_idx = GPOINTER_TO_UINT(value);
> + if (!riscv_pmu_counter_enabled(cpu, ctr_idx) ||
> + get_field(env->mcountinhibit, BIT(ctr_idx))) {
> + return -1;
> + }
> +
> + if (riscv_cpu_is_32bit(env)) {
> + ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx);
> + } else {
> + ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx);
> + }
> +
> + return ret;
> +}
> +
> bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
> uint32_t target_ctr)
> {
> - return (target_ctr == 0) ? true : false;
> + RISCVCPU *cpu;
> + uint32_t event_idx;
> + uint32_t ctr_idx;
> +
> + /* Fixed instret counter */
> + if (target_ctr == 2) {
> + return true;
> + }
> +
> + cpu = RISCV_CPU(env_cpu(env));
> + event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS;
> + ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
> + GUINT_TO_POINTER(event_idx)));
> + if (!ctr_idx) {
> + return false;
> + }
> +
> + return target_ctr == ctr_idx ? true : false;
> }
>
> bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
> {
> - return (target_ctr == 2) ? true : false;
> + RISCVCPU *cpu;
> + uint32_t event_idx;
> + uint32_t ctr_idx;
> +
> + /* Fixed mcycle counter */
> + if (target_ctr == 0) {
> + return true;
> + }
> +
> + cpu = RISCV_CPU(env_cpu(env));
> + event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES;
> + ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
> + GUINT_TO_POINTER(event_idx)));
> +
> + /* Counter zero is not used for event_ctr_map */
> + if (!ctr_idx) {
> + return false;
> + }
> +
> + return (target_ctr == ctr_idx) ? true : false;
> +}
> +
> +static gboolean pmu_remove_event_map(gpointer key, gpointer value,
> + gpointer udata)
> +{
> + return (GPOINTER_TO_UINT(value) == GPOINTER_TO_UINT(udata)) ? true :
> false;
> +}
> +
> +static int64_t pmu_icount_ticks_to_ns(int64_t value)
> +{
> + int64_t ret = 0;
> +
> + if (icount_enabled()) {
> + ret = icount_to_ns(value);
> + } else {
> + ret = (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value;
> + }
> +
> + return ret;
> +}
> +
> +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
> + uint32_t ctr_idx)
> +{
> + uint32_t event_idx;
> + RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +
> + if (!riscv_pmu_counter_valid(cpu, ctr_idx)) {
> + return -1;
> + }
> +
> + /**
> + * Expected mhpmevent value is zero for reset case. Remove the current
> + * mapping.
> + */
> + if (!value) {
> + g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
> + pmu_remove_event_map,
> + GUINT_TO_POINTER(ctr_idx));
> + return 0;
> + }
> +
> + event_idx = value & MHPMEVENT_IDX_MASK;
> + if (g_hash_table_lookup(cpu->pmu_event_ctr_map,
> + GUINT_TO_POINTER(event_idx))) {
> + return 0;
> + }
> +
> + switch (event_idx) {
> + case RISCV_PMU_EVENT_HW_CPU_CYCLES:
> + case RISCV_PMU_EVENT_HW_INSTRUCTIONS:
> + case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS:
> + case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS:
> + case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS:
> + break;
> + default:
> + /* We don't support any raw events right now */
> + return -1;
> + }
> + g_hash_table_insert(cpu->pmu_event_ctr_map,
> GUINT_TO_POINTER(event_idx),
> + GUINT_TO_POINTER(ctr_idx));
> +
> + return 0;
> +}
> +
> +static void pmu_timer_trigger_irq(RISCVCPU *cpu,
> + enum riscv_pmu_event_idx evt_idx)
> +{
> + uint32_t ctr_idx;
> + CPURISCVState *env = &cpu->env;
> + PMUCTRState *counter;
> + target_ulong *mhpmevent_val;
> + uint64_t of_bit_mask;
> + int64_t irq_trigger_at;
> +
> + if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES &&
> + evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) {
> + return;
> + }
> +
> + ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
> + GUINT_TO_POINTER(evt_idx)));
> + if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {
> + return;
> + }
> +
> + if (riscv_cpu_is_32bit(env)) {
> + mhpmevent_val = &env->mhpmeventh_val[ctr_idx];
> + of_bit_mask = MHPMEVENTH_BIT_OF;
> + } else {
> + mhpmevent_val = &env->mhpmevent_val[ctr_idx];
> + of_bit_mask = MHPMEVENT_BIT_OF;
> + }
> +
> + counter = &env->pmu_ctrs[ctr_idx];
> + if (counter->irq_overflow_left > 0) {
> + irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> + counter->irq_overflow_left;
> + timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at);
> + counter->irq_overflow_left = 0;
> + return;
> + }
> +
> + if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) {
> + /* Generate interrupt only if OF bit is clear */
> + if (!(*mhpmevent_val & of_bit_mask)) {
> + *mhpmevent_val |= of_bit_mask;
> + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> + }
> + }
> +}
> +
> +/* Timer callback for instret and cycle counter overflow */
> +void riscv_pmu_timer_cb(void *priv)
> +{
> + RISCVCPU *cpu = priv;
> +
> + /* Timer event was triggered only for these events */
> + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES);
> + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS);
> +}
> +
> +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t
> ctr_idx)
> +{
> + uint64_t overflow_delta, overflow_at;
> + int64_t overflow_ns, overflow_left = 0;
> + RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> + PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
> +
> + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscof) {
> + return -1;
> + }
> +
> + if (value) {
> + overflow_delta = UINT64_MAX - value + 1;
> + } else {
> + overflow_delta = UINT64_MAX - value;
> + }
> +
> + /**
> + * QEMU supports only int64_t timers while RISC-V counters are
> uint64_t.
> + * Compute the leftover and save it so that it can be reprogrammed
> again
> + * when timer expires.
> + */
> + if (overflow_delta > INT64_MAX) {
> + overflow_left = overflow_delta - INT64_MAX;
> + }
> +
> + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
> + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
> + overflow_ns = pmu_icount_ticks_to_ns((int64_t)overflow_delta);
> + overflow_left = pmu_icount_ticks_to_ns(overflow_left) ;
> + } else {
> + return -1;
> + }
> + overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> overflow_ns;
> +
> + if (overflow_at > INT64_MAX) {
> + overflow_left += overflow_at - INT64_MAX;
> + counter->irq_overflow_left = overflow_left;
> + overflow_at = INT64_MAX;
> + }
> + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
> +
> + return 0;
> +}
> +
> +
> +int riscv_pmu_init(RISCVCPU *cpu, int num_counters)
> +{
> + if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) {
> + return -1;
> + }
> +
> + cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash,
> g_direct_equal);
> + if (!cpu->pmu_event_ctr_map) {
> + /* PMU support can not be enabled */
> + qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n");
> + cpu->cfg.pmu_num = 0;
> + return -1;
> + }
> +
> + /* Create a bitmask of available programmable counters */
> + cpu->pmu_avail_ctrs = ~(-1 << (num_counters + 3)) & ~(0x07);
>
Hi Atish,
cpu->pmu_avail_ctrs mask would becomes 0x0 if num_counters equals to 29.
Perhaps it can be fixed with:
cpu->pmu_avail_ctrs = MAKE_64BIT_MASK(3, num_counters);
or some other similar techniques.
Regards,
Frank Chang
> + return 0;
> }
> diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
> index 58a5bc3a4089..af78da92e820 100644
> --- a/target/riscv/pmu.h
> +++ b/target/riscv/pmu.h
> @@ -26,3 +26,12 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState
> *env,
> uint32_t target_ctr);
> bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
> uint32_t target_ctr);
> +void riscv_pmu_timer_cb(void *priv);
> +int riscv_pmu_init(RISCVCPU *cpu, int num_counters);
> +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
> + uint32_t ctr_idx);
> +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
> +void riscv_pmu_generate_fdt_node(void *fdt, char *pmu_name);
> +target_ulong get_icount_ticks(bool brv32);
> +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
> + uint32_t ctr_idx);
> --
> 2.31.1
>
>
>
[-- Attachment #2: Type: text/html, Size: 40686 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
2021-11-04 11:07 ` Bin Meng
@ 2022-01-05 21:46 ` Atish Patra
0 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2022-01-05 21:46 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Atish Patra, Alistair Francis, Palmer Dabbelt
On Thu, Nov 4, 2021 at 4:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 3:56 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
>
> The commit title is incomplete
>
Oops. Fixed it.
>
> > Currently, the predicate function for PMU related CSRs only works if
> > virtualization is enabled. It also does not check mcounteren bits before
> > before cycle/minstret/hpmcounterx access.
> >
> > Support supervisor mode access in the predicate function as well.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 52 insertions(+)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 1ec776013435..de484c74d3b4 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > #if !defined(CONFIG_USER_ONLY)
> > CPUState *cs = env_cpu(env);
> > RISCVCPU *cpu = RISCV_CPU(cs);
> > + int ctr_index;
> >
> > if (!cpu->cfg.ext_counters) {
> > /* The Counters extensions is not enabled */
> > return RISCV_EXCP_ILLEGAL_INST;
> > }
> >
> > + if (env->priv == PRV_S) {
> > + switch (csrno) {
> > + case CSR_CYCLE:
> > + if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > + break;
> > + case CSR_TIME:
> > + if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > + break;
> > + case CSR_INSTRET:
> > + if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > + break;
> > + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> > + ctr_index = csrno - CSR_CYCLE;
> > + if (!get_field(env->mcounteren, 1 << ctr_index)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > + break;
>
> The above switch..case can be simplified with the logic of last case
> as the same one applies to all cases.
>
I did not condense it because I wanted to keep it analogous to the
virtualization case.
But I agree that it should be much shorter in both cases. I will add a
separate patch to simplify the entire function for
all the cases.
> > + }
> > + if (riscv_cpu_is_32bit(env)) {
> > + switch (csrno) {
> > + case CSR_CYCLEH:
> > + if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > + break;
> > + case CSR_TIMEH:
> > + if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > + break;
> > + case CSR_INSTRETH:
> > + if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > + break;
> > + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> > + ctr_index = csrno - CSR_CYCLEH;
> > + if (!get_field(env->mcounteren, 1 << ctr_index)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
>
> ditto
>
> > + break;
> > + }
> > + }
> > + }
> > +
> > if (riscv_cpu_virt_enabled(env)) {
> > switch (csrno) {
> > case CSR_CYCLE:
> >
>
> Regards,
> Bin
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
2021-11-04 11:10 ` Bin Meng
@ 2022-01-05 21:48 ` Atish Patra
0 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2022-01-05 21:48 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Atish Patra, Alistair Francis, Palmer Dabbelt
On Thu, Nov 4, 2021 at 4:11 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 4:02 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > The PMU counters are supported via cpu config "Counters" which doesn't
> > indicate the correct purpose of those counters.
> >
> > Rename the config property to pmu to indicate that these counters
> > are performance monitoring counters. This aligns with cpu options for
> > ARM architecture as well.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > target/riscv/cpu.c | 2 +-
> > target/riscv/cpu.h | 2 +-
> > target/riscv/csr.c | 2 +-
> > 3 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1d69d1887e63..3b55f5ed0036 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> > - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > + DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 9e55b2f5b170..ebc1a8754032 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -294,7 +294,7 @@ struct RISCVCPU {
> > bool ext_zbb;
> > bool ext_zbc;
> > bool ext_zbs;
> > - bool ext_counters;
> > + bool ext_pmu;
> > bool ext_ifencei;
> > bool ext_icsr;
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index de484c74d3b4..c486eeaffeb8 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > RISCVCPU *cpu = RISCV_CPU(cs);
> > int ctr_index;
> >
> > - if (!cpu->cfg.ext_counters) {
> > + if (!cpu->cfg.ext_pmu) {
> > /* The Counters extensions is not enabled */
>
> %s/Counters extensions/PMU extension
>
Thanks. Fixed it.
> > return RISCV_EXCP_ILLEGAL_INST;
> > }
> > --
>
> Otherwise,
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
2021-11-04 11:45 ` Bin Meng
@ 2022-01-05 21:51 ` Atish Patra
0 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2022-01-05 21:51 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Atish Patra, Alistair Francis, Palmer Dabbelt
On Thu, Nov 4, 2021 at 4:47 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 4:41 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > The RISC-V privilege specification provides flexibility to implement
> > any number of counters from 29 programmable counters. However, the QEMU
> > implements all the counters.
> >
> > Make it configurable through pmu config parameter which now will indicate
> > how many programmable counters should be implemented by the cpu.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > target/riscv/cpu.c | 2 +-
> > target/riscv/cpu.h | 2 +-
> > target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++----------------
> > 3 files changed, 65 insertions(+), 35 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 3b55f5ed0036..aec94101a4c0 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> > - DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> > + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
> > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index ebc1a8754032..d0a722e7cbe1 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -294,10 +294,10 @@ struct RISCVCPU {
> > bool ext_zbb;
> > bool ext_zbc;
> > bool ext_zbs;
> > - bool ext_pmu;
> > bool ext_ifencei;
> > bool ext_icsr;
> >
> > + uint8_t pmu_num;
> > char *priv_spec;
> > char *user_spec;
> > char *bext_spec;
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index c486eeaffeb8..a7249eaf917f 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -57,15 +57,45 @@ static RISCVException vs(CPURISCVState *env, int csrno)
> > return RISCV_EXCP_ILLEGAL_INST;
> > }
> >
> > +static RISCVException mctr(CPURISCVState *env, int csrno)
> > +{
> > +#if !defined(CONFIG_USER_ONLY)
> > + CPUState *cs = env_cpu(env);
> > + RISCVCPU *cpu = RISCV_CPU(cs);
> > + int ctr_index;
> > + int base_csrno = CSR_MHPMCOUNTER3;
> > +
> > + if (riscv_cpu_is_32bit(env) && csrno >= CSR_MCYCLEH) {
> > + /* Offset for RV32 mhpmcounternh counters */
> > + base_csrno += 0x80;
> > + }
> > + ctr_index = csrno - base_csrno;
> > + if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
> > + /* The PMU is not enabled or counter is out of range*/
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + return RISCV_EXCP_NONE;
> > +#endif
> > +}
> > +
> > static RISCVException ctr(CPURISCVState *env, int csrno)
> > {
> > #if !defined(CONFIG_USER_ONLY)
> > CPUState *cs = env_cpu(env);
> > RISCVCPU *cpu = RISCV_CPU(cs);
> > int ctr_index;
> > + int base_csrno = CSR_CYCLE;
>
> Use CSR_HPMCOUNTER3 here, for consistency with the mctr version
ok. Fixed it.
>
> > + bool brv32 = riscv_cpu_is_32bit(env);
>
> nits: the leading 'b' sounds useless. I would use rv32 instead.
>
Sure. Fixed it.
> > +
> > + if (brv32 && csrno >= CSR_CYCLEH) {
> > + /* Offset for RV32 hpmcounternh counters */
> > + base_csrno += 0x80;
> > + }
> > + ctr_index = csrno - base_csrno;
> >
> > - if (!cpu->cfg.ext_pmu) {
> > - /* The Counters extensions is not enabled */
> > + if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
>
> so we can use "ctr_index >= cpu->cfg.pmu_num" here
>
> > + /* The PMU is not enabled or counter is out of range */
> > return RISCV_EXCP_ILLEGAL_INST;
> > }
> >
> > @@ -93,7 +123,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > }
> > break;
> > }
> > - if (riscv_cpu_is_32bit(env)) {
> > + if (brv32) {
> > switch (csrno) {
> > case CSR_CYCLEH:
> > if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> > @@ -148,7 +178,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > }
> > break;
> > }
> > - if (riscv_cpu_is_32bit(env)) {
> > + if (brv32) {
> > switch (csrno) {
> > case CSR_CYCLEH:
> > if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> > @@ -1720,35 +1750,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
> > [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
> >
> > - [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
> > - [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
> > - [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
> > - [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
> > - [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
> > - [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
> > - [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
> > - [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
> > - [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
> > - [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
> > - [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
> > - [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
> > - [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
> > - [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
> > - [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
> > - [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
> > - [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
> > - [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
> > - [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
> > - [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
> > - [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
> > - [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
> > - [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
> > - [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
> > - [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
> > - [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
> > - [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
> > - [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
> > - [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
> > + [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
> > + [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
> > + [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
> > + [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
> > + [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
> > + [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
> > + [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
> > + [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
> > + [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
> > + [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
> > + [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
> > + [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
> > + [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
> > + [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
> > + [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
> > + [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
> > + [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
> > + [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
> > + [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
> > + [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
> > + [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
> > + [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
> > + [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
> > + [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
> > + [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
> > + [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
> > + [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
> > + [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
> > + [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
> >
> > [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
> > [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
>
> Regards,
> Bin
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
2021-12-27 4:37 ` Frank Chang
@ 2022-01-07 0:38 ` Atish Patra
0 siblings, 0 replies; 26+ messages in thread
From: Atish Patra @ 2022-01-07 0:38 UTC (permalink / raw)
To: Frank Chang
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Sun, Dec 26, 2021 at 8:38 PM Frank Chang <frank.chang@sifive.com> wrote:
>
> Atish Patra <atish.patra@wdc.com> 於 2021年10月26日 週二 上午3:57寫道：
>>
>> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
>> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
>> extension allows the perf to handle overflow interrupts and filtering
>> support. This patch provides a framework for programmable
>> counters to leverage the extension. As the extension doesn't have any
>> provision for the overflow bit for fixed counters, the fixed events
>> can also be monitoring using programmable counters. The underlying
>> counters for cycle and instruction counters are always running. Thus,
>> a separate timer device is programmed to handle the overflow.
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> ---
>> target/riscv/cpu.c | 12 ++
>> target/riscv/cpu.h | 25 +++
>> target/riscv/cpu_bits.h | 55 +++++++
>> target/riscv/csr.c | 150 +++++++++++++++++-
>> target/riscv/machine.c | 2 +-
>> target/riscv/pmu.c | 343 +++++++++++++++++++++++++++++++++++++++-
>> target/riscv/pmu.h | 9 ++
>> 7 files changed, 589 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index aec94101a4c0..757c646037bb 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -22,6 +22,7 @@
>> #include "qemu/ctype.h"
>> #include "qemu/log.h"
>> #include "cpu.h"
>> +#include "pmu.h"
>> #include "internals.h"
>> #include "exec/exec-all.h"
>> #include "qapi/error.h"
>> @@ -535,6 +536,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> set_misa(env, target_misa);
>> }
>>
>> + if (cpu->cfg.pmu_num) {
>> + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscof) {
>> + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
>> + riscv_pmu_timer_cb, cpu);
>> + if (!cpu->pmu_timer) {
>> + cpu->cfg.ext_sscof = false;
>> + }
>> + }
>> + }
>> +
>> riscv_cpu_register_gdb_regs_for_features(cs);
>>
>> qemu_init_vcpu(cs);
>> @@ -599,6 +610,7 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>> DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>> + DEFINE_PROP_BOOL("sscof", RISCVCPU, cfg.ext_sscof, false),
>> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index da34614ad788..b66d8acff109 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -123,6 +123,8 @@ struct PMUCTRState {
>> /* Snapshort value of a counter in RV32 */
>> target_ulong mhpmcounterh_prev;
>> bool started;
>> + /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
>> + target_ulong irq_overflow_left;
>> };
>>
>> struct CPURISCVState {
>> @@ -241,6 +243,9 @@ struct CPURISCVState {
>> /* PMU event selector configured values. First three are unused*/
>> target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
>>
>> + /* PMU event selector configured values for RV32*/
>> + target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
>> +
>> target_ulong sscratch;
>> target_ulong mscratch;
>>
>> @@ -320,6 +325,7 @@ struct RISCVCPU {
>> bool ext_zbs;
>> bool ext_ifencei;
>> bool ext_icsr;
>> + bool ext_sscof;
>>
>> uint8_t pmu_num;
>> char *priv_spec;
>> @@ -333,6 +339,12 @@ struct RISCVCPU {
>> bool epmp;
>> uint64_t resetvec;
>> } cfg;
>> +
>> + QEMUTimer *pmu_timer;
>> + /* A bitmask of Available programmable counters */
>> + uint32_t pmu_avail_ctrs;
>> + /* Mapping of events to counters */
>> + GHashTable *pmu_event_ctr_map;
>> };
>>
>> static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
>> @@ -528,6 +540,19 @@ enum {
>> CSR_TABLE_SIZE = 0x1000
>> };
>>
>> +/**
>> + * The event id are encoded based on the encoding specified in the
>> + * SBI specification v0.3
>> + */
>> +
>> +enum riscv_pmu_event_idx {
>> + RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
>> + RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
>> + RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
>> + RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
>> + RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
>> +};
>> +
>> /* CSR function table */
>> extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
>>
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index 72b1485e621f..cd6523c1c6ee 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -308,6 +308,37 @@
>> #define CSR_MHPMEVENT29 0x33d
>> #define CSR_MHPMEVENT30 0x33e
>> #define CSR_MHPMEVENT31 0x33f
>> +
>> +#define CSR_MHPMEVENT3H 0x723
>> +#define CSR_MHPMEVENT4H 0x724
>> +#define CSR_MHPMEVENT5H 0x725
>> +#define CSR_MHPMEVENT6H 0x726
>> +#define CSR_MHPMEVENT7H 0x727
>> +#define CSR_MHPMEVENT8H 0x728
>> +#define CSR_MHPMEVENT9H 0x729
>> +#define CSR_MHPMEVENT10H 0x72a
>> +#define CSR_MHPMEVENT11H 0x72b
>> +#define CSR_MHPMEVENT12H 0x72c
>> +#define CSR_MHPMEVENT13H 0x72d
>> +#define CSR_MHPMEVENT14H 0x72e
>> +#define CSR_MHPMEVENT15H 0x72f
>> +#define CSR_MHPMEVENT16H 0x730
>> +#define CSR_MHPMEVENT17H 0x731
>> +#define CSR_MHPMEVENT18H 0x732
>> +#define CSR_MHPMEVENT19H 0x733
>> +#define CSR_MHPMEVENT20H 0x734
>> +#define CSR_MHPMEVENT21H 0x735
>> +#define CSR_MHPMEVENT22H 0x736
>> +#define CSR_MHPMEVENT23H 0x737
>> +#define CSR_MHPMEVENT24H 0x738
>> +#define CSR_MHPMEVENT25H 0x739
>> +#define CSR_MHPMEVENT26H 0x73a
>> +#define CSR_MHPMEVENT27H 0x73b
>> +#define CSR_MHPMEVENT28H 0x73c
>> +#define CSR_MHPMEVENT29H 0x73d
>> +#define CSR_MHPMEVENT30H 0x73e
>> +#define CSR_MHPMEVENT31H 0x73f
>> +
>> #define CSR_MHPMCOUNTER3H 0xb83
>> #define CSR_MHPMCOUNTER4H 0xb84
>> #define CSR_MHPMCOUNTER5H 0xb85
>> @@ -338,6 +369,8 @@
>> #define CSR_MHPMCOUNTER30H 0xb9e
>> #define CSR_MHPMCOUNTER31H 0xb9f
>>
>> +#define CSR_SCOUNTOVF 0xda0
>> +
>> /* mstatus CSR bits */
>> #define MSTATUS_UIE 0x00000001
>> #define MSTATUS_SIE 0x00000002
>> @@ -508,6 +541,7 @@ typedef enum RISCVException {
>> #define IRQ_S_EXT 9
>> #define IRQ_VS_EXT 10
>> #define IRQ_M_EXT 11
>> +#define IRQ_PMU_OVF 13
>>
>> /* mip masks */
>> #define MIP_USIP (1 << IRQ_U_SOFT)
>> @@ -522,11 +556,13 @@ typedef enum RISCVException {
>> #define MIP_SEIP (1 << IRQ_S_EXT)
>> #define MIP_VSEIP (1 << IRQ_VS_EXT)
>> #define MIP_MEIP (1 << IRQ_M_EXT)
>> +#define MIP_LCOFIP (1 << IRQ_PMU_OVF)
>>
>> /* sip masks */
>> #define SIP_SSIP MIP_SSIP
>> #define SIP_STIP MIP_STIP
>> #define SIP_SEIP MIP_SEIP
>> +#define SIP_LCOFIP MIP_LCOFIP
>>
>> /* MIE masks */
>> #define MIE_SEIE (1 << IRQ_S_EXT)
>> @@ -535,4 +571,23 @@ typedef enum RISCVException {
>> #define MIE_UTIE (1 << IRQ_U_TIMER)
>> #define MIE_SSIE (1 << IRQ_S_SOFT)
>> #define MIE_USIE (1 << IRQ_U_SOFT)
>> +#define MIE_LCOFIE (1 << IRQ_PMU_OVF)
>> +
>> +#define MHPMEVENT_BIT_OF BIT(63)
>> +#define MHPMEVENTH_BIT_OF BIT(31)
>> +#define MHPMEVENT_BIT_MINH BIT(62)
>> +#define MHPMEVENTH_BIT_MINH BIT(30)
>> +#define MHPMEVENT_BIT_SINH BIT(61)
>> +#define MHPMEVENTH_BIT_SINH BIT(29)
>> +#define MHPMEVENT_BIT_UINH BIT(60)
>> +#define MHPMEVENTH_BIT_UINH BIT(28)
>> +#define MHPMEVENT_BIT_VSINH BIT(59)
>> +#define MHPMEVENTH_BIT_VSINH BIT(27)
>> +#define MHPMEVENT_BIT_VUINH BIT(58)
>> +#define MHPMEVENTH_BIT_VUINH BIT(26)
>> +
>> +#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
>> +#define MHPMEVENT_IDX_MASK 0xFFFFF
>> +#define MHPMEVENT_SSCOF_RESVD 16
>> +
>> #endif
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 1ce1bb0868d7..6a1580c4b6ce 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -89,6 +89,19 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
>> return mctr(env, csrno);
>> }
>>
>> +static RISCVException sscof(CPURISCVState *env, int csrno)
>> +{
>> + #if !defined(CONFIG_USER_ONLY)
>> + CPUState *cs = env_cpu(env);
>> + RISCVCPU *cpu = RISCV_CPU(cs);
>> +
>> + if (!cpu->cfg.ext_sscof) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>> +#endif
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> static RISCVException ctr(CPURISCVState *env, int csrno)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> @@ -104,11 +117,18 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>> }
>> ctr_index = csrno - base_csrno;
>>
>> - if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
>> + if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
>> + (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
>> + goto skip_ext_pmu_check;
>> + }
>> +
>> + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) {
>> /* The PMU is not enabled or counter is out of range */
>> return RISCV_EXCP_ILLEGAL_INST;
>> }
>>
>> +skip_ext_pmu_check:
>> +
>> if (env->priv == PRV_S) {
>> switch (csrno) {
>> case CSR_CYCLE:
>> @@ -424,7 +444,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno,
>> }
>>
>> /* User Timers and Counters */
>> -static target_ulong get_icount_ticks(bool brv32)
>> +target_ulong get_icount_ticks(bool brv32)
>> {
>> int64_t val;
>> target_ulong result;
>> @@ -461,11 +481,36 @@ static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
>> {
>> int evt_index = csrno - CSR_MCOUNTINHIBIT;
>>
>> + if (!riscv_cpu_is_32bit(env)) {
>> + riscv_pmu_update_event_map(env, val, evt_index);
>> + }
>> env->mhpmevent_val[evt_index] = val;
>>
>> return RISCV_EXCP_NONE;
>> }
>>
>> +static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val)
>> +{
>> + int evt_index = csrno - CSR_MHPMEVENT3H + 3;
>> +
>> + *val = env->mhpmevent_val[evt_index];
>> +
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val)
>> +{
>> + int evt_index = csrno - CSR_MHPMEVENT3H + 3;
>> + uint64_t mhpmevth_val = val;
>> + uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
>> +
>> + mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
>> + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
>> + env->mhpmeventh_val[evt_index] = val;
>> +
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
>> {
>> int ctr_idx = csrno - CSR_MCYCLE;
>> @@ -475,6 +520,9 @@ static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
>> if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
>> riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
>> counter->mhpmcounter_prev = get_icount_ticks(false);
>> + if (ctr_idx > 2) {
>> + riscv_pmu_setup_timer(env, val, ctr_idx);
>> + }
>> } else {
>> /* Other counters can keep incrementing from the given value */
>> counter->mhpmcounter_prev = val;
>> @@ -487,11 +535,17 @@ static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
>> {
>> int ctr_idx = csrno - CSR_MCYCLEH;
>> PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
>> + uint64_t mhpmctr_val = counter->mhpmcounter_val;
>> + uint64_t mhpmctrh_val = val;
>>
>> counter->mhpmcounterh_val = val;
>> + mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32);
>> if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
>> riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
>> counter->mhpmcounterh_prev = get_icount_ticks(false);
>> + if (ctr_idx > 2) {
>> + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);
>> + }
>> } else {
>> counter->mhpmcounterh_prev = val;
>> }
>> @@ -561,6 +615,32 @@ static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
>> return riscv_pmu_read_ctr(env, val, true, ctr_index);
>> }
>>
>> +static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val)
>> +{
>> + int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
>> + int i;
>> + *val = 0;
>> + target_ulong *mhpm_evt_val;
>> + uint64_t of_bit_mask;
>> +
>> + if (riscv_cpu_is_32bit(env)) {
>> + mhpm_evt_val = env->mhpmeventh_val;
>> + of_bit_mask = MHPMEVENTH_BIT_OF;
>> + } else {
>> + mhpm_evt_val = env->mhpmevent_val;
>> + of_bit_mask = MHPMEVENT_BIT_OF;
>> + }
>> +
>> + for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
>> + if ((get_field(env->mcounteren, BIT(i))) &&
>> + (mhpm_evt_val[i] & of_bit_mask)) {
>> + *val |= BIT(i);
>> + }
>> + }
>> +
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> #if defined(CONFIG_USER_ONLY)
>> static RISCVException read_time(CPURISCVState *env, int csrno,
>> target_ulong *val)
>> @@ -607,7 +687,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
>> /* Machine constants */
>>
>> #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
>> -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
>> +#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP | MIP_LCOFIP)
>> #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
>>
>> static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
>> @@ -645,7 +725,8 @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
>> static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
>> SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
>> SSTATUS_SUM | SSTATUS_MXR;
>> -static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
>> +static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
>> + SIP_LCOFIP;
>> static const target_ulong hip_writable_mask = MIP_VSSIP;
>> static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
>> static const target_ulong vsip_writable_mask = MIP_VSSIP;
>> @@ -2022,6 +2103,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>> [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
>> write_mhpmevent },
>>
>> + [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> + [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscof, read_mhpmeventh,
>> + write_mhpmeventh},
>> +
>> [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
>> [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
>> [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh },
>> @@ -2110,5 +2250,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>> write_mhpmcounterh },
>> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
>> write_mhpmcounterh },
>> + [CSR_SCOUNTOVF] = { "scountovf", sscof, read_scountovf },
>> +
>> #endif /* !CONFIG_USER_ONLY */
>> };
>> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
>> index e0a489c20e67..7b2ef17904a9 100644
>> --- a/target/riscv/machine.c
>> +++ b/target/riscv/machine.c
>> @@ -88,7 +88,7 @@ static bool pmu_needed(void *opaque)
>> {
>> RISCVCPU *cpu = opaque;
>>
>> - return cpu->cfg.ext_pmu;
>> + return cpu->cfg.pmu_num;
>> }
>>
>> static const VMStateDescription vmstate_vector = {
>> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
>> index 000fe8da45ef..25bdbdf48ff7 100644
>> --- a/target/riscv/pmu.c
>> +++ b/target/riscv/pmu.c
>> @@ -20,13 +20,352 @@
>> #include "cpu.h"
>> #include "pmu.h"
>>
>> +#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
>> +
>> +static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
>> +{
>> + if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||
>> + !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) {
>> + return false;
>> + } else {
>> + return true;
>> + }
>> +}
>> +
>> +static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx)
>> +{
>> + CPURISCVState *env = &cpu->env;
>> +
>> + if (!riscv_pmu_counter_valid(cpu, ctr_idx) ||
>> + !get_field(env->mcounteren, BIT(ctr_idx))) {
>> + return false;
>> + } else {
>> + return true;
>> + }
>> +}
>> +
>> +static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
>> +{
>> + CPURISCVState *env = &cpu->env;
>> + target_ulong max_val = UINT32_MAX;
>> + PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
>> +
>> + /* Privilege mode filtering */
>> + if ((env->priv == PRV_M &&
>> + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) ||
>> + (env->priv == PRV_S &&
>> + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) ||
>> + (env->priv == PRV_U &&
>> + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) {
>> + return 0;
>> + }
>> +
>> + /* Handle the overflow scenario */
>> + if (counter->mhpmcounter_val == max_val) {
>> + if (counter->mhpmcounterh_val == max_val) {
>> + counter->mhpmcounter_val = 0;
>> + counter->mhpmcounterh_val = 0;
>> + /* Generate interrupt only if OF bit is clear */
>> + if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
>> + env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
>> + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
>> + }
>> + } else {
>> + counter->mhpmcounterh_val++;
>> + }
>> + } else {
>> + counter->mhpmcounter_val++;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
>> +{
>> + CPURISCVState *env = &cpu->env;
>> + PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
>> + uint64_t max_val = UINT64_MAX;
>> +
>> + /* Privilege mode filtering */
>> + if ((env->priv == PRV_M &&
>> + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) ||
>> + (env->priv == PRV_S &&
>> + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) ||
>> + (env->priv == PRV_U &&
>> + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) {
>> + return 0;
>> + }
>> +
>> + /* Handle the overflow scenario */
>> + if (counter->mhpmcounter_val == max_val) {
>> + counter->mhpmcounter_val = 0;
>> + /* Generate interrupt only if OF bit is clear */
>> + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
>> + env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
>> + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
>> + }
>> + } else {
>> + counter->mhpmcounter_val++;
>> + }
>> + return 0;
>> +}
>> +
>> +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)
>> +{
>> + uint32_t ctr_idx;
>> + int ret;
>> + CPURISCVState *env = &cpu->env;
>> + gpointer value;
>> +
>> + value = g_hash_table_lookup(cpu->pmu_event_ctr_map,
>> + GUINT_TO_POINTER(event_idx));
>> + if (!value) {
>> + return -1;
>> + }
>> +
>> + ctr_idx = GPOINTER_TO_UINT(value);
>> + if (!riscv_pmu_counter_enabled(cpu, ctr_idx) ||
>> + get_field(env->mcountinhibit, BIT(ctr_idx))) {
>> + return -1;
>> + }
>> +
>> + if (riscv_cpu_is_32bit(env)) {
>> + ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx);
>> + } else {
>> + ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
>> uint32_t target_ctr)
>> {
>> - return (target_ctr == 0) ? true : false;
>> + RISCVCPU *cpu;
>> + uint32_t event_idx;
>> + uint32_t ctr_idx;
>> +
>> + /* Fixed instret counter */
>> + if (target_ctr == 2) {
>> + return true;
>> + }
>> +
>> + cpu = RISCV_CPU(env_cpu(env));
>> + event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS;
>> + ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
>> + GUINT_TO_POINTER(event_idx)));
>> + if (!ctr_idx) {
>> + return false;
>> + }
>> +
>> + return target_ctr == ctr_idx ? true : false;
>> }
>>
>> bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
>> {
>> - return (target_ctr == 2) ? true : false;
>> + RISCVCPU *cpu;
>> + uint32_t event_idx;
>> + uint32_t ctr_idx;
>> +
>> + /* Fixed mcycle counter */
>> + if (target_ctr == 0) {
>> + return true;
>> + }
>> +
>> + cpu = RISCV_CPU(env_cpu(env));
>> + event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES;
>> + ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
>> + GUINT_TO_POINTER(event_idx)));
>> +
>> + /* Counter zero is not used for event_ctr_map */
>> + if (!ctr_idx) {
>> + return false;
>> + }
>> +
>> + return (target_ctr == ctr_idx) ? true : false;
>> +}
>> +
>> +static gboolean pmu_remove_event_map(gpointer key, gpointer value,
>> + gpointer udata)
>> +{
>> + return (GPOINTER_TO_UINT(value) == GPOINTER_TO_UINT(udata)) ? true : false;
>> +}
>> +
>> +static int64_t pmu_icount_ticks_to_ns(int64_t value)
>> +{
>> + int64_t ret = 0;
>> +
>> + if (icount_enabled()) {
>> + ret = icount_to_ns(value);
>> + } else {
>> + ret = (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
>> + uint32_t ctr_idx)
>> +{
>> + uint32_t event_idx;
>> + RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
>> +
>> + if (!riscv_pmu_counter_valid(cpu, ctr_idx)) {
>> + return -1;
>> + }
>> +
>> + /**
>> + * Expected mhpmevent value is zero for reset case. Remove the current
>> + * mapping.
>> + */
>> + if (!value) {
>> + g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
>> + pmu_remove_event_map,
>> + GUINT_TO_POINTER(ctr_idx));
>> + return 0;
>> + }
>> +
>> + event_idx = value & MHPMEVENT_IDX_MASK;
>> + if (g_hash_table_lookup(cpu->pmu_event_ctr_map,
>> + GUINT_TO_POINTER(event_idx))) {
>> + return 0;
>> + }
>> +
>> + switch (event_idx) {
>> + case RISCV_PMU_EVENT_HW_CPU_CYCLES:
>> + case RISCV_PMU_EVENT_HW_INSTRUCTIONS:
>> + case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS:
>> + case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS:
>> + case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS:
>> + break;
>> + default:
>> + /* We don't support any raw events right now */
>> + return -1;
>> + }
>> + g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx),
>> + GUINT_TO_POINTER(ctr_idx));
>> +
>> + return 0;
>> +}
>> +
>> +static void pmu_timer_trigger_irq(RISCVCPU *cpu,
>> + enum riscv_pmu_event_idx evt_idx)
>> +{
>> + uint32_t ctr_idx;
>> + CPURISCVState *env = &cpu->env;
>> + PMUCTRState *counter;
>> + target_ulong *mhpmevent_val;
>> + uint64_t of_bit_mask;
>> + int64_t irq_trigger_at;
>> +
>> + if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES &&
>> + evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) {
>> + return;
>> + }
>> +
>> + ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
>> + GUINT_TO_POINTER(evt_idx)));
>> + if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {
>> + return;
>> + }
>> +
>> + if (riscv_cpu_is_32bit(env)) {
>> + mhpmevent_val = &env->mhpmeventh_val[ctr_idx];
>> + of_bit_mask = MHPMEVENTH_BIT_OF;
>> + } else {
>> + mhpmevent_val = &env->mhpmevent_val[ctr_idx];
>> + of_bit_mask = MHPMEVENT_BIT_OF;
>> + }
>> +
>> + counter = &env->pmu_ctrs[ctr_idx];
>> + if (counter->irq_overflow_left > 0) {
>> + irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
>> + counter->irq_overflow_left;
>> + timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at);
>> + counter->irq_overflow_left = 0;
>> + return;
>> + }
>> +
>> + if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) {
>> + /* Generate interrupt only if OF bit is clear */
>> + if (!(*mhpmevent_val & of_bit_mask)) {
>> + *mhpmevent_val |= of_bit_mask;
>> + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
>> + }
>> + }
>> +}
>> +
>> +/* Timer callback for instret and cycle counter overflow */
>> +void riscv_pmu_timer_cb(void *priv)
>> +{
>> + RISCVCPU *cpu = priv;
>> +
>> + /* Timer event was triggered only for these events */
>> + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES);
>> + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS);
>> +}
>> +
>> +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
>> +{
>> + uint64_t overflow_delta, overflow_at;
>> + int64_t overflow_ns, overflow_left = 0;
>> + RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
>> + PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
>> +
>> + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscof) {
>> + return -1;
>> + }
>> +
>> + if (value) {
>> + overflow_delta = UINT64_MAX - value + 1;
>> + } else {
>> + overflow_delta = UINT64_MAX - value;
>> + }
>> +
>> + /**
>> + * QEMU supports only int64_t timers while RISC-V counters are uint64_t.
>> + * Compute the leftover and save it so that it can be reprogrammed again
>> + * when timer expires.
>> + */
>> + if (overflow_delta > INT64_MAX) {
>> + overflow_left = overflow_delta - INT64_MAX;
>> + }
>> +
>> + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
>> + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
>> + overflow_ns = pmu_icount_ticks_to_ns((int64_t)overflow_delta);
>> + overflow_left = pmu_icount_ticks_to_ns(overflow_left) ;
>> + } else {
>> + return -1;
>> + }
>> + overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
>> +
>> + if (overflow_at > INT64_MAX) {
>> + overflow_left += overflow_at - INT64_MAX;
>> + counter->irq_overflow_left = overflow_left;
>> + overflow_at = INT64_MAX;
>> + }
>> + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
>> +
>> + return 0;
>> +}
>> +
>> +
>> +int riscv_pmu_init(RISCVCPU *cpu, int num_counters)
>> +{
>> + if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) {
>> + return -1;
>> + }
>> +
>> + cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal);
>> + if (!cpu->pmu_event_ctr_map) {
>> + /* PMU support can not be enabled */
>> + qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n");
>> + cpu->cfg.pmu_num = 0;
>> + return -1;
>> + }
>> +
>> + /* Create a bitmask of available programmable counters */
>> + cpu->pmu_avail_ctrs = ~(-1 << (num_counters + 3)) & ~(0x07);
>
>
> Hi Atish,
>
> cpu->pmu_avail_ctrs mask would becomes 0x0 if num_counters equals to 29.
> Perhaps it can be fixed with:
> cpu->pmu_avail_ctrs = MAKE_64BIT_MASK(3, num_counters);
> or some other similar techniques.
Thanks for catching it. Fixed in next version
>
> Regards,
> Frank Chang
>
>>
>> + return 0;
>> }
>> diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
>> index 58a5bc3a4089..af78da92e820 100644
>> --- a/target/riscv/pmu.h
>> +++ b/target/riscv/pmu.h
>> @@ -26,3 +26,12 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
>> uint32_t target_ctr);
>> bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
>> uint32_t target_ctr);
>> +void riscv_pmu_timer_cb(void *priv);
>> +int riscv_pmu_init(RISCVCPU *cpu, int num_counters);
>> +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
>> + uint32_t ctr_idx);
>> +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
>> +void riscv_pmu_generate_fdt_node(void *fdt, char *pmu_name);
>> +target_ulong get_icount_ticks(bool brv32);
>> +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
>> + uint32_t ctr_idx);
>> --
>> 2.31.1
>>
>>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-01-07 0:51 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
2021-11-03 5:40 ` Alistair Francis
2021-11-04 11:00 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for Atish Patra
2021-11-03 5:43 ` Alistair Francis
2021-11-04 11:07 ` Bin Meng
2022-01-05 21:46 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2021-11-03 5:47 ` Alistair Francis
2021-11-04 11:10 ` Bin Meng
2022-01-05 21:48 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Atish Patra
2021-11-03 5:50 ` Alistair Francis
2021-11-04 11:45 ` Bin Meng
2022-01-05 21:51 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR Atish Patra
2021-11-03 5:51 ` Alistair Francis
2021-11-04 11:49 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2021-10-25 19:55 ` [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation Atish Patra
2021-10-25 19:55 ` [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support Atish Patra
2021-12-27 4:37 ` Frank Chang
2022-01-07 0:38 ` Atish Patra
2021-10-25 19:56 ` [ PATCH v3 09/10] target/riscv: Add few cache related PMU events Atish Patra
2021-10-25 19:56 ` [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
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