From: Bin Meng <bmeng.cn@gmail.com>
To: Jonathan Behrens <jonathan@fintelia.io>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v3 3/3] target/riscv: Make the priv register writable by GDB
Date: Tue, 8 Oct 2019 20:32:30 +0800 [thread overview]
Message-ID: <CAEUhbmVGnVi_5LKFXYL3fMoPLHrLMYK0p_8MvnugiNkyh35TtQ@mail.gmail.com> (raw)
In-Reply-To: <20191008001318.219367-4-jonathan@fintelia.io>
On Tue, Oct 8, 2019 at 8:20 AM Jonathan Behrens <jonathan@fintelia.io> wrote:
>
> Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that
> the privilege mode is set to one of them. Once support for the H-extension is
> added, this code will also need to properly update the virtualization status
> when switching between VU/VS-modes and M-mode.
>
> Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
> ---
> target/riscv/gdbstub.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2019-10-08 12:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 0:13 [PATCH v3 0/3] target/riscv: Expose "priv" register for GDB Jonathan Behrens
2019-10-08 0:13 ` [PATCH v3 1/3] target/riscv: Tell gdbstub the correct number of CSRs Jonathan Behrens
2019-10-08 9:53 ` Bin Meng
2019-10-08 14:01 ` Jonathan Behrens
2019-10-08 16:18 ` Alistair Francis
2019-10-08 0:13 ` [PATCH v3 2/3] target/riscv: Expose priv register for GDB for reads Jonathan Behrens
2019-10-08 12:27 ` Bin Meng
2019-10-08 14:03 ` Jonathan Behrens
2019-10-08 0:13 ` [PATCH v3 3/3] target/riscv: Make the priv register writable by GDB Jonathan Behrens
2019-10-08 12:32 ` Bin Meng [this message]
2019-10-08 16:49 ` Alistair Francis
2019-10-08 0:17 ` [PATCH v3 0/3] target/riscv: Expose "priv" register for GDB Jonathan Behrens
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