Re: [PATCH v3 3/3] target/riscv: Make the priv register writable by GDB

[Alistair Francis <alistair23@gmail.com>]

On Mon, Oct 7, 2019 at 5:20 PM Jonathan Behrens <jonathan@fintelia.io> wrote:
>
> Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that
> the privilege mode is set to one of them. Once support for the H-extension is
> added, this code will also need to properly update the virtualization status
> when switching between VU/VS-modes and M-mode.
>
> Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/gdbstub.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 33cf7c4c7d..bc84b599c2 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -387,6 +387,15 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
>
>  static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
>  {
> +    if (n == 0) {
> +#ifndef CONFIG_USER_ONLY
> +        cs->priv = ldtul_p(mem_buf) & 0x3;
> +        if (cs->priv == PRV_H) {
> +            cs->priv = PRV_S;
> +        }
> +#endif
> +        return sizeof(target_ulong);
> +    }
>      return 0;
>  }
>
> --
> 2.23.0
>