From: Frank Chang <frank.chang@sifive.com>
To: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Cc: Chih-Min Chao <chihmin.chao@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v4 2/2] target/riscv: change the api for RVF/RVD fmin/fmax
Date: Wed, 20 Oct 2021 10:56:06 +0800 [thread overview]
Message-ID: <CAE_xrPg0Lhn3=83mBJmCMymiO9GgbMZv+LDLX13_azdPdfgXxg@mail.gmail.com> (raw)
In-Reply-To: <20211016085428.3001501-3-frank.chang@sifive.com>
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On Sat, Oct 16, 2021 at 4:54 PM <frank.chang@sifive.com> wrote:
> From: Chih-Min Chao <chihmin.chao@sifive.com>
>
> The sNaN propagation behavior has been changed since
> cd20cee7 in https://github.com/riscv/riscv-isa-manual.
>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/fpu_helper.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 8700516a14c..d62f4709002 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -174,14 +174,18 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t
> rs1, uint64_t rs2)
> {
> float32 frs1 = check_nanbox_s(rs1);
> float32 frs2 = check_nanbox_s(rs2);
> - return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
> + return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
> + float32_minnum(frs1, frs2, &env->fp_status) :
> + float32_minimum_number(frs1, frs2, &env->fp_status));
> }
>
> uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> float32 frs1 = check_nanbox_s(rs1);
> float32 frs2 = check_nanbox_s(rs2);
> - return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status));
> + return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
> + float32_maxnum(frs1, frs2, &env->fp_status) :
> + float32_maximum_number(frs1, frs2, &env->fp_status));
> }
>
> uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
> @@ -283,12 +287,16 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t
> frs1, uint64_t frs2)
>
> uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> {
> - return float64_minnum(frs1, frs2, &env->fp_status);
> + return env->priv_ver < PRIV_VERSION_1_11_0 ?
> + float64_minnum(frs1, frs2, &env->fp_status) :
> + float64_minimum_number(frs1, frs2, &env->fp_status);
> }
>
> uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> {
> - return float64_maxnum(frs1, frs2, &env->fp_status);
> + return env->priv_ver < PRIV_VERSION_1_11_0 ?
> + float64_maxnum(frs1, frs2, &env->fp_status) :
> + float64_maximum_number(frs1, frs2, &env->fp_status);
> }
>
> uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
> --
> 2.25.1
>
>
If we have decided to tie RVF with Privilege spec version for now as
discussed in:
https://patchew.org/QEMU/20211015065500.3850513-1-frank.chang@sifive.com/20211015065500.3850513-3-frank.chang@sifive.com/
then I think this patch doesn't require any further changes, right?
Regards,
Frank Chang
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next prev parent reply other threads:[~2021-10-20 2:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-16 8:54 [PATCH v4 0/2] add APIs to handle alternative sNaN propagation for fmax/fmin frank.chang
2021-10-16 8:54 ` [PATCH v4 1/2] softfloat: " frank.chang
2021-10-16 17:59 ` Richard Henderson
2021-10-16 8:54 ` [PATCH v4 2/2] target/riscv: change the api for RVF/RVD fmin/fmax frank.chang
2021-10-20 2:56 ` Frank Chang [this message]
2021-10-20 23:24 ` Alistair Francis
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