* [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook
@ 2019-10-08 20:51 Alistair Francis
2019-10-08 20:51 ` [PATCH v2 1/2] RISC-V: Handle bus errors in the page table walker Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Alistair Francis @ 2019-10-08 20:51 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
The do_unassigned_access hook has been deprecated and RISC-V is the last
user of it. Let's instead update the RISC-V implementation to use
do_transaction_failed instead.
After this series I used the 'git grep' regexes in
docs/devel/loads-stores.rst and these are the memory accesses inside
target/riscv:
monitor.c:102: cpu_physical_memory_read(pte_addr, &pte, ptesize);
cpu_helper.c:262: target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
cpu_helper.c:264: target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
translate.c:782: ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
gdbstub.c:328: env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
All of these look safe to me.
v2:
- Rebase on master
Palmer Dabbelt (2):
RISC-V: Handle bus errors in the page table walker
RISC-V: Implement cpu_do_transaction_failed
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 7 +++++--
target/riscv/cpu_helper.c | 23 ++++++++++++++++-------
3 files changed, 22 insertions(+), 10 deletions(-)
--
2.23.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] RISC-V: Handle bus errors in the page table walker
2019-10-08 20:51 [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook Alistair Francis
@ 2019-10-08 20:51 ` Alistair Francis
2019-10-08 20:51 ` [PATCH v2 2/2] RISC-V: Implement cpu_do_transaction_failed Alistair Francis
2019-10-08 21:29 ` [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook Palmer Dabbelt
2 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2019-10-08 20:51 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
From: Palmer Dabbelt <palmer@sifive.com>
We directly access physical memory while walking the page tables on
RISC-V, but while doing so we were using cpu_ld*() which does not report
bus errors. This patch converts the page table walker over to use
address_space_ld*(), which allows bus errors to be detected.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/riscv/cpu_helper.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6ece..c82e7ed52b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -169,7 +169,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
* (riscv_cpu_do_interrupt) is correct */
-
+ MemTxResult res;
+ MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx;
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
@@ -256,11 +257,16 @@ restart:
1 << MMU_DATA_LOAD, PRV_S)) {
return TRANSLATE_PMP_FAIL;
}
+
#if defined(TARGET_RISCV32)
- target_ulong pte = ldl_phys(cs->as, pte_addr);
+ target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
#elif defined(TARGET_RISCV64)
- target_ulong pte = ldq_phys(cs->as, pte_addr);
+ target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
#endif
+ if (res != MEMTX_OK) {
+ return TRANSLATE_FAIL;
+ }
+
hwaddr ppn = pte >> PTE_PPN_SHIFT;
if (!(pte & PTE_V)) {
--
2.23.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] RISC-V: Implement cpu_do_transaction_failed
2019-10-08 20:51 [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook Alistair Francis
2019-10-08 20:51 ` [PATCH v2 1/2] RISC-V: Handle bus errors in the page table walker Alistair Francis
@ 2019-10-08 20:51 ` Alistair Francis
2019-10-08 21:29 ` [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook Palmer Dabbelt
2 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2019-10-08 20:51 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
From: Palmer Dabbelt <palmer@sifive.com>
This converts our port over from cpu_do_unassigned_access to
cpu_do_transaction_failed, as cpu_do_unassigned_access has been
deprecated.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 7 +++++--
target/riscv/cpu_helper.c | 11 +++++++----
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f13e298a36..3939963b71 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -484,7 +484,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->do_unassigned_access = riscv_cpu_unassigned_access;
+ cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 124ed33ee4..8c64c68538 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -264,8 +264,11 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
- bool is_exec, int unused, unsigned size);
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c82e7ed52b..917252f71b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -408,20 +408,23 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
return phys_addr;
}
-void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
- bool is_exec, int unused, unsigned size)
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- if (is_write) {
+ if (access_type == MMU_DATA_STORE) {
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
} else {
cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
}
env->badaddr = addr;
- riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
+ riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
}
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
--
2.23.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook
2019-10-08 20:51 [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook Alistair Francis
2019-10-08 20:51 ` [PATCH v2 1/2] RISC-V: Handle bus errors in the page table walker Alistair Francis
2019-10-08 20:51 ` [PATCH v2 2/2] RISC-V: Implement cpu_do_transaction_failed Alistair Francis
@ 2019-10-08 21:29 ` Palmer Dabbelt
2019-10-25 13:56 ` Peter Maydell
2 siblings, 1 reply; 5+ messages in thread
From: Palmer Dabbelt @ 2019-10-08 21:29 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, qemu-riscv, qemu-devel, alistair23
On Tue, 08 Oct 2019 13:51:46 PDT (-0700), Alistair Francis wrote:
>
> The do_unassigned_access hook has been deprecated and RISC-V is the last
> user of it. Let's instead update the RISC-V implementation to use
> do_transaction_failed instead.
>
> After this series I used the 'git grep' regexes in
> docs/devel/loads-stores.rst and these are the memory accesses inside
> target/riscv:
>
> monitor.c:102: cpu_physical_memory_read(pte_addr, &pte, ptesize);
>
> cpu_helper.c:262: target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
> cpu_helper.c:264: target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
>
> translate.c:782: ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
>
> gdbstub.c:328: env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
>
> All of these look safe to me.
>
> v2:
> - Rebase on master
>
>
> Palmer Dabbelt (2):
> RISC-V: Handle bus errors in the page table walker
> RISC-V: Implement cpu_do_transaction_failed
>
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 7 +++++--
> target/riscv/cpu_helper.c | 23 ++++++++++++++++-------
> 3 files changed, 22 insertions(+), 10 deletions(-)
Thanks, these are in the queue.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook
2019-10-08 21:29 ` [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook Palmer Dabbelt
@ 2019-10-25 13:56 ` Peter Maydell
0 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2019-10-25 13:56 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: open list:RISC-V, Alistair Francis, QEMU Developers, Alistair Francis
On Tue, 8 Oct 2019 at 22:31, Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Tue, 08 Oct 2019 13:51:46 PDT (-0700), Alistair Francis wrote:
> >
> > The do_unassigned_access hook has been deprecated and RISC-V is the last
> > user of it. Let's instead update the RISC-V implementation to use
> > do_transaction_failed instead.
> >
> > After this series I used the 'git grep' regexes in
> > docs/devel/loads-stores.rst and these are the memory accesses inside
> > target/riscv:
> >
> > monitor.c:102: cpu_physical_memory_read(pte_addr, &pte, ptesize);
> >
> > cpu_helper.c:262: target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
> > cpu_helper.c:264: target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
> >
> > translate.c:782: ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
> >
> > gdbstub.c:328: env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> >
> > All of these look safe to me.
> >
> > v2:
> > - Rebase on master
> >
> >
> > Palmer Dabbelt (2):
> > RISC-V: Handle bus errors in the page table walker
> > RISC-V: Implement cpu_do_transaction_failed
> >
> > target/riscv/cpu.c | 2 +-
> > target/riscv/cpu.h | 7 +++++--
> > target/riscv/cpu_helper.c | 23 ++++++++++++++++-------
> > 3 files changed, 22 insertions(+), 10 deletions(-)
>
> Thanks, these are in the queue.
Ping! These still don't seem to be in master, and softfreeze
is rapidly approaching (it's on the 29th).
(As a general observation, flow of riscv patches into
master seems to be quite slow. My recommendation would tend
to be doing smaller pullrequests more frequently; I try to
push through accumulated target-arm patches at least once
a fortnight, though it depends on how many patches are
arriving.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
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2019-10-08 20:51 ` [PATCH v2 2/2] RISC-V: Implement cpu_do_transaction_failed Alistair Francis
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