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* [PULL v2 00/46] target-arm queue
@ 2020-02-21 16:18 Peter Maydell
  2020-02-21 17:00 ` Peter Maydell
  0 siblings, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2020-02-21 16:18 UTC (permalink / raw)
  To: qemu-devel

v1->v2 changes: dropped the last 6 patches from rth as there's
a problem with one of them that's too complicated to try to
fix up.

thanks
-- PMM

The following changes since commit a8c6af67e1e8d460e2c6e87070807e0a02c0fec2:

  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' into staging (2020-02-21 14:20:42 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221-1

for you to fetch changes up to 9eb4f58918a851fb46895fd9b7ce579afeac9d02:

  target/arm: Set MVFR0.FPSP for ARMv5 cpus (2020-02-21 16:07:03 +0000)

----------------------------------------------------------------
target-arm queue:
 * aspeed/scu: Implement chip ID register
 * hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
 * mainstone: Make providing flash images non-mandatory
 * z2: Make providing flash images non-mandatory
 * Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT
 * Minor performance improvement: spend less time recalculating hflags values
 * Code cleanup to isar_feature function tests
 * Implement ARMv8.1-PMU and ARMv8.4-PMU extensions
 * Bugfix: correct handling of PMCR_EL0.LC bit
 * Bugfix: correct definition of PMCRDP
 * Correctly implement ACTLR2, HACTLR2
 * allwinner: Wire up USB ports
 * Vectorize emulation of USHL, SSHL, PMUL*
 * xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
 * sh4: Fix PCI ISA IO memory subregion

----------------------------------------------------------------
Francisco Iglesias (1):
      xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd

Guenter Roeck (6):
      mainstone: Make providing flash images non-mandatory
      z2: Make providing flash images non-mandatory
      hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
      hcd-ehci: Introduce "companion-enable" sysbus property
      arm: allwinner: Wire up USB ports
      sh4: Fix PCI ISA IO memory subregion

Joel Stanley (2):
      aspeed/scu: Create separate write callbacks
      aspeed/scu: Implement chip ID register

Peter Maydell (21):
      target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
      target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
      target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
      target/arm: Define and use any_predinv isar_feature test
      target/arm: Factor out PMU register definitions
      target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
      target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
      target/arm: Define an aa32_pmu_8_1 isar feature test function
      target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
      target/arm: Stop assuming DBGDIDR always exists
      target/arm: Move DBGDIDR into ARMISARegisters
      target/arm: Read debug-related ID registers from KVM
      target/arm: Implement ARMv8.1-PMU extension
      target/arm: Implement ARMv8.4-PMU extension
      target/arm: Provide ARMv8.4-PMU in '-cpu max'
      target/arm: Correct definition of PMCRDP
      target/arm: Correct handling of PMCR_EL0.LC bit
      target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
      target/arm: Use isar_feature function for testing AA32HPD feature
      target/arm: Use FIELD_EX32 for testing 32-bit fields
      target/arm: Correctly implement ACTLR2, HACTLR2

Philippe Mathieu-Daudé (1):
      hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register

Richard Henderson (15):
      target/arm: Flush high bits of sve register after AdvSIMD EXT
      target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
      target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
      target/arm: Flush high bits of sve register after AdvSIMD INS
      target/arm: Use bit 55 explicitly for pauth
      target/arm: Fix select for aa64_va_parameters_both
      target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
      target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
      target/arm: Vectorize USHL and SSHL
      target/arm: Convert PMUL.8 to gvec
      target/arm: Convert PMULL.64 to gvec
      target/arm: Convert PMULL.8 to gvec
      target/arm: Rename isar_feature_aa32_simd_r32
      target/arm: Use isar_feature_aa32_simd_r32 more places
      target/arm: Set MVFR0.FPSP for ARMv5 cpus

 hw/usb/hcd-ohci.h              |  16 ++
 include/hw/arm/allwinner-a10.h |   6 +
 target/arm/cpu.h               | 145 ++++++++++---
 target/arm/helper-sve.h        |   2 +
 target/arm/helper.h            |  21 +-
 target/arm/internals.h         |  47 ++++-
 target/arm/translate.h         |   6 +
 hw/arm/allwinner-a10.c         |  43 ++++
 hw/arm/mainstone.c             |  11 +-
 hw/arm/z2.c                    |   6 -
 hw/intc/armv7m_nvic.c          |  10 +-
 hw/misc/aspeed_scu.c           |  93 ++++++--
 hw/misc/iotkit-secctl.c        |   2 +-
 hw/sh4/sh_pci.c                |  11 +-
 hw/ssi/xilinx_spips.c          |   2 +-
 hw/usb/hcd-ehci-sysbus.c       |   2 +
 hw/usb/hcd-ohci.c              |  15 --
 linux-user/elfload.c           |   4 +-
 target/arm/cpu.c               | 169 +++++++--------
 target/arm/cpu64.c             |  58 +++--
 target/arm/debug_helper.c      |   6 +-
 target/arm/helper.c            | 468 +++++++++++++++++++++++------------------
 target/arm/kvm32.c             |  25 +++
 target/arm/kvm64.c             |  46 ++++
 target/arm/neon_helper.c       | 117 -----------
 target/arm/pauth_helper.c      |   3 +-
 target/arm/translate-a64.c     |  92 ++++----
 target/arm/translate-vfp.inc.c |  53 ++---
 target/arm/translate.c         | 356 ++++++++++++++++++++++++++-----
 target/arm/vec_helper.c        | 211 +++++++++++++++++++
 target/arm/vfp_helper.c        |   2 +-
 31 files changed, 1377 insertions(+), 671 deletions(-)


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PULL v2 00/46] target-arm queue
  2020-02-21 16:18 [PULL v2 00/46] target-arm queue Peter Maydell
@ 2020-02-21 17:00 ` Peter Maydell
  0 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2020-02-21 17:00 UTC (permalink / raw)
  To: QEMU Developers

On Fri, 21 Feb 2020 at 16:18, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> v1->v2 changes: dropped the last 6 patches from rth as there's
> a problem with one of them that's too complicated to try to
> fix up.
>
> thanks
> -- PMM
>
> The following changes since commit a8c6af67e1e8d460e2c6e87070807e0a02c0fec2:
>
>   Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' into staging (2020-02-21 14:20:42 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221-1
>
> for you to fetch changes up to 9eb4f58918a851fb46895fd9b7ce579afeac9d02:
>
>   target/arm: Set MVFR0.FPSP for ARMv5 cpus (2020-02-21 16:07:03 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * aspeed/scu: Implement chip ID register
>  * hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
>  * mainstone: Make providing flash images non-mandatory
>  * z2: Make providing flash images non-mandatory
>  * Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT
>  * Minor performance improvement: spend less time recalculating hflags values
>  * Code cleanup to isar_feature function tests
>  * Implement ARMv8.1-PMU and ARMv8.4-PMU extensions
>  * Bugfix: correct handling of PMCR_EL0.LC bit
>  * Bugfix: correct definition of PMCRDP
>  * Correctly implement ACTLR2, HACTLR2
>  * allwinner: Wire up USB ports
>  * Vectorize emulation of USHL, SSHL, PMUL*
>  * xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
>  * sh4: Fix PCI ISA IO memory subregion
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PULL v2 00/46] target-arm queue
  2021-01-29 16:08 Peter Maydell
@ 2021-01-29 19:42 ` Peter Maydell
  0 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2021-01-29 19:42 UTC (permalink / raw)
  To: QEMU Developers

On Fri, 29 Jan 2021 at 16:08, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> v2 update: fix memory leaks in pvpanic-pci test case spotted by
> oss-fuzz gitlab CI run.
>
> -- PMM
>
> The following changes since commit 7e7eb9f852a46b51a71ae9d82590b2e4d28827ee:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-01-28' into staging (2021-01-28 22:43:18 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210129-1
>
> for you to fetch changes up to 14711b6f54708b9583796db02b12ee7bd0331502:
>
>   hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS (2021-01-29 15:54:44 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Implement ID_PFR2
>  * Conditionalize DBGDIDR
>  * rename xlnx-zcu102.canbusN properties
>  * provide powerdown/reset mechanism for secure firmware on 'virt' board
>  * hw/misc: Fix arith overflow in NPCM7XX PWM module
>  * target/arm: Replace magic value by MMU_DATA_LOAD definition
>  * configure: fix preadv errors on Catalina macOS with new XCode
>  * Various configure and other cleanups in preparation for iOS support
>  * hvf: Add hypervisor entitlement to output binaries (needed for Big Sur)
>  * Implement pvpanic-pci device
>  * Convert the CMSDK timer devices to the Clock framework
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PULL v2 00/46] target-arm queue
@ 2021-01-29 16:08 Peter Maydell
  2021-01-29 19:42 ` Peter Maydell
  0 siblings, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2021-01-29 16:08 UTC (permalink / raw)
  To: qemu-devel

v2 update: fix memory leaks in pvpanic-pci test case spotted by
oss-fuzz gitlab CI run.

-- PMM

The following changes since commit 7e7eb9f852a46b51a71ae9d82590b2e4d28827ee:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-01-28' into staging (2021-01-28 22:43:18 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210129-1

for you to fetch changes up to 14711b6f54708b9583796db02b12ee7bd0331502:

  hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS (2021-01-29 15:54:44 +0000)

----------------------------------------------------------------
target-arm queue:
 * Implement ID_PFR2
 * Conditionalize DBGDIDR
 * rename xlnx-zcu102.canbusN properties
 * provide powerdown/reset mechanism for secure firmware on 'virt' board
 * hw/misc: Fix arith overflow in NPCM7XX PWM module
 * target/arm: Replace magic value by MMU_DATA_LOAD definition
 * configure: fix preadv errors on Catalina macOS with new XCode
 * Various configure and other cleanups in preparation for iOS support
 * hvf: Add hypervisor entitlement to output binaries (needed for Big Sur)
 * Implement pvpanic-pci device
 * Convert the CMSDK timer devices to the Clock framework

----------------------------------------------------------------
Alexander Graf (1):
      hvf: Add hypervisor entitlement to output binaries

Hao Wu (1):
      hw/misc: Fix arith overflow in NPCM7XX PWM module

Joelle van Dyne (7):
      configure: cross-compiling with empty cross_prefix
      osdep: build with non-working system() function
      darwin: remove redundant dependency declaration
      darwin: fix cross-compiling for Darwin
      configure: cross compile should use x86_64 cpu_family
      darwin: detect CoreAudio for build
      darwin: remove 64-bit build detection on 32-bit OS

Maxim Uvarov (3):
      hw: gpio: implement gpio-pwr driver for qemu reset/poweroff
      arm-virt: refactor gpios creation
      arm-virt: add secure pl061 for reset/power down

Mihai Carabas (4):
      hw/misc/pvpanic: split-out generic and bus dependent code
      hw/misc/pvpanic: add PCI interface support
      pvpanic : update pvpanic spec document
      tests/qtest: add a test case for pvpanic-pci

Paolo Bonzini (1):
      arm: rename xlnx-zcu102.canbusN properties

Peter Maydell (26):
      configure: Move preadv check to meson.build
      ptimer: Add new ptimer_set_period_from_clock() function
      clock: Add new clock_has_source() function
      tests: Add a simple test of the CMSDK APB timer
      tests: Add a simple test of the CMSDK APB watchdog
      tests: Add a simple test of the CMSDK APB dual timer
      hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
      hw/timer/cmsdk-apb-timer: Add Clock input
      hw/timer/cmsdk-apb-dualtimer: Add Clock input
      hw/watchdog/cmsdk-apb-watchdog: Add Clock input
      hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
      hw/arm/armsse: Wire up clocks
      hw/arm/mps2: Inline CMSDK_APB_TIMER creation
      hw/arm/mps2: Create and connect SYSCLK Clock
      hw/arm/mps2-tz: Create and connect ARMSSE Clocks
      hw/arm/musca: Create and connect ARMSSE Clocks
      hw/arm/stellaris: Convert SSYS to QOM device
      hw/arm/stellaris: Create Clock input for watchdog
      hw/timer/cmsdk-apb-timer: Convert to use Clock input
      hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
      hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
      tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
      hw/arm/armsse: Use Clock to set system_clock_scale
      arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
      arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
      hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS

Philippe Mathieu-Daudé (1):
      target/arm: Replace magic value by MMU_DATA_LOAD definition

Richard Henderson (2):
      target/arm: Implement ID_PFR2
      target/arm: Conditionalize DBGDIDR

 docs/devel/clocks.rst                    |  16 +++
 docs/specs/pci-ids.txt                   |   1 +
 docs/specs/pvpanic.txt                   |  13 ++-
 docs/system/arm/virt.rst                 |   2 +
 configure                                |  78 ++++++++------
 meson.build                              |  34 ++++++-
 include/hw/arm/armsse.h                  |  14 ++-
 include/hw/arm/virt.h                    |   2 +
 include/hw/clock.h                       |  15 +++
 include/hw/misc/pvpanic.h                |  24 ++++-
 include/hw/pci/pci.h                     |   1 +
 include/hw/ptimer.h                      |  22 ++++
 include/hw/timer/cmsdk-apb-dualtimer.h   |   5 +-
 include/hw/timer/cmsdk-apb-timer.h       |  34 ++-----
 include/hw/watchdog/cmsdk-apb-watchdog.h |   5 +-
 include/qemu/osdep.h                     |  12 +++
 include/qemu/typedefs.h                  |   1 +
 target/arm/cpu.h                         |   1 +
 hw/arm/armsse.c                          |  48 ++++++---
 hw/arm/mps2-tz.c                         |  14 ++-
 hw/arm/mps2.c                            |  28 ++++-
 hw/arm/musca.c                           |  13 ++-
 hw/arm/stellaris.c                       | 170 +++++++++++++++++++++++--------
 hw/arm/virt.c                            | 111 ++++++++++++++++----
 hw/arm/xlnx-zcu102.c                     |   4 +-
 hw/core/ptimer.c                         |  34 +++++++
 hw/gpio/gpio_pwr.c                       |  70 +++++++++++++
 hw/misc/npcm7xx_pwm.c                    |  23 ++++-
 hw/misc/pvpanic-isa.c                    |  94 +++++++++++++++++
 hw/misc/pvpanic-pci.c                    |  94 +++++++++++++++++
 hw/misc/pvpanic.c                        |  85 ++--------------
 hw/timer/cmsdk-apb-dualtimer.c           |  53 +++++++---
 hw/timer/cmsdk-apb-timer.c               |  55 +++++-----
 hw/watchdog/cmsdk-apb-watchdog.c         |  29 ++++--
 target/arm/helper.c                      |  27 +++--
 target/arm/kvm64.c                       |   2 +
 tests/qtest/cmsdk-apb-dualtimer-test.c   | 130 +++++++++++++++++++++++
 tests/qtest/cmsdk-apb-timer-test.c       |  75 ++++++++++++++
 tests/qtest/cmsdk-apb-watchdog-test.c    | 131 ++++++++++++++++++++++++
 tests/qtest/npcm7xx_pwm-test.c           |   4 +-
 tests/qtest/pvpanic-pci-test.c           |  98 ++++++++++++++++++
 tests/qtest/xlnx-can-test.c              |  30 +++---
 MAINTAINERS                              |   3 +
 accel/hvf/entitlements.plist             |   8 ++
 hw/arm/Kconfig                           |   1 +
 hw/gpio/Kconfig                          |   3 +
 hw/gpio/meson.build                      |   1 +
 hw/i386/Kconfig                          |   2 +-
 hw/misc/Kconfig                          |  12 ++-
 hw/misc/meson.build                      |   4 +-
 scripts/entitlement.sh                   |  13 +++
 tests/qtest/meson.build                  |   6 +-
 52 files changed, 1436 insertions(+), 319 deletions(-)
 create mode 100644 hw/gpio/gpio_pwr.c
 create mode 100644 hw/misc/pvpanic-isa.c
 create mode 100644 hw/misc/pvpanic-pci.c
 create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
 create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
 create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
 create mode 100644 tests/qtest/pvpanic-pci-test.c
 create mode 100644 accel/hvf/entitlements.plist
 create mode 100755 scripts/entitlement.sh


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-01-29 19:44 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-21 16:18 [PULL v2 00/46] target-arm queue Peter Maydell
2020-02-21 17:00 ` Peter Maydell
2021-01-29 16:08 Peter Maydell
2021-01-29 19:42 ` Peter Maydell

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