* [PATCH v3 0/2] qemu-cpu-models: Convert to rST; document other MSR bits
@ 2020-02-20 14:19 Kashyap Chamarthy
2020-02-20 14:20 ` [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST Kashyap Chamarthy
2020-02-20 14:20 ` [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl Kashyap Chamarthy
0 siblings, 2 replies; 11+ messages in thread
From: Kashyap Chamarthy @ 2020-02-20 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, berrange, Eduardo Habkost, kchamart,
Paolo Bonzini, Richard Henderson
In v3:
- Address the comments from Peter Maydell, from here:
https://lists.nongnu.org/archive/html/qemu-devel/2020-02/msg05155.html
This small series does two things:
(1) Convert the original qemu-cpu-models.texi to rST
(2) In a separate patch, incorporate the additional new content from
this:
https://lists.nongnu.org/archive/html/qemu-devel/2020-01/msg06455.html
([PATCH v3] qemu-cpu-models: Document -noTSX, mds-no, taa-no, and
tsx-ctrl)
Sphinx rendering of the converted doc is here:
https://kashyapc.fedorapeople.org/QEMU_v4.2.0-1301-gb082353c5e_docs/system/qemu-cpu-models.html
Kashyap Chamarthy (2):
docs: Convert qemu-cpu-models.texi to rST
qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl
MAINTAINERS | 2 +-
Makefile | 10 +-
docs/qemu-cpu-models.texi | 677 --------------------------------
docs/system/conf.py | 3 +
docs/system/index.rst | 1 +
docs/system/qemu-cpu-models.rst | 571 +++++++++++++++++++++++++++
qemu-doc.texi | 5 -
7 files changed, 581 insertions(+), 688 deletions(-)
delete mode 100644 docs/qemu-cpu-models.texi
create mode 100644 docs/system/qemu-cpu-models.rst
--
2.21.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST 2020-02-20 14:19 [PATCH v3 0/2] qemu-cpu-models: Convert to rST; document other MSR bits Kashyap Chamarthy @ 2020-02-20 14:20 ` Kashyap Chamarthy 2020-02-21 15:16 ` Peter Maydell 2020-02-20 14:20 ` [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl Kashyap Chamarthy 1 sibling, 1 reply; 11+ messages in thread From: Kashyap Chamarthy @ 2020-02-20 14:20 UTC (permalink / raw) To: qemu-devel Cc: peter.maydell, berrange, Eduardo Habkost, kchamart, Paolo Bonzini, Richard Henderson This doc was originally written by Daniel P. Berrangé <berrange@redhat.com>, introduced via commit[1]: 2544e9e4aa (docs: add guidance on configuring CPU models for x86, 2018-06-27). In this patch: - 1-1 conversion of Texinfo to rST, besides a couple of minor tweaks that are too trivial to mention. (Thanks to Stephen Finucane on IRC for the suggestion to use rST "definition lists" instead of bullets in some places.) Further modifications will be done via a separate patch. - rST and related infra changes: for building the manual page, Makefile fixes, clean up references to qemu-cpu-models.texi, etc. [1] https://git.qemu.org/?p=qemu.git;a=commit;h=2544e9e4aa Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> --- v2: Fix rST conversion, man page creation, Makefile changes, et al (thanks, Peter Maydell) --- MAINTAINERS | 2 +- Makefile | 10 +- docs/qemu-cpu-models.texi | 677 -------------------------------- docs/system/conf.py | 3 + docs/system/index.rst | 1 + docs/system/qemu-cpu-models.rst | 514 ++++++++++++++++++++++++ qemu-doc.texi | 5 - 7 files changed, 524 insertions(+), 688 deletions(-) delete mode 100644 docs/qemu-cpu-models.texi create mode 100644 docs/system/qemu-cpu-models.rst diff --git a/MAINTAINERS b/MAINTAINERS index e72b5e5f69..38bb821034 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -319,7 +319,7 @@ F: tests/tcg/i386/ F: tests/tcg/x86_64/ F: hw/i386/ F: disas/i386.c -F: docs/qemu-cpu-models.texi +F: docs/system/qemu-cpu-models.rst T: git https://github.com/ehabkost/qemu.git x86-next Xtensa TCG CPUs diff --git a/Makefile b/Makefile index 461d40bea6..5377a30d88 100644 --- a/Makefile +++ b/Makefile @@ -349,9 +349,9 @@ DOCS+=$(MANUAL_BUILDDIR)/interop/qemu-img.1 DOCS+=$(MANUAL_BUILDDIR)/interop/qemu-nbd.8 DOCS+=$(MANUAL_BUILDDIR)/interop/qemu-ga.8 DOCS+=$(MANUAL_BUILDDIR)/system/qemu-block-drivers.7 +DOCS+=$(MANUAL_BUILDDIR)/system/qemu-cpu-models.7 DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt docs/interop/qemu-qmp-ref.7 DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7 -DOCS+=docs/qemu-cpu-models.7 DOCS+=$(MANUAL_BUILDDIR)/index.html ifdef CONFIG_VIRTFS DOCS+=$(MANUAL_BUILDDIR)/interop/virtfs-proxy-helper.1 @@ -764,7 +764,6 @@ distclean: clean rm -f docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt rm -f docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf rm -f docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html - rm -f docs/qemu-cpu-models.7 rm -rf .doctrees $(call clean-manual,devel) $(call clean-manual,interop) @@ -841,7 +840,7 @@ ifdef CONFIG_POSIX $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man7" $(INSTALL_DATA) docs/interop/qemu-qmp-ref.7 "$(DESTDIR)$(mandir)/man7" $(INSTALL_DATA) $(MANUAL_BUILDDIR)/system/qemu-block-drivers.7 "$(DESTDIR)$(mandir)/man7" - $(INSTALL_DATA) docs/qemu-cpu-models.7 "$(DESTDIR)$(mandir)/man7" + $(INSTALL_DATA) $(MANUAL_BUILDDIR)/system/qemu-cpu-models.7 "$(DESTDIR)$(mandir)/man7" ifeq ($(CONFIG_TOOLS),y) $(INSTALL_DATA) $(MANUAL_BUILDDIR)/interop/qemu-img.1 "$(DESTDIR)$(mandir)/man1" $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man8" @@ -1056,6 +1055,8 @@ $(call define-manpage-rule,interop,\ $(call define-manpage-rule,system,qemu-block-drivers.7) +$(call define-manpage-rule,system,qemu-cpu-models.7) + $(MANUAL_BUILDDIR)/index.html: $(SRC_PATH)/docs/index.html.in qemu-version.h @mkdir -p "$(MANUAL_BUILDDIR)" $(call quiet-command, sed "s|@@VERSION@@|${VERSION}|g" $< >$@, \ @@ -1078,7 +1079,6 @@ docs/interop/qemu-ga-qapi.texi: qga/qapi-generated/qga-qapi-doc.texi qemu.1: qemu-doc.texi qemu-options.texi qemu-monitor.texi qemu-monitor-info.texi qemu.1: qemu-option-trace.texi -docs/qemu-cpu-models.7: docs/qemu-cpu-models.texi html: qemu-doc.html docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html sphinxdocs info: qemu-doc.info docs/interop/qemu-qmp-ref.info docs/interop/qemu-ga-ref.info @@ -1090,7 +1090,7 @@ qemu-doc.html qemu-doc.info qemu-doc.pdf qemu-doc.txt: \ qemu-tech.texi qemu-option-trace.texi \ qemu-deprecated.texi qemu-monitor.texi \ qemu-monitor-info.texi \ - docs/qemu-cpu-models.texi docs/security.texi + docs/security.texi docs/interop/qemu-ga-ref.dvi docs/interop/qemu-ga-ref.html \ docs/interop/qemu-ga-ref.info docs/interop/qemu-ga-ref.pdf \ diff --git a/docs/qemu-cpu-models.texi b/docs/qemu-cpu-models.texi deleted file mode 100644 index f88a1def0d..0000000000 --- a/docs/qemu-cpu-models.texi +++ /dev/null @@ -1,677 +0,0 @@ -@c man begin SYNOPSIS -QEMU / KVM CPU model configuration -@c man end - -@set qemu_system_x86 qemu-system-x86_64 - -@c man begin DESCRIPTION - -@menu -* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts -* recommendations_cpu_models_MIPS:: Supported CPU model configurations on MIPS hosts -* cpu_model_syntax_apps:: Syntax for configuring CPU models -@end menu - -QEMU / KVM virtualization supports two ways to configure CPU models - -@table @option - -@item Host passthrough - -This passes the host CPU model features, model, stepping, exactly to the -guest. Note that KVM may filter out some host CPU model features if they -cannot be supported with virtualization. Live migration is unsafe when -this mode is used as libvirt / QEMU cannot guarantee a stable CPU is -exposed to the guest across hosts. This is the recommended CPU to use, -provided live migration is not required. - -@item Named model - -QEMU comes with a number of predefined named CPU models, that typically -refer to specific generations of hardware released by Intel and AMD. -These allow the guest VMs to have a degree of isolation from the host CPU, -allowing greater flexibility in live migrating between hosts with differing -hardware. -@end table - -In both cases, it is possible to optionally add or remove individual CPU -features, to alter what is presented to the guest by default. - -Libvirt supports a third way to configure CPU models known as "Host model". -This uses the QEMU "Named model" feature, automatically picking a CPU model -that is similar the host CPU, and then adding extra features to approximate -the host model as closely as possible. This does not guarantee the CPU family, -stepping, etc will precisely match the host CPU, as they would with "Host -passthrough", but gives much of the benefit of passthrough, while making -live migration safe. - -@node recommendations_cpu_models_x86 -@subsection Recommendations for KVM CPU model configuration on x86 hosts - -The information that follows provides recommendations for configuring -CPU models on x86 hosts. The goals are to maximise performance, while -protecting guest OS against various CPU hardware flaws, and optionally -enabling live migration between hosts with heterogeneous CPU models. - -@menu -* preferred_cpu_models_intel_x86:: Preferred CPU models for Intel x86 hosts -* important_cpu_features_intel_x86:: Important CPU features for Intel x86 hosts -* preferred_cpu_models_amd_x86:: Preferred CPU models for AMD x86 hosts -* important_cpu_features_amd_x86:: Important CPU features for AMD x86 hosts -* default_cpu_models_x86:: Default x86 CPU models -* other_non_recommended_cpu_models_x86:: Other non-recommended x86 CPUs -@end menu - -@node preferred_cpu_models_intel_x86 -@subsubsection Preferred CPU models for Intel x86 hosts - -The following CPU models are preferred for use on Intel hosts. Administrators / -applications are recommended to use the CPU model that matches the generation -of the host CPUs in use. In a deployment with a mixture of host CPU models -between machines, if live migration compatibility is required, use the newest -CPU model that is compatible across all desired hosts. - -@table @option -@item @code{Skylake-Server} -@item @code{Skylake-Server-IBRS} - -Intel Xeon Processor (Skylake, 2016) - - -@item @code{Skylake-Client} -@item @code{Skylake-Client-IBRS} - -Intel Core Processor (Skylake, 2015) - - -@item @code{Broadwell} -@item @code{Broadwell-IBRS} -@item @code{Broadwell-noTSX} -@item @code{Broadwell-noTSX-IBRS} - -Intel Core Processor (Broadwell, 2014) - - -@item @code{Haswell} -@item @code{Haswell-IBRS} -@item @code{Haswell-noTSX} -@item @code{Haswell-noTSX-IBRS} - -Intel Core Processor (Haswell, 2013) - - -@item @code{IvyBridge} -@item @code{IvyBridge-IBRS} - -Intel Xeon E3-12xx v2 (Ivy Bridge, 2012) - - -@item @code{SandyBridge} -@item @code{SandyBridge-IBRS} - -Intel Xeon E312xx (Sandy Bridge, 2011) - - -@item @code{Westmere} -@item @code{Westmere-IBRS} - -Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010) - - -@item @code{Nehalem} -@item @code{Nehalem-IBRS} - -Intel Core i7 9xx (Nehalem Class Core i7, 2008) - - -@item @code{Penryn} - -Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007) - - -@item @code{Conroe} - -Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006) - -@end table - -@node important_cpu_features_intel_x86 -@subsubsection Important CPU features for Intel x86 hosts - -The following are important CPU features that should be used on Intel x86 -hosts, when available in the host CPU. Some of them require explicit -configuration to enable, as they are not included by default in some, or all, -of the named CPU models listed above. In general all of these features are -included if using "Host passthrough" or "Host model". - - -@table @option - -@item @code{pcid} - -Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix - -Included by default in Haswell, Broadwell & Skylake Intel CPU models. - -Should be explicitly turned on for Westmere, SandyBridge, and IvyBridge -Intel CPU models. Note that some desktop/mobile Westmere CPUs cannot -support this feature. - - -@item @code{spec-ctrl} - -Required to enable the Spectre v2 (CVE-2017-5715) fix. - -Included by default in Intel CPU models with -IBRS suffix. - -Must be explicitly turned on for Intel CPU models without -IBRS suffix. - -Requires the host CPU microcode to support this feature before it -can be used for guest CPUs. - - -@item @code{stibp} - -Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some -operating systems. - -Must be explicitly turned on for all Intel CPU models. - -Requires the host CPU microcode to support this feature before it -can be used for guest CPUs. - - -@item @code{ssbd} - -Required to enable the CVE-2018-3639 fix - -Not included by default in any Intel CPU model. - -Must be explicitly turned on for all Intel CPU models. - -Requires the host CPU microcode to support this feature before it -can be used for guest CPUs. - - -@item @code{pdpe1gb} - -Recommended to allow guest OS to use 1GB size pages - -Not included by default in any Intel CPU model. - -Should be explicitly turned on for all Intel CPU models. - -Note that not all CPU hardware will support this feature. - -@item @code{md-clear} - -Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, -CVE-2019-11091) fixes. - -Not included by default in any Intel CPU model. - -Must be explicitly turned on for all Intel CPU models. - -Requires the host CPU microcode to support this feature before it -can be used for guest CPUs. -@end table - - -@node preferred_cpu_models_amd_x86 -@subsubsection Preferred CPU models for AMD x86 hosts - -The following CPU models are preferred for use on Intel hosts. Administrators / -applications are recommended to use the CPU model that matches the generation -of the host CPUs in use. In a deployment with a mixture of host CPU models -between machines, if live migration compatibility is required, use the newest -CPU model that is compatible across all desired hosts. - -@table @option - -@item @code{EPYC} -@item @code{EPYC-IBPB} - -AMD EPYC Processor (2017) - - -@item @code{Opteron_G5} - -AMD Opteron 63xx class CPU (2012) - - -@item @code{Opteron_G4} - -AMD Opteron 62xx class CPU (2011) - - -@item @code{Opteron_G3} - -AMD Opteron 23xx (Gen 3 Class Opteron, 2009) - - -@item @code{Opteron_G2} - -AMD Opteron 22xx (Gen 2 Class Opteron, 2006) - - -@item @code{Opteron_G1} - -AMD Opteron 240 (Gen 1 Class Opteron, 2004) -@end table - -@node important_cpu_features_amd_x86 -@subsubsection Important CPU features for AMD x86 hosts - -The following are important CPU features that should be used on AMD x86 -hosts, when available in the host CPU. Some of them require explicit -configuration to enable, as they are not included by default in some, or all, -of the named CPU models listed above. In general all of these features are -included if using "Host passthrough" or "Host model". - - -@table @option - -@item @code{ibpb} - -Required to enable the Spectre v2 (CVE-2017-5715) fix. - -Included by default in AMD CPU models with -IBPB suffix. - -Must be explicitly turned on for AMD CPU models without -IBPB suffix. - -Requires the host CPU microcode to support this feature before it -can be used for guest CPUs. - - -@item @code{stibp} - -Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some -operating systems. - -Must be explicitly turned on for all AMD CPU models. - -Requires the host CPU microcode to support this feature before it -can be used for guest CPUs. - - -@item @code{virt-ssbd} - -Required to enable the CVE-2018-3639 fix - -Not included by default in any AMD CPU model. - -Must be explicitly turned on for all AMD CPU models. - -This should be provided to guests, even if amd-ssbd is also -provided, for maximum guest compatibility. - -Note for some QEMU / libvirt versions, this must be force enabled -when when using "Host model", because this is a virtual feature -that doesn't exist in the physical host CPUs. - - -@item @code{amd-ssbd} - -Required to enable the CVE-2018-3639 fix - -Not included by default in any AMD CPU model. - -Must be explicitly turned on for all AMD CPU models. - -This provides higher performance than virt-ssbd so should be -exposed to guests whenever available in the host. virt-ssbd -should none the less also be exposed for maximum guest -compatibility as some kernels only know about virt-ssbd. - - -@item @code{amd-no-ssb} - -Recommended to indicate the host is not vulnerable CVE-2018-3639 - -Not included by default in any AMD CPU model. - -Future hardware generations of CPU will not be vulnerable to -CVE-2018-3639, and thus the guest should be told not to enable -its mitigations, by exposing amd-no-ssb. This is mutually -exclusive with virt-ssbd and amd-ssbd. - - -@item @code{pdpe1gb} - -Recommended to allow guest OS to use 1GB size pages - -Not included by default in any AMD CPU model. - -Should be explicitly turned on for all AMD CPU models. - -Note that not all CPU hardware will support this feature. -@end table - - -@node default_cpu_models_x86 -@subsubsection Default x86 CPU models - -The default QEMU CPU models are designed such that they can run on all hosts. -If an application does not wish to do perform any host compatibility checks -before launching guests, the default is guaranteed to work. - -The default CPU models will, however, leave the guest OS vulnerable to various -CPU hardware flaws, so their use is strongly discouraged. Applications should -follow the earlier guidance to setup a better CPU configuration, with host -passthrough recommended if live migration is not needed. - -@table @option -@item @code{qemu32} -@item @code{qemu64} - -QEMU Virtual CPU version 2.5+ (32 & 64 bit variants) - -qemu64 is used for x86_64 guests and qemu32 is used for i686 guests, when no --cpu argument is given to QEMU, or no <cpu> is provided in libvirt XML. -@end table - - -@node other_non_recommended_cpu_models_x86 -@subsubsection Other non-recommended x86 CPUs - -The following CPUs models are compatible with most AMD and Intel x86 hosts, but -their usage is discouraged, as they expose a very limited featureset, which -prevents guests having optimal performance. - -@table @option - -@item @code{kvm32} -@item @code{kvm64} - -Common KVM processor (32 & 64 bit variants) - -Legacy models just for historical compatibility with ancient QEMU versions. - - -@item @code{486} -@item @code{athlon} -@item @code{phenom} -@item @code{coreduo} -@item @code{core2duo} -@item @code{n270} -@item @code{pentium} -@item @code{pentium2} -@item @code{pentium3} - -Various very old x86 CPU models, mostly predating the introduction of -hardware assisted virtualization, that should thus not be required for -running virtual machines. -@end table - -@node recommendations_cpu_models_MIPS -@subsection Supported CPU model configurations on MIPS hosts - -QEMU supports variety of MIPS CPU models: - -@menu -* cpu_models_MIPS32:: Supported CPU models for MIPS32 hosts -* cpu_models_MIPS64:: Supported CPU models for MIPS64 hosts -* cpu_models_nanoMIPS:: Supported CPU models for nanoMIPS hosts -* preferred_cpu_models_MIPS:: Preferred CPU models for MIPS hosts -@end menu - -@node cpu_models_MIPS32 -@subsubsection Supported CPU models for MIPS32 hosts - -The following CPU models are supported for use on MIPS32 hosts. Administrators / -applications are recommended to use the CPU model that matches the generation -of the host CPUs in use. In a deployment with a mixture of host CPU models -between machines, if live migration compatibility is required, use the newest -CPU model that is compatible across all desired hosts. - -@table @option -@item @code{mips32r6-generic} - -MIPS32 Processor (Release 6, 2015) - - -@item @code{P5600} - -MIPS32 Processor (P5600, 2014) - - -@item @code{M14K} -@item @code{M14Kc} - -MIPS32 Processor (M14K, 2009) - - -@item @code{74Kf} - -MIPS32 Processor (74K, 2007) - - -@item @code{34Kf} - -MIPS32 Processor (34K, 2006) - - -@item @code{24Kc} -@item @code{24KEc} -@item @code{24Kf} - -MIPS32 Processor (24K, 2003) - - -@item @code{4Kc} -@item @code{4Km} -@item @code{4KEcR1} -@item @code{4KEmR1} -@item @code{4KEc} -@item @code{4KEm} - -MIPS32 Processor (4K, 1999) -@end table - -@node cpu_models_MIPS64 -@subsubsection Supported CPU models for MIPS64 hosts - -The following CPU models are supported for use on MIPS64 hosts. Administrators / -applications are recommended to use the CPU model that matches the generation -of the host CPUs in use. In a deployment with a mixture of host CPU models -between machines, if live migration compatibility is required, use the newest -CPU model that is compatible across all desired hosts. - -@table @option -@item @code{I6400} - -MIPS64 Processor (Release 6, 2014) - - -@item @code{Loongson-2F} - -MIPS64 Processor (Loongson 2, 2008) - - -@item @code{Loongson-2E} - -MIPS64 Processor (Loongson 2, 2006) - - -@item @code{mips64dspr2} - -MIPS64 Processor (Release 2, 2006) - - -@item @code{MIPS64R2-generic} -@item @code{5KEc} -@item @code{5KEf} - -MIPS64 Processor (Release 2, 2002) - - -@item @code{20Kc} - -MIPS64 Processor (20K, 2000) - - -@item @code{5Kc} -@item @code{5Kf} - -MIPS64 Processor (5K, 1999) - - -@item @code{VR5432} - -MIPS64 Processor (VR, 1998) - - -@item @code{R4000} - -MIPS64 Processor (MIPS III, 1991) -@end table - -@node cpu_models_nanoMIPS -@subsubsection Supported CPU models for nanoMIPS hosts - -The following CPU models are supported for use on nanoMIPS hosts. Administrators / -applications are recommended to use the CPU model that matches the generation -of the host CPUs in use. In a deployment with a mixture of host CPU models -between machines, if live migration compatibility is required, use the newest -CPU model that is compatible across all desired hosts. - -@table @option -@item @code{I7200} - -MIPS I7200 (nanoMIPS, 2018) - -@end table - -@node preferred_cpu_models_MIPS -@subsubsection Preferred CPU models for MIPS hosts - -The following CPU models are preferred for use on different MIPS hosts: - -@table @option -@item @code{MIPS III} -R4000 - -@item @code{MIPS32R2} -34Kf - -@item @code{MIPS64R6} -I6400 - -@item @code{nanoMIPS} -I7200 -@end table - -@node cpu_model_syntax_apps -@subsection Syntax for configuring CPU models - -The example below illustrate the approach to configuring the various -CPU models / features in QEMU and libvirt - -@menu -* cpu_model_syntax_qemu:: QEMU command line -* cpu_model_syntax_libvirt:: Libvirt guest XML -@end menu - -@node cpu_model_syntax_qemu -@subsubsection QEMU command line - -@table @option - -@item Host passthrough - -@example - $ @value{qemu_system_x86} -cpu host -@end example - -With feature customization: - -@example - $ @value{qemu_system_x86} -cpu host,-vmx,... -@end example - -@item Named CPU models - -@example - $ @value{qemu_system_x86} -cpu Westmere -@end example - -With feature customization: - -@example - $ @value{qemu_system_x86} -cpu Westmere,+pcid,... -@end example - -@end table - -@node cpu_model_syntax_libvirt -@subsubsection Libvirt guest XML - -@table @option - -@item Host passthrough - -@example - <cpu mode='host-passthrough'/> -@end example - -With feature customization: - -@example - <cpu mode='host-passthrough'> - <feature name="vmx" policy="disable"/> - ... - </cpu> -@end example - -@item Host model - -@example - <cpu mode='host-model'/> -@end example - -With feature customization: - -@example - <cpu mode='host-model'> - <feature name="vmx" policy="disable"/> - ... - </cpu> -@end example - -@item Named model - -@example - <cpu mode='custom'> - <model name="Westmere"/> - </cpu> -@end example - -With feature customization: - -@example - <cpu mode='custom'> - <model name="Westmere"/> - <feature name="pcid" policy="require"/> - ... - </cpu> -@end example - -@end table - -@c man end - -@ignore - -@setfilename qemu-cpu-models -@settitle QEMU / KVM CPU model configuration - -@c man begin SEEALSO -The HTML documentation of QEMU for more precise information and Linux -user mode emulator invocation. -@c man end - -@c man begin AUTHOR -Daniel P. Berrange -@c man end - -@end ignore diff --git a/docs/system/conf.py b/docs/system/conf.py index 7ca115f5e0..7cc9da9508 100644 --- a/docs/system/conf.py +++ b/docs/system/conf.py @@ -18,5 +18,8 @@ html_theme_options['description'] = u'System Emulation User''s Guide' man_pages = [ ('qemu-block-drivers', 'qemu-block-drivers', u'QEMU block drivers reference', + ['Fabrice Bellard and the QEMU Project developers'], 7), + ('qemu-cpu-models', 'qemu-cpu-models', + u'QEMU CPU Models', ['Fabrice Bellard and the QEMU Project developers'], 7) ] diff --git a/docs/system/index.rst b/docs/system/index.rst index f66e6ea585..849dcd8cb8 100644 --- a/docs/system/index.rst +++ b/docs/system/index.rst @@ -15,3 +15,4 @@ Contents: :maxdepth: 2 qemu-block-drivers + qemu-cpu-models diff --git a/docs/system/qemu-cpu-models.rst b/docs/system/qemu-cpu-models.rst new file mode 100644 index 0000000000..a189d6a9da --- /dev/null +++ b/docs/system/qemu-cpu-models.rst @@ -0,0 +1,514 @@ +QEMU / KVM CPU model configuration +================================== + +.. |qemu_system| replace:: qemu-system-x86_64 + +.. only:: man + + Synopsis + -------- + + QEMU CPU Modelling Infrastructure manual + +Two ways to configure CPU models with QEMU / KVM +------------------------------------------------ + +(1) **Host passthrough** + + This passes the host CPU model features, model, stepping, exactly to + the guest. Note that KVM may filter out some host CPU model features + if they cannot be supported with virtualization. Live migration is + unsafe when this mode is used as libvirt / QEMU cannot guarantee a + stable CPU is exposed to the guest across hosts. This is the + recommended CPU to use, provided live migration is not required. + +(2) **Named model** + + QEMU comes with a number of predefined named CPU models, that + typically refer to specific generations of hardware released by + Intel and AMD. These allow the guest VMs to have a degree of + isolation from the host CPU, allowing greater flexibility in live + migrating between hosts with differing hardware. @end table + +In both cases, it is possible to optionally add or remove individual CPU +features, to alter what is presented to the guest by default. + +Libvirt supports a third way to configure CPU models known as "Host +model". This uses the QEMU "Named model" feature, automatically picking +a CPU model that is similar the host CPU, and then adding extra features +to approximate the host model as closely as possible. This does not +guarantee the CPU family, stepping, etc will precisely match the host +CPU, as they would with "Host passthrough", but gives much of the +benefit of passthrough, while making live migration safe. + + +Recommendations for KVM CPU model configuration on x86 hosts +------------------------------------------------------------ + +The information that follows provides recommendations for configuring +CPU models on x86 hosts. The goals are to maximise performance, while +protecting guest OS against various CPU hardware flaws, and optionally +enabling live migration between hosts with heterogeneous CPU models. + + +Preferred CPU models for Intel x86 hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following CPU models are preferred for use on Intel hosts. +Administrators / applications are recommended to use the CPU model that +matches the generation of the host CPUs in use. In a deployment with a +mixture of host CPU models between machines, if live migration +compatibility is required, use the newest CPU model that is compatible +across all desired hosts. + +* Intel Xeon Processor (Skylake, 2016) + + * ``Skylake-Server`` + * ``Skylake-Server-IBRS`` + +* Intel Core Processor (Skylake, 2015) + + * ``Skylake-Client`` + * ``Skylake-Client-IBRS`` + +* Intel Core Processor (Broadwell, 2014) + + * ``Broadwell`` + * ``Broadwell-IBRS`` + * ``Broadwell-noTSX`` + * ``Broadwell-noTSX-IBRS`` + +* Intel Core Processor (Haswell, 2013) + + * ``Haswell`` + * ``Haswell-IBRS`` + * ``Haswell-noTSX`` + * ``Haswell-noTSX-IBRS`` + +* Intel Xeon E3-12xx v2 (Ivy Bridge, 2012) + + * ``IvyBridge`` + * ``IvyBridge-IBR`` + +* Intel Xeon E312xx (Sandy Bridge, 2011) + + * ``SandyBridge`` + * ``SandyBridge-IBRS`` + +* Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010) + + * ``Westmere`` + * ``Westmere-IBRS`` + +* Intel Core i7 9xx (Nehalem Class Core i7, 2008) + + * ``Nehalem`` + * ``Nehalem-IBRS`` + +* Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007) + + * ``Penryn`` + +* Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006) + + * ``Conroe`` + + +Important CPU features for Intel x86 hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following are important CPU features that should be used on Intel +x86 hosts, when available in the host CPU. Some of them require explicit +configuration to enable, as they are not included by default in some, or +all, of the named CPU models listed above. In general all of these +features are included if using "Host passthrough" or "Host model". + +``pcid`` + Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix. + + Included by default in Haswell, Broadwell & Skylake Intel CPU models. + + Should be explicitly turned on for Westmere, SandyBridge, and + IvyBridge Intel CPU models. Note that some desktop/mobile Westmere + CPUs cannot support this feature. + +``spec-ctrl`` + Required to enable the Spectre v2 (CVE-2017-5715) fix. + + Included by default in Intel CPU models with -IBRS suffix. + + Must be explicitly turned on for Intel CPU models without -IBRS + suffix. + + Requires the host CPU microcode to support this feature before it + can be used for guest CPUs. + +``stibp`` + Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some + operating systems. + + Must be explicitly turned on for all Intel CPU models. + + Requires the host CPU microcode to support this feature before it can + be used for guest CPUs. + +``ssbd`` + Required to enable the CVE-2018-3639 fix. + + Not included by default in any Intel CPU model. + + Must be explicitly turned on for all Intel CPU models. + + Requires the host CPU microcode to support this feature before it + can be used for guest CPUs. + +``pdpe1gb`` + Recommended to allow guest OS to use 1GB size pages. + + Not included by default in any Intel CPU model. + + Should be explicitly turned on for all Intel CPU models. + + Note that not all CPU hardware will support this feature. + +``md-clear`` + Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127, + CVE-2018-12130, CVE-2019-11091) fixes. + + Not included by default in any Intel CPU model. + + Must be explicitly turned on for all Intel CPU models. + + Requires the host CPU microcode to support this feature before it + can be used for guest CPUs. + + +Preferred CPU models for AMD x86 hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following CPU models are preferred for use on Intel hosts. +Administrators / applications are recommended to use the CPU model that +matches the generation of the host CPUs in use. In a deployment with a +mixture of host CPU models between machines, if live migration +compatibility is required, use the newest CPU model that is compatible +across all desired hosts. + +* AMD EPYC Processor (2017) + + * ``EPYC`` + * ``EPYC-IBPB`` + +* ``Opteron_G5`` – AMD Opteron 63xx class CPU (2012) + +* ``Opteron_G4`` – AMD Opteron 62xx class CPU (2011) + +* ``Opteron_G3`` – AMD Opteron 23xx (Gen 3 Class Opteron, 2009) + +* ``Opteron_G2`` – AMD Opteron 22xx (Gen 2 Class Opteron, 2006) + +* ``Opteron_G1`` – AMD Opteron 240 (Gen 1 Class Opteron, 2004) + + +Important CPU features for AMD x86 hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following are important CPU features that should be used on AMD x86 +hosts, when available in the host CPU. Some of them require explicit +configuration to enable, as they are not included by default in some, or +all, of the named CPU models listed above. In general all of these +features are included if using "Host passthrough" or "Host model". + +``ibpb`` + Required to enable the Spectre v2 (CVE-2017-5715) fix. + + Included by default in AMD CPU models with -IBPB suffix. + + Must be explicitly turned on for AMD CPU models without -IBPB suffix. + + Requires the host CPU microcode to support this feature before it + can be used for guest CPUs. + +``stibp`` + Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some + operating systems. + + Must be explicitly turned on for all AMD CPU models. + + Requires the host CPU microcode to support this feature before it + can be used for guest CPUs. + +``virt-ssbd`` + Required to enable the CVE-2018-3639 fix + + Not included by default in any AMD CPU model. + + Must be explicitly turned on for all AMD CPU models. + + This should be provided to guests, even if amd-ssbd is also provided, + for maximum guest compatibility. + + Note for some QEMU / libvirt versions, this must be force enabled when + when using "Host model", because this is a virtual feature that + doesn't exist in the physical host CPUs. + +``amd-ssbd`` + Required to enable the CVE-2018-3639 fix + + Not included by default in any AMD CPU model. + + Must be explicitly turned on for all AMD CPU models. + + This provides higher performance than ``virt-ssbd`` so should be + exposed to guests whenever available in the host. ``virt-ssbd`` should + none the less also be exposed for maximum guest compatibility as some + kernels only know about ``virt-ssbd``. + +``amd-no-ssb`` + Recommended to indicate the host is not vulnerable CVE-2018-3639 + + Not included by default in any AMD CPU model. + + Future hardware generations of CPU will not be vulnerable to + CVE-2018-3639, and thus the guest should be told not to enable + its mitigations, by exposing amd-no-ssb. This is mutually + exclusive with virt-ssbd and amd-ssbd. + +``pdpe1gb`` + Recommended to allow guest OS to use 1GB size pages + + Not included by default in any AMD CPU model. + + Should be explicitly turned on for all AMD CPU models. + + Note that not all CPU hardware will support this feature. + + +Default x86 CPU models +---------------------- + +The default QEMU CPU models are designed such that they can run on all +hosts. If an application does not wish to do perform any host +compatibility checks before launching guests, the default is guaranteed +to work. + +The default CPU models will, however, leave the guest OS vulnerable to +various CPU hardware flaws, so their use is strongly discouraged. +Applications should follow the earlier guidance to setup a better CPU +configuration, with host passthrough recommended if live migration is +not needed. + +* QEMU Virtual CPU version 2.5+ (32 & 64 bit variants) + + * ``qemu32`` + * ``qemu64`` + + ``qemu64`` is used for x86_64 guests and ``qemu32`` is used for i686 + guests, when no ``-cpu`` argument is given to QEMU, or no ``<cpu>`` is + provided in libvirt XML. + +Other non-recommended x86 CPUs +------------------------------ + +The following CPUs models are compatible with most AMD and Intel x86 +hosts, but their usage is discouraged, as they expose a very limited +featureset, which prevents guests having optimal performance. + +* Common KVM processor (32 & 64 bit variants): + + * ``kvm32`` + * ``kvm64`` + + Legacy models just for historical compatibility with ancient QEMU + versions. + +* Various very old x86 CPU models, mostly predating the introduction of + hardware assisted virtualization, that should thus not be required for + running virtual machines. + + * ``486`` + * ``athlon`` + * ``phenom`` + * ``coreduo`` + * ``core2duo`` + * ``n270`` + * ``pentium`` + * ``pentium2`` + * ``pentium3`` + + +Supported CPU model configurations on MIPS hosts +------------------------------------------------ + +QEMU supports variety of MIPS CPU models: + +Supported CPU models for MIPS32 hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following CPU models are supported for use on MIPS32 hosts. +Administrators / applications are recommended to use the CPU model that +matches the generation of the host CPUs in use. In a deployment with a +mixture of host CPU models between machines, if live migration +compatibility is required, use the newest CPU model that is compatible +across all desired hosts. + +* ``mips32r6-generic`` – MIPS32 Processor (Release 6, 2015) + +* ``P5600`` – MIPS32 Processor (P5600, 2014) + +* MIPS32 Processor (M14K, 2009) + + * ``M14K`` + * ``M14Kc`` + +* ``74Kf`` – MIPS32 Processor (74K, 2007) + +* ``34Kf`` – MIPS32 Processor (34K, 2006) + +* MIPS32 Processor (24K, 2003) + + * ``24Kc`` + * ``24KEc`` + * ``24Kf`` + +* MIPS32 Processor (4K, 1999) + + * ``4Kc`` + * ``4Km`` + * ``4KEcR1`` + * ``4KEmR1`` + * ``4KEc`` + * ``4KEm`` + + +Supported CPU models for MIPS64 hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following CPU models are supported for use on MIPS64 hosts. +Administrators / applications are recommended to use the CPU model that +matches the generation of the host CPUs in use. In a deployment with a +mixture of host CPU models between machines, if live migration +compatibility is required, use the newest CPU model that is compatible +across all desired hosts. + +* ``I6400`` – MIPS64 Processor (Release 6, 2014) + +* ``Loongson-2F`` – MIPS64 Processor (Loongson 2, 2008) + +* ``Loongson-2E`` – MIPS64 Processor (Loongson 2, 2006) + +* ``mips64dspr2`` – MIPS64 Processor (Release 2, 2006) + +* MIPS64 Processor (Release 2, 2002) + + * ``MIPS64R2-generic`` + * ``5KEc`` + * ``5KEf`` + +* ``20Kc`` – MIPS64 Processor (20K, 2000 + +* MIPS64 Processor (5K, 1999) + + * ``5Kc`` + * ``5Kf`` + +* ``VR5432`` – MIPS64 Processor (VR, 1998) + +* ``R4000`` – MIPS64 Processor (MIPS III, 1991) + + +Supported CPU models for nanoMIPS hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following CPU models are supported for use on nanoMIPS hosts. +Administrators / applications are recommended to use the CPU model that +matches the generation of the host CPUs in use. In a deployment with a +mixture of host CPU models between machines, if live migration +compatibility is required, use the newest CPU model that is compatible +across all desired hosts. + +* ``I7200`` – MIPS I7200 (nanoMIPS, 2018) + +Preferred CPU models for MIPS hosts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following CPU models are preferred for use on different MIPS hosts: + +* ``MIPS III`` – R4000 + +* ``MIPS32R2`` – 34Kf + +* ``MIPS64R6`` – I6400 + +* ``nanoMIPS`` – I7200 + +Syntax for configuring CPU models +--------------------------------- + +The examples below illustrate the approach to configuring the various +CPU models / features in QEMU and libvirt. + +QEMU command line +~~~~~~~~~~~~~~~~~ + +Host passthrough: + +.. parsed-literal:: + + |qemu_system| -cpu host + +Host passthrough with feature customization: + +.. parsed-literal:: + + |qemu_system| -cpu host,-vmx,... + +Named CPU models: + +.. parsed-literal:: + + |qemu_system| -cpu Westmere + +Named CPU models with feature customization: + +.. parsed-literal:: + + |qemu_system| -cpu Westmere,+pcid,... + +Libvirt guest XML +~~~~~~~~~~~~~~~~~ + +Host passthrough:: + + <cpu mode='host-passthrough'/> + +Host passthrough with feature customization:: + + <cpu mode='host-passthrough'> + <feature name="vmx" policy="disable"/> + ... + </cpu> + +Host model:: + + <cpu mode='host-model'/> + +Host model with feature customization:: + + <cpu mode='host-model'> + <feature name="vmx" policy="disable"/> + ... + </cpu> + +Named model:: + + <cpu mode='custom'> + <model name="Westmere"/> + </cpu> + +Named model with feature customization:: + + <cpu mode='custom'> + <model name="Westmere"/> + <feature name="pcid" policy="require"/> + ... + </cpu> diff --git a/qemu-doc.texi b/qemu-doc.texi index a1ef6b6484..c6a74877d6 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -616,11 +616,6 @@ The monitor understands integers expressions for every integer argument. You can use register names to get the value of specifics CPU registers by prefixing them with @emph{$}. -@node cpu_models -@section CPU models - -@include docs/qemu-cpu-models.texi - @node disk_images @section Disk Images -- 2.21.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST 2020-02-20 14:20 ` [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST Kashyap Chamarthy @ 2020-02-21 15:16 ` Peter Maydell 2020-02-21 15:31 ` Daniel P. Berrangé 2020-02-25 9:16 ` Kashyap Chamarthy 0 siblings, 2 replies; 11+ messages in thread From: Peter Maydell @ 2020-02-21 15:16 UTC (permalink / raw) To: Kashyap Chamarthy Cc: Paolo Bonzini, Richard Henderson, Daniel P. Berrange, QEMU Developers, Eduardo Habkost On Thu, 20 Feb 2020 at 14:20, Kashyap Chamarthy <kchamart@redhat.com> wrote: > > This doc was originally written by Daniel P. Berrangé > <berrange@redhat.com>, introduced via commit[1]: 2544e9e4aa (docs: add > guidance on configuring CPU models for x86, 2018-06-27). > > In this patch: > > - 1-1 conversion of Texinfo to rST, besides a couple of minor > tweaks that are too trivial to mention. (Thanks to Stephen > Finucane on IRC for the suggestion to use rST "definition lists" > instead of bullets in some places.) > > Further modifications will be done via a separate patch. > > - rST and related infra changes: for building the manual page, > Makefile fixes, clean up references to qemu-cpu-models.texi, etc. > > [1] https://git.qemu.org/?p=qemu.git;a=commit;h=2544e9e4aa > > Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> > --- > v2: Fix rST conversion, man page creation, Makefile changes, et al > (thanks, Peter Maydell) > --- > MAINTAINERS | 2 +- > Makefile | 10 +- > docs/qemu-cpu-models.texi | 677 -------------------------------- > docs/system/conf.py | 3 + > docs/system/index.rst | 1 + > docs/system/qemu-cpu-models.rst | 514 ++++++++++++++++++++++++ > qemu-doc.texi | 5 - > 7 files changed, 524 insertions(+), 688 deletions(-) > delete mode 100644 docs/qemu-cpu-models.texi > create mode 100644 docs/system/qemu-cpu-models.rst > @@ -1056,6 +1055,8 @@ $(call define-manpage-rule,interop,\ > > $(call define-manpage-rule,system,qemu-block-drivers.7) > > +$(call define-manpage-rule,system,qemu-cpu-models.7) The new manpage should be added to the existing define-manpage-rule invocation for the system manual: the last argument is a space separated list of all the manpages in the manual, like this: $(call define-manpage-rule,system,qemu-block-drivers.7 qemu-cpu-models.7) > + > $(MANUAL_BUILDDIR)/index.html: $(SRC_PATH)/docs/index.html.in qemu-version.h > @mkdir -p "$(MANUAL_BUILDDIR)" > $(call quiet-command, sed "s|@@VERSION@@|${VERSION}|g" $< >$@, \ > -@c man begin AUTHOR > -Daniel P. Berrange > -@c man end > diff --git a/docs/system/conf.py b/docs/system/conf.py > index 7ca115f5e0..7cc9da9508 100644 > --- a/docs/system/conf.py > +++ b/docs/system/conf.py > @@ -18,5 +18,8 @@ html_theme_options['description'] = u'System Emulation User''s Guide' > man_pages = [ > ('qemu-block-drivers', 'qemu-block-drivers', > u'QEMU block drivers reference', > + ['Fabrice Bellard and the QEMU Project developers'], 7), > + ('qemu-cpu-models', 'qemu-cpu-models', > + u'QEMU CPU Models', > ['Fabrice Bellard and the QEMU Project developers'], 7) > ] The old manpage/documentation credits Dan as the author, so that's what we should specify in the conf.py line, rather than 'Fabrice and the project devs' (which we use for qemu-block-drivers.7 because that's what the old texi version of that file specified as the authors). > +Preferred CPU models for Intel x86 hosts > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +The following CPU models are preferred for use on Intel hosts. > +Administrators / applications are recommended to use the CPU model that > +matches the generation of the host CPUs in use. In a deployment with a > +mixture of host CPU models between machines, if live migration > +compatibility is required, use the newest CPU model that is compatible > +across all desired hosts. > + > +* Intel Xeon Processor (Skylake, 2016) > + > + * ``Skylake-Server`` > + * ``Skylake-Server-IBRS`` This reverses the old ordering of these lists, which consistently had the QEMU CPU model names as the 'term' and the explanations as the 'definition' of a definition-list. Now we have the 'explanation' first and the 'terms' second... > +* AMD EPYC Processor (2017) > + > + * ``EPYC`` > + * ``EPYC-IBPB`` > + > +* ``Opteron_G5`` – AMD Opteron 63xx class CPU (2012) > + > +* ``Opteron_G4`` – AMD Opteron 62xx class CPU (2011) > + > +* ``Opteron_G3`` – AMD Opteron 23xx (Gen 3 Class Opteron, 2009) > + > +* ``Opteron_G2`` – AMD Opteron 22xx (Gen 2 Class Opteron, 2006) > + > +* ``Opteron_G1`` – AMD Opteron 240 (Gen 1 Class Opteron, 2004) ...but here we become inconsistent, switching back to term first and explanation second. I think the term-first approach of the original texi makes more sense, as we're trying to document the behaviour of the various CPU models QEMU supports. rST is not a fan of having multiple definition list items sharing a definition, which is probably why you ended up with the list approach you did, but we can do: ``Skylake-Server``, ``Skylake-Server-IBRS`` Intel Xeon Processor (Skylake, 2016) ``Skylake-Client``, ``Skylake-Client-IBRS`` Intel Core Processor (Skylake, 2015) Or we can actually document what the difference is between a "Skylake-Server" and a "Skylake-Server-IBRS", rather than leaving the user to guess :-), in which case we could write ``Skylake-Server`` Intel Xeon Processor (Skylake, 2016) ``Skylake-Server-IBRS`` Like ``Skylake-Server`` but with extra magic (or whatever the difference is...) Regardless of how we format this, we should be consistent in using the same format throughout the document. thanks -- PMM ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST 2020-02-21 15:16 ` Peter Maydell @ 2020-02-21 15:31 ` Daniel P. Berrangé 2020-02-21 15:36 ` Peter Maydell 2020-02-25 9:16 ` Kashyap Chamarthy 1 sibling, 1 reply; 11+ messages in thread From: Daniel P. Berrangé @ 2020-02-21 15:31 UTC (permalink / raw) To: Peter Maydell Cc: Paolo Bonzini, Richard Henderson, QEMU Developers, Eduardo Habkost, Kashyap Chamarthy On Fri, Feb 21, 2020 at 03:16:29PM +0000, Peter Maydell wrote: > On Thu, 20 Feb 2020 at 14:20, Kashyap Chamarthy <kchamart@redhat.com> wrote: > > > > This doc was originally written by Daniel P. Berrangé > > <berrange@redhat.com>, introduced via commit[1]: 2544e9e4aa (docs: add > > guidance on configuring CPU models for x86, 2018-06-27). > > > > In this patch: > > > > - 1-1 conversion of Texinfo to rST, besides a couple of minor > > tweaks that are too trivial to mention. (Thanks to Stephen > > Finucane on IRC for the suggestion to use rST "definition lists" > > instead of bullets in some places.) > > > > Further modifications will be done via a separate patch. > > > > - rST and related infra changes: for building the manual page, > > Makefile fixes, clean up references to qemu-cpu-models.texi, etc. > > > > [1] https://git.qemu.org/?p=qemu.git;a=commit;h=2544e9e4aa > > > > Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> > > --- > > v2: Fix rST conversion, man page creation, Makefile changes, et al > > (thanks, Peter Maydell) > > --- > > MAINTAINERS | 2 +- > > Makefile | 10 +- > > docs/qemu-cpu-models.texi | 677 -------------------------------- > > docs/system/conf.py | 3 + > > docs/system/index.rst | 1 + > > docs/system/qemu-cpu-models.rst | 514 ++++++++++++++++++++++++ > > qemu-doc.texi | 5 - > > 7 files changed, 524 insertions(+), 688 deletions(-) > > delete mode 100644 docs/qemu-cpu-models.texi > > create mode 100644 docs/system/qemu-cpu-models.rst > > > @@ -1056,6 +1055,8 @@ $(call define-manpage-rule,interop,\ > > > > $(call define-manpage-rule,system,qemu-block-drivers.7) > > > > +$(call define-manpage-rule,system,qemu-cpu-models.7) > > The new manpage should be added to the existing define-manpage-rule > invocation for the system manual: the last argument is a space > separated list of all the manpages in the manual, like this: > > $(call define-manpage-rule,system,qemu-block-drivers.7 qemu-cpu-models.7) > > > + > > $(MANUAL_BUILDDIR)/index.html: $(SRC_PATH)/docs/index.html.in qemu-version.h > > @mkdir -p "$(MANUAL_BUILDDIR)" > > $(call quiet-command, sed "s|@@VERSION@@|${VERSION}|g" $< >$@, \ > > > > > -@c man begin AUTHOR > > -Daniel P. Berrange > > -@c man end > > > diff --git a/docs/system/conf.py b/docs/system/conf.py > > index 7ca115f5e0..7cc9da9508 100644 > > --- a/docs/system/conf.py > > +++ b/docs/system/conf.py > > @@ -18,5 +18,8 @@ html_theme_options['description'] = u'System Emulation User''s Guide' > > man_pages = [ > > ('qemu-block-drivers', 'qemu-block-drivers', > > u'QEMU block drivers reference', > > + ['Fabrice Bellard and the QEMU Project developers'], 7), > > + ('qemu-cpu-models', 'qemu-cpu-models', > > + u'QEMU CPU Models', > > ['Fabrice Bellard and the QEMU Project developers'], 7) > > ] > > The old manpage/documentation credits Dan as the author, > so that's what we should specify in the conf.py line, > rather than 'Fabrice and the project devs' (which we > use for qemu-block-drivers.7 because that's what the > old texi version of that file specified as the authors). I agree that listing Fabrice explicitly here is wrong since he didn't write any of it. As the author, I don't feel a need for my name to be explicitly credited here. QEMU is a collaborative project and other people add text to this over time. Indeed IME explicitly listing an individual encourages users to directly email the individual person with questions, instead of using the mailing list / irc / forums. Thus I would personally prefer if we just used "The QEMU Project maintainers" as the author credit > > +Preferred CPU models for Intel x86 hosts > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > + > > +The following CPU models are preferred for use on Intel hosts. > > +Administrators / applications are recommended to use the CPU model that > > +matches the generation of the host CPUs in use. In a deployment with a > > +mixture of host CPU models between machines, if live migration > > +compatibility is required, use the newest CPU model that is compatible > > +across all desired hosts. > > + > > +* Intel Xeon Processor (Skylake, 2016) > > + > > + * ``Skylake-Server`` > > + * ``Skylake-Server-IBRS`` > > This reverses the old ordering of these lists, which consistently > had the QEMU CPU model names as the 'term' and the explanations > as the 'definition' of a definition-list. Now we have the > 'explanation' first and the 'terms' second... Yep, the model name used for the "-cpu NAME" arg is the most important piece of information IMHO. The human description is just a side note. Regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST 2020-02-21 15:31 ` Daniel P. Berrangé @ 2020-02-21 15:36 ` Peter Maydell 0 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2020-02-21 15:36 UTC (permalink / raw) To: Daniel P. Berrangé Cc: Paolo Bonzini, Richard Henderson, QEMU Developers, Eduardo Habkost, Kashyap Chamarthy On Fri, 21 Feb 2020 at 15:31, Daniel P. Berrangé <berrange@redhat.com> wrote: > > On Fri, Feb 21, 2020 at 03:16:29PM +0000, Peter Maydell wrote: > > On Thu, 20 Feb 2020 at 14:20, Kashyap Chamarthy <kchamart@redhat.com> wrote: > > > diff --git a/docs/system/conf.py b/docs/system/conf.py > > > index 7ca115f5e0..7cc9da9508 100644 > > > --- a/docs/system/conf.py > > > +++ b/docs/system/conf.py > > > @@ -18,5 +18,8 @@ html_theme_options['description'] = u'System Emulation User''s Guide' > > > man_pages = [ > > > ('qemu-block-drivers', 'qemu-block-drivers', > > > u'QEMU block drivers reference', > > > + ['Fabrice Bellard and the QEMU Project developers'], 7), > > > + ('qemu-cpu-models', 'qemu-cpu-models', > > > + u'QEMU CPU Models', > > > ['Fabrice Bellard and the QEMU Project developers'], 7) > > > ] > > > > The old manpage/documentation credits Dan as the author, > > so that's what we should specify in the conf.py line, > > rather than 'Fabrice and the project devs' (which we > > use for qemu-block-drivers.7 because that's what the > > old texi version of that file specified as the authors). > > I agree that listing Fabrice explicitly here is wrong > since he didn't write any of it. > > As the author, I don't feel a need for my name to be > explicitly credited here. QEMU is a collaborative project > and other people add text to this over time. Indeed IME > explicitly listing an individual encourages users to > directly email the individual person with questions, > instead of using the mailing list / irc / forums. > > Thus I would personally prefer if we just used > > "The QEMU Project maintainers" > > as the author credit Sure, if you want to update the author credit (which you originally picked in commit 2544e9e4aa2bcef :-)) we can do that, though our standard phrasing (see the QEMU_COPYRIGHT #define in qemu-common.h) is "The QEMU Project developers" so I'd rather we stuck with that than "maintainers". Mostly I want to avoid our rST conversion accidentally dropping or changing existing authorship/attribution information, so maybe we should change the authorship in a follow-on patch. thanks -- PMM ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST 2020-02-21 15:16 ` Peter Maydell 2020-02-21 15:31 ` Daniel P. Berrangé @ 2020-02-25 9:16 ` Kashyap Chamarthy 2020-02-25 14:22 ` Kashyap Chamarthy 1 sibling, 1 reply; 11+ messages in thread From: Kashyap Chamarthy @ 2020-02-25 9:16 UTC (permalink / raw) To: Peter Maydell Cc: Paolo Bonzini, Richard Henderson, Daniel P. Berrange, QEMU Developers, Eduardo Habkost On Fri, Feb 21, 2020 at 03:16:29PM +0000, Peter Maydell wrote: > On Thu, 20 Feb 2020 at 14:20, Kashyap Chamarthy <kchamart@redhat.com> wrote: [...] > > @@ -1056,6 +1055,8 @@ $(call define-manpage-rule,interop,\ > > > > $(call define-manpage-rule,system,qemu-block-drivers.7) > > > > +$(call define-manpage-rule,system,qemu-cpu-models.7) > > The new manpage should be added to the existing define-manpage-rule > invocation for the system manual: the last argument is a space > separated list of all the manpages in the manual, like this: > > $(call define-manpage-rule,system,qemu-block-drivers.7 qemu-cpu-models.7) Ah, will fix. [...] > > +++ b/docs/system/conf.py > > @@ -18,5 +18,8 @@ html_theme_options['description'] = u'System Emulation User''s Guide' > > man_pages = [ > > ('qemu-block-drivers', 'qemu-block-drivers', > > u'QEMU block drivers reference', > > + ['Fabrice Bellard and the QEMU Project developers'], 7), > > + ('qemu-cpu-models', 'qemu-cpu-models', > > + u'QEMU CPU Models', > > ['Fabrice Bellard and the QEMU Project developers'], 7) > > ] > > The old manpage/documentation credits Dan as the author, > so that's what we should specify in the conf.py line, > rather than 'Fabrice and the project devs' (which we > use for qemu-block-drivers.7 because that's what the > old texi version of that file specified as the authors). Yeah, I first felt strange adding "Fabrice and the QEMU Project developers". But as you've guessed I just picked what you used for 'qemu-block-drivers.7'. That's why I mentioned Dan and his original commit ID in my commit message, for clear posterity. As Dan says in his follow-up, a file indeed usually gets modified over time. And given the follow-up interaction between you and Dan, in the next iteration, I'll change it to: "The QEMU Project developers". (While I agree that we should be careful to not mix attribution changes with the noise of rST conversion, maybe in this case a seperate commit is an overkill; hope it is okay if I call it out in the commit message.) > > +Preferred CPU models for Intel x86 hosts > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > + > > +The following CPU models are preferred for use on Intel hosts. > > +Administrators / applications are recommended to use the CPU model that > > +matches the generation of the host CPUs in use. In a deployment with a > > +mixture of host CPU models between machines, if live migration > > +compatibility is required, use the newest CPU model that is compatible > > +across all desired hosts. > > + > > +* Intel Xeon Processor (Skylake, 2016) > > + > > + * ``Skylake-Server`` > > + * ``Skylake-Server-IBRS`` > > This reverses the old ordering of these lists, which consistently > had the QEMU CPU model names as the 'term' and the explanations > as the 'definition' of a definition-list. Now we have the > 'explanation' first and the 'terms' second... Yeah, as you guessed, I was trying to wrangle with rST syntax. > > +* AMD EPYC Processor (2017) > > + > > + * ``EPYC`` > > + * ``EPYC-IBPB`` > > + > > +* ``Opteron_G5`` – AMD Opteron 63xx class CPU (2012) > > + > > +* ``Opteron_G4`` – AMD Opteron 62xx class CPU (2011) > > + > > +* ``Opteron_G3`` – AMD Opteron 23xx (Gen 3 Class Opteron, 2009) > > + > > +* ``Opteron_G2`` – AMD Opteron 22xx (Gen 2 Class Opteron, 2006) > > + > > +* ``Opteron_G1`` – AMD Opteron 240 (Gen 1 Class Opteron, 2004) > > ...but here we become inconsistent, switching back to > term first and explanation second. I think the > term-first approach of the original texi makes more sense, > as we're trying to document the behaviour of the various > CPU models QEMU supports. True, I'll stick with the term-first approach, and get rid of the inconsistency. > rST is not a fan of having multiple definition list items > sharing a definition, which is probably why you ended up with > the list approach you did, but we can do: > > ``Skylake-Server``, ``Skylake-Server-IBRS`` > Intel Xeon Processor (Skylake, 2016) > > ``Skylake-Client``, ``Skylake-Client-IBRS`` > Intel Core Processor (Skylake, 2015) > > Or we can actually document what the difference is between > a "Skylake-Server" and a "Skylake-Server-IBRS", rather than > leaving the user to guess :-), in which case we could write > ``Skylake-Server`` > Intel Xeon Processor (Skylake, 2016) > ``Skylake-Server-IBRS`` > Like ``Skylake-Server`` but with extra magic > > (or whatever the difference is...) (The difference is the -IBRS models have 'spec-ctrl' CPU flag baked in.) And yes, I like the latter approach — explicitly spelling it out reduces cogntive load for the readers. > Regardless of how we format this, we should be consistent > in using the same format throughout the document. Agree, will fix. Thanks for the eagle eyes, as usual. :-) [...] -- /kashyap ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST 2020-02-25 9:16 ` Kashyap Chamarthy @ 2020-02-25 14:22 ` Kashyap Chamarthy 0 siblings, 0 replies; 11+ messages in thread From: Kashyap Chamarthy @ 2020-02-25 14:22 UTC (permalink / raw) To: Peter Maydell Cc: Paolo Bonzini, Richard Henderson, Daniel P. Berrange, QEMU Developers, Eduardo Habkost On Tue, Feb 25, 2020 at 10:16:11AM +0100, Kashyap Chamarthy wrote: > On Fri, Feb 21, 2020 at 03:16:29PM +0000, Peter Maydell wrote: [...] > > rST is not a fan of having multiple definition list items > > sharing a definition, which is probably why you ended up with > > the list approach you did, but we can do: > > > > ``Skylake-Server``, ``Skylake-Server-IBRS`` > > Intel Xeon Processor (Skylake, 2016) > > > > ``Skylake-Client``, ``Skylake-Client-IBRS`` > > Intel Core Processor (Skylake, 2015) For this series, I'll stick with the above approach throughout. And will do the separate description of each model and how it differs from the previous, as a follow-up. (No, I won't forget about it :-)) [...] -- /kashyap ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl 2020-02-20 14:19 [PATCH v3 0/2] qemu-cpu-models: Convert to rST; document other MSR bits Kashyap Chamarthy 2020-02-20 14:20 ` [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST Kashyap Chamarthy @ 2020-02-20 14:20 ` Kashyap Chamarthy 2020-02-20 14:52 ` Paolo Bonzini 1 sibling, 1 reply; 11+ messages in thread From: Kashyap Chamarthy @ 2020-02-20 14:20 UTC (permalink / raw) To: qemu-devel Cc: peter.maydell, berrange, Eduardo Habkost, kchamart, Paolo Bonzini, Richard Henderson - Add the '-noTSX' variants for CascadeLake and SkyLake. - Document the three MSR bits: 'mds-no', 'taa-no', and 'tsx-ctrl' Two confusing things about 'mds-no' (and the first point applies to the other two MSRs too): (1) The 'mds-no' bit will _not_ show up in the guest's /proc/cpuinfo. Rather it is used to fill in the guest's sysfs: /sys/devices/system/cpu/vulnerabilities/mds:Not affected Paolo confirmed on IRC as such. (2) There are _three_ variants[+] of CascadeLake CPUs, with different stepping levels: 5, 6, and 7. To quote wikichip.org[*]: "note that while steppings 6 & 7 are fully mitigated, earlier stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM" The above is also indicated in the Intel's document[+], as indicated by "No" under the three columns of MFBDS, MSBDS, and MLPDS. I've expressed this in the docs without belabouring the details. [+] https://software.intel.com/security-software-guidance/insights/processors-affected-microarchitectural-data-sampling [*] https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake#Key_changes_from_Skylake Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> --- --- [Retaining parts of the change-log from the Texinfo-variant of this patch, which is now no-longer needed: https://lists.nongnu.org/archive/html/qemu-devel/2020-01/msg06455.html] v3: - Makefile, Sphinx and related fixes (Peter Maydell) - Address feedback from Paolo - Add URL to the deep-dive on Intel's MDS v2: - Address feedback from DanPB - Add sections on 'taa-no' and 'tsx-ctrl' Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> --- docs/system/qemu-cpu-models.rst | 57 +++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/docs/system/qemu-cpu-models.rst b/docs/system/qemu-cpu-models.rst index a189d6a9da..946e90e1dc 100644 --- a/docs/system/qemu-cpu-models.rst +++ b/docs/system/qemu-cpu-models.rst @@ -61,15 +61,24 @@ mixture of host CPU models between machines, if live migration compatibility is required, use the newest CPU model that is compatible across all desired hosts. +* Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6 or + 7 only. (The Cascade Lake Xeon processor with *stepping 5 is + vulnerable to MDS variants*.) + + * ``Cascadelake-Server`` + * ``Cascadelake-Server-noTSX`` + * Intel Xeon Processor (Skylake, 2016) * ``Skylake-Server`` * ``Skylake-Server-IBRS`` + * ``Skylake-Server-IBRS-noTSX`` * Intel Core Processor (Skylake, 2015) * ``Skylake-Client`` * ``Skylake-Client-IBRS`` + * ``Skylake-Client-noTSX-IBRS}`` * Intel Core Processor (Broadwell, 2014) @@ -182,6 +191,54 @@ features are included if using "Host passthrough" or "Host model". Requires the host CPU microcode to support this feature before it can be used for guest CPUs. +``mds-no`` + Recommended to inform the guest OS that the host is *not* vulnerable + to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS] + CVE-2018-12127, [MSBDS] CVE-2018-12126). + + This is an MSR (Model-Specific Register) feature rather than a CPUID feature, + so it will not appear in the Linux ``/proc/cpuinfo`` in the host or + guest. Instead, the host kernel uses it to populate the MDS + vulnerability file in ``sysfs``. + + So it should only be enabled for VMs if the host reports @code{Not + affected} in the ``/sys/devices/system/cpu/vulnerabilities/mds`` file. + +``taa-no`` + Recommended to inform that the guest that the host is ``not`` + vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA). + + This too is an MSR feature, so it does not show up in the Linux + ``/proc/cpuinfo`` in the host or guest. + + It should only be enabled for VMs if the host reports ``Not affected`` + in the ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` + file. + +``tsx-ctrl`` + Recommended to inform the guest that it can disable the Intel TSX + (Transactional Synchronization Extensions) feature; or, if the + processor is vulnerable, use the Intel VERW instruction (a + processor-level instruction that performs checks on memory access) as + a mitigation for the TAA vulnerability. (For details, refer to this + `Intel's deep-dive into + MDS <https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling>`_.) + + Expose this to the guest OS if and only if: (a) the host has TSX + enabled; *and* (b) the guest has ``rtm`` CPU flag enabled. + + By disabling TSX, KVM-based guests can avoid paying the price of + mitigting TSX-based attacks. + + Note that ``tsx-ctrl`` too is an MSR feature, so it does not show + up in the Linux ``/proc/cpuinfo`` in the host or guest. + + To validate that Intel TSX is indeed disabled for the guest, there are + two ways: (a) check for the *absence* of ``rtm`` in the guest's + ``/proc/cpuinfo``; or (b) the + ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` file in + the guest should report ``Mitigation: TSX disabled``. + Preferred CPU models for AMD x86 hosts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- 2.21.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl 2020-02-20 14:20 ` [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl Kashyap Chamarthy @ 2020-02-20 14:52 ` Paolo Bonzini 2020-02-20 15:45 ` Peter Maydell 0 siblings, 1 reply; 11+ messages in thread From: Paolo Bonzini @ 2020-02-20 14:52 UTC (permalink / raw) To: Kashyap Chamarthy, qemu-devel Cc: peter.maydell, berrange, Eduardo Habkost, Richard Henderson Two small changes... On 20/02/20 15:20, Kashyap Chamarthy wrote: > + Recommended to inform the guest that it can disable the Intel TSX > + (Transactional Synchronization Extensions) feature; or, if the > + processor is vulnerable, use the Intel VERW instruction (a > + processor-level instruction that performs checks on memory access) as > + a mitigation for the TAA vulnerability. (For details, refer to this > + `Intel's deep-dive into > + MDS <https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling>`_.) ... refer to Intel's `deep dive into MDS <...>`_. (I don't know what the trailing underscore is for. I reaffirm my definition of rST as the Perl of markup formats). > + > + Expose this to the guest OS if and only if: (a) the host has TSX > + enabled; *and* (b) the guest has ``rtm`` CPU flag enabled. > + > + By disabling TSX, KVM-based guests can avoid paying the price of > + mitigting TSX-based attacks. "mitigating" Paolo ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl 2020-02-20 14:52 ` Paolo Bonzini @ 2020-02-20 15:45 ` Peter Maydell 0 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2020-02-20 15:45 UTC (permalink / raw) To: Paolo Bonzini Cc: Richard Henderson, Daniel P. Berrange, QEMU Developers, Eduardo Habkost, Kashyap Chamarthy On Thu, 20 Feb 2020 at 14:52, Paolo Bonzini <pbonzini@redhat.com> wrote: > ... refer to Intel's `deep dive into MDS <...>`_. > > (I don't know what the trailing underscore is for. It's because the external-hyperlink syntax is a complication of the simpler format for within-document references. Inside a document, you can have a simple link like this: This is a link to the target_ defined below. .. _target: This is where the link target defined above goes to. So trailing underscore is for words that go to somewhere else, and leading underscore for words that come from somewhere else. Syntax complication 1 is that instead of word_ you can say `some phrase with spaces`_ if you want the link to span more than one word. (The docutils spec calls these "phrase-references"). Syntax complication 2 is that instead of having to define the target of an external URL separately from the place you wanted to refer to it, like this: .. _target: http://somewhere-else.org/ you can directly embed it inside a phrase-reference: Go to `somewhere external <http://somewhere-else.org/>`_ which is more convenient if you only wanted to use the URL once. But the _ is still there because it's still the markup that indicates "this is going be a link to go somewhere". > I reaffirm my definition of rST as the Perl of markup formats). Not going to argue with that :-) But like Perl, there's usually some kind of a rationale lurking under the surface. thanks -- PMM ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 0/2] qemu-cpu-models: Convert to rST; document other MSR bits
@ 2020-02-20 14:02 Kashyap Chamarthy
2020-02-20 14:02 ` [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl Kashyap Chamarthy
0 siblings, 1 reply; 11+ messages in thread
From: Kashyap Chamarthy @ 2020-02-20 14:02 UTC (permalink / raw)
To: kchamart, qemu-devel; +Cc: peter.maydell, berrange, ehabkost
In v3:
- Address the comments from Peter Maydell, from here:
https://lists.nongnu.org/archive/html/qemu-devel/2020-02/msg05155.html
This small series does two things:
(1) Convert the original qemu-cpu-models.texi to rST
(2) In a separate patch, incorporate the additional new content from
this:
https://lists.nongnu.org/archive/html/qemu-devel/2020-01/msg06455.html
([PATCH v3] qemu-cpu-models: Document -noTSX, mds-no, taa-no, and
tsx-ctrl)
A Sphinx rendering of the converted doc is here:
https://kashyapc.fedorapeople.org/QEMU_v4.2.0-1301-gb082353c5e_docs/system/qemu-cpu-models.html
Kashyap Chamarthy (2):
docs: Convert qemu-cpu-models.texi to rST
qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl
MAINTAINERS | 2 +-
Makefile | 10 +-
docs/qemu-cpu-models.texi | 677 --------------------------------
docs/system/conf.py | 3 +
docs/system/index.rst | 1 +
docs/system/qemu-cpu-models.rst | 571 +++++++++++++++++++++++++++
qemu-doc.texi | 5 -
7 files changed, 581 insertions(+), 688 deletions(-)
delete mode 100644 docs/qemu-cpu-models.texi
create mode 100644 docs/system/qemu-cpu-models.rst
--
2.21.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl 2020-02-20 14:02 [PATCH v3 0/2] qemu-cpu-models: Convert to rST; document other MSR bits Kashyap Chamarthy @ 2020-02-20 14:02 ` Kashyap Chamarthy 0 siblings, 0 replies; 11+ messages in thread From: Kashyap Chamarthy @ 2020-02-20 14:02 UTC (permalink / raw) To: kchamart, qemu-devel; +Cc: peter.maydell, berrange, ehabkost - Add the '-noTSX' variants for CascadeLake and SkyLake. - Document the three MSR bits: 'mds-no', 'taa-no', and 'tsx-ctrl' Two confusing things about 'mds-no' (and the first point applies to the other two MSRs too): (1) The 'mds-no' bit will _not_ show up in the guest's /proc/cpuinfo. Rather it is used to fill in the guest's sysfs: /sys/devices/system/cpu/vulnerabilities/mds:Not affected Paolo confirmed on IRC as such. (2) There are _three_ variants[+] of CascadeLake CPUs, with different stepping levels: 5, 6, and 7. To quote wikichip.org[*]: "note that while steppings 6 & 7 are fully mitigated, earlier stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM" The above is also indicated in the Intel's document[+], as indicated by "No" under the three columns of MFBDS, MSBDS, and MLPDS. I've expressed this in the docs without belabouring the details. [+] https://software.intel.com/security-software-guidance/insights/processors-affected-microarchitectural-data-sampling [*] https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake#Key_changes_from_Skylake Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> --- docs/system/qemu-cpu-models.rst | 57 +++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/docs/system/qemu-cpu-models.rst b/docs/system/qemu-cpu-models.rst index a189d6a9da..946e90e1dc 100644 --- a/docs/system/qemu-cpu-models.rst +++ b/docs/system/qemu-cpu-models.rst @@ -61,15 +61,24 @@ mixture of host CPU models between machines, if live migration compatibility is required, use the newest CPU model that is compatible across all desired hosts. +* Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6 or + 7 only. (The Cascade Lake Xeon processor with *stepping 5 is + vulnerable to MDS variants*.) + + * ``Cascadelake-Server`` + * ``Cascadelake-Server-noTSX`` + * Intel Xeon Processor (Skylake, 2016) * ``Skylake-Server`` * ``Skylake-Server-IBRS`` + * ``Skylake-Server-IBRS-noTSX`` * Intel Core Processor (Skylake, 2015) * ``Skylake-Client`` * ``Skylake-Client-IBRS`` + * ``Skylake-Client-noTSX-IBRS}`` * Intel Core Processor (Broadwell, 2014) @@ -182,6 +191,54 @@ features are included if using "Host passthrough" or "Host model". Requires the host CPU microcode to support this feature before it can be used for guest CPUs. +``mds-no`` + Recommended to inform the guest OS that the host is *not* vulnerable + to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS] + CVE-2018-12127, [MSBDS] CVE-2018-12126). + + This is an MSR (Model-Specific Register) feature rather than a CPUID feature, + so it will not appear in the Linux ``/proc/cpuinfo`` in the host or + guest. Instead, the host kernel uses it to populate the MDS + vulnerability file in ``sysfs``. + + So it should only be enabled for VMs if the host reports @code{Not + affected} in the ``/sys/devices/system/cpu/vulnerabilities/mds`` file. + +``taa-no`` + Recommended to inform that the guest that the host is ``not`` + vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA). + + This too is an MSR feature, so it does not show up in the Linux + ``/proc/cpuinfo`` in the host or guest. + + It should only be enabled for VMs if the host reports ``Not affected`` + in the ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` + file. + +``tsx-ctrl`` + Recommended to inform the guest that it can disable the Intel TSX + (Transactional Synchronization Extensions) feature; or, if the + processor is vulnerable, use the Intel VERW instruction (a + processor-level instruction that performs checks on memory access) as + a mitigation for the TAA vulnerability. (For details, refer to this + `Intel's deep-dive into + MDS <https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling>`_.) + + Expose this to the guest OS if and only if: (a) the host has TSX + enabled; *and* (b) the guest has ``rtm`` CPU flag enabled. + + By disabling TSX, KVM-based guests can avoid paying the price of + mitigting TSX-based attacks. + + Note that ``tsx-ctrl`` too is an MSR feature, so it does not show + up in the Linux ``/proc/cpuinfo`` in the host or guest. + + To validate that Intel TSX is indeed disabled for the guest, there are + two ways: (a) check for the *absence* of ``rtm`` in the guest's + ``/proc/cpuinfo``; or (b) the + ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` file in + the guest should report ``Mitigation: TSX disabled``. + Preferred CPU models for AMD x86 hosts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- 2.21.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-02-25 14:23 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-20 14:19 [PATCH v3 0/2] qemu-cpu-models: Convert to rST; document other MSR bits Kashyap Chamarthy 2020-02-20 14:20 ` [PATCH v3 1/2] docs: Convert qemu-cpu-models.texi to rST Kashyap Chamarthy 2020-02-21 15:16 ` Peter Maydell 2020-02-21 15:31 ` Daniel P. Berrangé 2020-02-21 15:36 ` Peter Maydell 2020-02-25 9:16 ` Kashyap Chamarthy 2020-02-25 14:22 ` Kashyap Chamarthy 2020-02-20 14:20 ` [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl Kashyap Chamarthy 2020-02-20 14:52 ` Paolo Bonzini 2020-02-20 15:45 ` Peter Maydell -- strict thread matches above, loose matches on Subject: below -- 2020-02-20 14:02 [PATCH v3 0/2] qemu-cpu-models: Convert to rST; document other MSR bits Kashyap Chamarthy 2020-02-20 14:02 ` [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl Kashyap Chamarthy
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