From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 05/11] target/arm: Enforce alignment for SRS
Date: Thu, 3 Dec 2020 11:38:54 +0000 [thread overview]
Message-ID: <CAFEAcA_U9XMqJmYEWm340T=MWuzUgNFZXC58vD7QimD2ny2n6w@mail.gmail.com> (raw)
In-Reply-To: <20201125040642.2339476-6-richard.henderson@linaro.org>
On Wed, 25 Nov 2020 at 04:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 4406f6a67c..b1f43bfb8f 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -5124,11 +5124,13 @@ static void gen_srs(DisasContext *s,
> }
> tcg_gen_addi_i32(addr, addr, offset);
> tmp = load_reg(s, 14);
> - gen_aa32_st32(s, tmp, addr, get_mem_index(s));
> + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
> + MO_UL | MO_ALIGN | s->be_data);
> tcg_temp_free_i32(tmp);
> tmp = load_cpu_field(spsr);
> tcg_gen_addi_i32(addr, addr, 4);
> - gen_aa32_st32(s, tmp, addr, get_mem_index(s));
> + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
> + MO_UL | MO_ALIGN | s->be_data);
Having just come back to look at this as a result of reading
a review comment from you on the v8.1M series, it's a bit
unfortunate that we now have to remember to factor in s->be_data
in every memory access. Previously gen_aa32_st32() got this
right for us automatically, as well as being able to provide
the right sized MO_UL or whatever part... Can we make the
new API a bit less awkward ? (I suspect we're eventually
going to want to be able to pass an enum for "always OK
unaligned", "never OK unaligned", or "OK unaligned only
if SCTLR.A is 0", for that matter.)
thanks
-- PMM
next prev parent reply other threads:[~2020-12-03 11:40 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 4:06 [PATCH for-6.0 00/11] target/arm: enforce alignment Richard Henderson
2020-11-25 4:06 ` [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2020-11-25 8:11 ` Philippe Mathieu-Daudé
2020-11-25 4:06 ` [PATCH 02/11] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2020-11-25 8:13 ` Philippe Mathieu-Daudé
2020-11-25 4:06 ` [PATCH 03/11] target/arm: Enforce alignment for LDM/STM Richard Henderson
2020-11-25 4:06 ` [PATCH 04/11] target/arm: Enforce alignment for RFE Richard Henderson
2020-11-25 4:06 ` [PATCH 05/11] target/arm: Enforce alignment for SRS Richard Henderson
2020-12-03 11:38 ` Peter Maydell [this message]
2020-11-25 4:06 ` [PATCH 06/11] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2020-11-25 4:06 ` [PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2020-11-25 4:06 ` [PATCH 08/11] target/arm: Enforce alignment for VLD1 (all lanes) Richard Henderson
2020-11-25 4:06 ` [PATCH 09/11] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2020-11-25 4:06 ` [PATCH 10/11] target/arm: Fix decode of align in VLDST_single Richard Henderson
2020-12-01 14:09 ` Peter Maydell
2020-11-25 4:06 ` [PATCH 11/11] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2020-12-01 14:27 ` [PATCH for-6.0 00/11] target/arm: enforce alignment Peter Maydell
2020-12-01 14:37 ` Richard Henderson
2020-12-01 15:55 ` Peter Maydell
2020-12-03 12:30 ` Philippe Mathieu-Daudé
2020-12-03 16:10 ` Pavel Dovgalyuk
2020-12-03 16:14 ` Peter Maydell
2020-12-04 6:17 ` Pavel Dovgalyuk
2020-12-04 16:36 ` Peter Maydell
2020-12-04 17:28 ` Richard Henderson
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