From: Peter Maydell <peter.maydell@linaro.org>
To: Damien Hedde <damien.hedde@greensocs.com>
Cc: "Daniel P. Berrange" <berrange@redhat.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Mark Burton" <mark.burton@greensocs.com>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
qemu-arm <qemu-arm@nongnu.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v6 7/9] hw/misc/zynq_slcr: add clock generation for uarts
Date: Mon, 2 Dec 2019 15:20:12 +0000 [thread overview]
Message-ID: <CAFEAcA_mmBeVnx5TsdeEaEU=jNnkFR9aa-nziaTQD7par7GpoA@mail.gmail.com> (raw)
In-Reply-To: <20190904125531.27545-8-damien.hedde@greensocs.com>
On Wed, 4 Sep 2019 at 13:56, Damien Hedde <damien.hedde@greensocs.com> wrote:
>
> Switch the slcr to multi-phase reset and add some clocks:
> + the main input clock (ps_clk)
> + the reference clock outputs for each uart (uart0 & 1)
>
> The clock frequencies are computed using the internal pll & uart configuration
> registers and the ps_clk frequency.
>
> Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Review of this and the following two patches by some Xilinx
person would be nice. I've just looked them over for general
issues, and haven't checked against the hardware specs.
> ---
> +/*
> + * return the output frequency of a clock given:
> + * + the frequencies in an array corresponding to mux's indexes
> + * + the register xxx_CLK_CTRL value
> + * + enable bit index in ctrl register
> + *
> + * This function make the assumption that ctrl_reg value is organized as follow:
"makes"; "that the"; "follows"
> + * + bits[13:8] clock divisor
> + * + bits[5:4] clock mux selector (index in array)
> + * + bits[index] clock enable
> + */
> +static uint64_t zynq_slcr_compute_clock(const uint64_t mux[],
> + uint32_t ctrl_reg,
> + unsigned index)
> +{
> + uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */
> + uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */
> +
> + /* first, check if clock is enabled */
> + if (((ctrl_reg >> index) & 1u) == 0) {
> + return 0;
> + }
> +
> + /*
> + * according to the Zynq technical ref. manual UG585 v1.12.2 in
> + * "Clocks" chapter, section 25.10.1 page 705" the range of the divisor
> + * is [1;63].
Is this the range notation the spec doc uses?
> + * So divide the source while avoiding division-by-zero.
> + */
> + return mux[srcsel] / (divisor ? divisor : 1u);
> +}
> +
> +static const ClockPortInitArray zynq_slcr_clocks = {
> + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback),
> + QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk),
> + QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk),
> + QDEV_CLOCK_END
> +};
> +
> static void zynq_slcr_init(Object *obj)
> {
> ZynqSLCRState *s = ZYNQ_SLCR(obj);
> @@ -425,6 +559,8 @@ static void zynq_slcr_init(Object *obj)
> memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
> ZYNQ_SLCR_MMIO_SIZE);
> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
> +
> + qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks);
> }
>
> static const VMStateDescription vmstate_zynq_slcr = {
> @@ -440,9 +576,12 @@ static const VMStateDescription vmstate_zynq_slcr = {
> static void zynq_slcr_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
>
> dc->vmsd = &vmstate_zynq_slcr;
> - dc->reset = zynq_slcr_reset;
> + rc->phases.init = zynq_slcr_reset_init;
> + rc->phases.hold = zynq_slcr_reset_hold;
> + rc->phases.exit = zynq_slcr_reset_exit;
> }
We're adding an input clock, so doesn't the migration
state struct need to be updated to migrate it ?
thanks
-- PMM
next prev parent reply other threads:[~2019-12-02 15:21 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-04 12:55 [Qemu-devel] [PATCH v6 0/9] Clock framework API Damien Hedde
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 1/9] hw/core/clock: introduce clock objects Damien Hedde
2019-11-25 13:07 ` Philippe Mathieu-Daudé
2019-11-25 13:37 ` Philippe Mathieu-Daudé
2019-12-03 15:14 ` Damien Hedde
2019-12-02 13:42 ` Peter Maydell
2019-12-03 15:28 ` Damien Hedde
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 2/9] hw/core/clock-vmstate: define a vmstate entry for clock state Damien Hedde
2019-11-25 13:05 ` Philippe Mathieu-Daudé
2019-12-02 13:44 ` Peter Maydell
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 3/9] qdev: add clock input&output support to devices Damien Hedde
2019-11-25 13:30 ` Philippe Mathieu-Daudé
2019-12-03 15:35 ` Damien Hedde
2019-12-02 14:34 ` Peter Maydell
2019-12-04 9:05 ` Damien Hedde
2019-12-04 9:53 ` Philippe Mathieu-Daudé
2019-12-04 11:58 ` Damien Hedde
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 4/9] qdev-monitor: print the device's clock with info qtree Damien Hedde
2019-12-02 14:35 ` Peter Maydell
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 5/9] qdev-clock: introduce an init array to ease the device construction Damien Hedde
2019-12-02 15:13 ` Peter Maydell
2019-12-04 11:04 ` Damien Hedde
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 6/9] docs/clocks: add device's clock documentation Damien Hedde
2019-12-02 15:17 ` Peter Maydell
2019-12-04 12:11 ` Damien Hedde
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 7/9] hw/misc/zynq_slcr: add clock generation for uarts Damien Hedde
2019-12-02 15:20 ` Peter Maydell [this message]
2019-12-04 12:51 ` Damien Hedde
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 8/9] hw/char/cadence_uart: add clock support Damien Hedde
2019-12-02 15:24 ` Peter Maydell
2019-12-04 13:35 ` Damien Hedde
2019-09-04 12:55 ` [Qemu-devel] [PATCH v6 9/9] hw/arm/xilinx_zynq: connect uart clocks to slcr Damien Hedde
2019-12-02 15:34 ` Peter Maydell
2019-12-03 14:59 ` Damien Hedde
2019-12-03 15:29 ` Philippe Mathieu-Daudé
2019-12-02 16:15 ` [PATCH v6 0/9] Clock framework API Peter Maydell
2019-12-04 16:40 ` Damien Hedde
2019-12-04 20:34 ` Philippe Mathieu-Daudé
2019-12-05 9:36 ` Damien Hedde
2019-12-05 9:59 ` Philippe Mathieu-Daudé
2019-12-05 10:21 ` Dr. David Alan Gilbert
2019-12-05 10:44 ` Philippe Mathieu-Daudé
2019-12-05 10:56 ` Dr. David Alan Gilbert
2019-12-05 11:01 ` Philippe Mathieu-Daudé
2019-12-06 12:46 ` Cleber Rosa
2019-12-06 13:48 ` Dr. David Alan Gilbert
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAFEAcA_mmBeVnx5TsdeEaEU=jNnkFR9aa-nziaTQD7par7GpoA@mail.gmail.com' \
--to=peter.maydell@linaro.org \
--cc=alistair@alistair23.me \
--cc=berrange@redhat.com \
--cc=damien.hedde@greensocs.com \
--cc=edgar.iglesias@gmail.com \
--cc=ehabkost@redhat.com \
--cc=marcandre.lureau@redhat.com \
--cc=mark.burton@greensocs.com \
--cc=pbonzini@redhat.com \
--cc=philmd@redhat.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).