* [PATCH V6 0/4] mips: Add Loongson-3 machine support (with KVM)
@ 2020-06-24 10:45 Huacai Chen
2020-06-24 10:45 ` [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass Huacai Chen
` (3 more replies)
0 siblings, 4 replies; 14+ messages in thread
From: Huacai Chen @ 2020-06-24 10:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, in QEMU we just define two CPU types:
1, "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
suitable for TCG because Loongson-3A R1 has fewest ASE.
2, "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
suitable for KVM because Loongson-3A R4 has the VZ ASE.
Loongson-3 lacks English documents. I've tried to translated them with
translate.google.com, and the machine translated documents (together
with their original Chinese versions) are available here.
Loongson-3A R1 (Loongson-3A1000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A1000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P1.pdf (Chinese Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A1000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P2.pdf (Chinese Version)
Loongson-3A R2 (Loongson-3A2000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A2000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A2000_user1.pdf (Chinese Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A2000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A2000_user2.pdf (Chinese Version)
Loongson-3A R3 (Loongson-3A3000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A3000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual1.pdf (Chinese Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A3000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual2.pdf (Chinese Version)
Loongson-3A R4 (Loongson-3A4000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A4000_p1.pdf
http://ftp.godson.ac.cn/lemote/3A4000user.pdf (Chinese Version)
User Manual Part 2:
I'm sorry that it is unavailable now.
We are preparing to add QEMU's Loongson-3 support. MIPS VZ extension is
fully supported in Loongson-3A R4+, so we at first add QEMU/KVM support
in this series. And the next series will add QEMU/TCG support (it will
emulate Loongson-3A R1).
We already have a full functional Linux kernel (based on Linux-5.4.x LTS
but not upstream yet) here:
https://github.com/chenhuacai/linux
How to use QEMU/Loongson-3?
1, Download kernel source from the above URL;
2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
3, Boot a Loongson-3A4000 host with this kernel;
4, Build QEMU-5.0.0 with this patchset;
5, modprobe kvm;
6, Use QEMU with TCG (available in future):
qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ...
Use QEMU with KVM (available at present):
qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically.
V1 -> V2:
1, Add a cover letter;
2, Improve CPU definitions;
3, Remove LS7A-related things (Use GPEX instead);
4, Add a description of how to run QEMU/Loongson-3.
V2 -> V3:
1, Fix all possible checkpatch.pl errors and warnings.
V3 -> V4:
1, Sync code with upstream;
2, Remove merged patches;
3, Fix build failure without CONFIG_KVM;
4, Add Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>.
V4 -> V5:
1, Improve coding style;
2, Remove merged patches;
3, Rename machine name from "loongson3" to "loongson3-virt";
4, Rework the "loongson3-virt" machine to drop any ISA things;
5, Rework "hw/mips: Implement the kvm_type() hook in MachineClass";
6, Add Jiaxun Yang as a reviewer of Loongson-3.
V5 -> V6:
1, Fix license preamble;
2, Improve commit messages;
3, Add hw/intc/loongson_liointc.c to MAINTAINERS;
4, Fix all possible checkpatch.pl errors and warnings.
Huacai Chen(4):
hw/mips: Implement the kvm_type() hook in MachineClass
hw/intc: Add Loongson liointc support
hw/mips: Add Loongson-3 machine support (with KVM)
MAINTAINERS: Add Loongson-3 maintainer and reviewer
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
MAINTAINERS | 7 +
default-configs/mips64el-softmmu.mak | 1 +
hw/intc/Kconfig | 3 +
hw/intc/Makefile.objs | 1 +
hw/intc/loongson_liointc.c | 241 +++++++++
hw/mips/Kconfig | 11 +
hw/mips/Makefile.objs | 1 +
hw/mips/loongson3_virt.c | 978 +++++++++++++++++++++++++++++++++++
target/mips/kvm.c | 20 +
target/mips/kvm_mips.h | 11 +
10 files changed, 1274 insertions(+)
create mode 100644 hw/intc/loongson_liointc.c
create mode 100644 hw/mips/loongson3_virt.c
--
2.7.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass
2020-06-24 10:45 [PATCH V6 0/4] mips: Add Loongson-3 machine support (with KVM) Huacai Chen
@ 2020-06-24 10:45 ` Huacai Chen
2020-06-25 12:31 ` Aleksandar Markovic
2020-06-27 17:51 ` Aleksandar Markovic
2020-06-24 10:45 ` [PATCH V6 2/4] hw/intc: Add Loongson liointc support Huacai Chen
` (2 subsequent siblings)
3 siblings, 2 replies; 14+ messages in thread
From: Huacai Chen @ 2020-06-24 10:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we
can't create a VZ guest in QEMU because it lacks the kvm_type() hook in
MachineClass. This patch add the the kvm_type() hook to support both of
the two types.
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/kvm.c | 20 ++++++++++++++++++++
target/mips/kvm_mips.h | 11 +++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 96cfa10..373f582 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -21,10 +21,12 @@
#include "qemu/main-loop.h"
#include "qemu/timer.h"
#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
#include "sysemu/runstate.h"
#include "sysemu/cpus.h"
#include "kvm_mips.h"
#include "exec/memattrs.h"
+#include "hw/boards.h"
#define DEBUG_KVM 0
@@ -1270,3 +1272,21 @@ int kvm_arch_msi_data_to_gsi(uint32_t data)
{
abort();
}
+
+int mips_kvm_type(MachineState *machine, const char *vm_type)
+{
+ int r;
+ KVMState *s = KVM_STATE(machine->accelerator);
+
+ r = kvm_check_extension(s, KVM_CAP_MIPS_VZ);
+ if (r > 0) {
+ return KVM_VM_MIPS_VZ;
+ }
+
+ r = kvm_check_extension(s, KVM_CAP_MIPS_TE);
+ if (r > 0) {
+ return KVM_VM_MIPS_TE;
+ }
+
+ return -1;
+}
diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h
index 1e40147..171d53d 100644
--- a/target/mips/kvm_mips.h
+++ b/target/mips/kvm_mips.h
@@ -12,6 +12,8 @@
#ifndef KVM_MIPS_H
#define KVM_MIPS_H
+#include "cpu.h"
+
/**
* kvm_mips_reset_vcpu:
* @cpu: MIPSCPU
@@ -23,4 +25,13 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu);
int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level);
int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level);
+#ifdef CONFIG_KVM
+int mips_kvm_type(MachineState *machine, const char *vm_type);
+#else
+static inline int mips_kvm_type(MachineState *machine, const char *vm_type)
+{
+ return 0;
+}
+#endif
+
#endif /* KVM_MIPS_H */
--
2.7.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V6 2/4] hw/intc: Add Loongson liointc support
2020-06-24 10:45 [PATCH V6 0/4] mips: Add Loongson-3 machine support (with KVM) Huacai Chen
2020-06-24 10:45 ` [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass Huacai Chen
@ 2020-06-24 10:45 ` Huacai Chen
2020-06-25 10:35 ` Aleksandar Markovic
2020-06-27 17:54 ` Aleksandar Markovic
2020-06-24 10:45 ` [PATCH V6 3/4] hw/mips: Add Loongson-3 machine support (with KVM) Huacai Chen
2020-06-24 10:45 ` [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer Huacai Chen
3 siblings, 2 replies; 14+ messages in thread
From: Huacai Chen @ 2020-06-24 10:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Jiaxun Yang,
Huacai Chen, Aurelien Jarno
Loongson-3 has an integrated liointc (Local I/O interrupt controller).
It is similar to goldfish interrupt controller, but more powerful (e.g.,
it can route external interrupt to multi-cores).
Documents about Loongson-3's liointc:
1, https://wiki.godson.ac.cn/ip_block:liointc;
2, The "I/O中断" section of Loongson-3's user mannual, part 1.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
hw/intc/Kconfig | 3 +
hw/intc/Makefile.objs | 1 +
hw/intc/loongson_liointc.c | 241 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 245 insertions(+)
create mode 100644 hw/intc/loongson_liointc.c
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index f562342..2ae1e89 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -64,3 +64,6 @@ config OMPIC
config RX_ICU
bool
+
+config LOONGSON_LIOINTC
+ bool
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index a420263..3ac2b40 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -51,3 +51,4 @@ obj-$(CONFIG_MIPS_CPS) += mips_gic.o
obj-$(CONFIG_NIOS2) += nios2_iic.o
obj-$(CONFIG_OMPIC) += ompic.o
obj-$(CONFIG_IBEX) += ibex_plic.o
+obj-$(CONFIG_LOONGSON_LIOINTC) += loongson_liointc.o
diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c
new file mode 100644
index 0000000..e39e39e
--- /dev/null
+++ b/hw/intc/loongson_liointc.c
@@ -0,0 +1,241 @@
+/*
+ * QEMU Loongson Local I/O interrupt controler.
+ *
+ * Copyright (c) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/module.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+
+#define D(x)
+
+#define NUM_IRQS 32
+
+#define NUM_CORES 4
+#define NUM_IPS 4
+#define NUM_PARENTS (NUM_CORES * NUM_IPS)
+#define PARENT_COREx_IPy(x, y) (NUM_IPS * x + y)
+
+#define R_MAPPER_START 0x0
+#define R_MAPPER_END 0x20
+#define R_ISR R_MAPPER_END
+#define R_IEN 0x24
+#define R_IEN_SET 0x28
+#define R_IEN_CLR 0x2c
+#define R_PERCORE_ISR(x) (0x40 + 0x8 * x)
+#define R_END 0x64
+
+#define TYPE_LOONGSON_LIOINTC "loongson.liointc"
+#define LOONGSON_LIOINTC(obj) \
+ OBJECT_CHECK(struct loongson_liointc, (obj), TYPE_LOONGSON_LIOINTC)
+
+struct loongson_liointc {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+ qemu_irq parent_irq[NUM_PARENTS];
+
+ uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */
+ uint32_t isr;
+ uint32_t ien;
+ uint32_t per_core_isr[NUM_CORES];
+
+ /* state of the interrupt input pins */
+ uint32_t pin_state;
+ bool parent_state[NUM_PARENTS];
+};
+
+static void update_irq(struct loongson_liointc *p)
+{
+ uint32_t irq, core, ip;
+ uint32_t per_ip_isr[NUM_IPS] = {0};
+
+ /* level triggered interrupt */
+ p->isr = p->pin_state;
+
+ /* Clear disabled IRQs */
+ p->isr &= p->ien;
+
+ /* Clear per_core_isr */
+ for (core = 0; core < NUM_CORES; core++) {
+ p->per_core_isr[core] = 0;
+ }
+
+ /* Update per_core_isr and per_ip_isr */
+ for (irq = 0; irq < NUM_IRQS; irq++) {
+ if (!(p->isr & (1 << irq))) {
+ continue;
+ }
+
+ for (core = 0; core < NUM_CORES; core++) {
+ if ((p->mapper[irq] & (1 << core))) {
+ p->per_core_isr[core] |= (1 << irq);
+ }
+ }
+
+ for (ip = 0; ip < NUM_IPS; ip++) {
+ if ((p->mapper[irq] & (1 << (ip + 4)))) {
+ per_ip_isr[ip] |= (1 << irq);
+ }
+ }
+ }
+
+ /* Emit IRQ to parent! */
+ for (core = 0; core < NUM_CORES; core++) {
+ for (ip = 0; ip < NUM_IPS; ip++) {
+ int parent = PARENT_COREx_IPy(core, ip);
+ if (p->parent_state[parent] !=
+ (!!p->per_core_isr[core] && !!per_ip_isr[ip])) {
+ p->parent_state[parent] = !p->parent_state[parent];
+ qemu_set_irq(p->parent_irq[parent], p->parent_state[parent]);
+ }
+ }
+ }
+}
+
+static uint64_t
+liointc_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ struct loongson_liointc *p = opaque;
+ uint32_t r = 0;
+
+ /* Mapper is 1 byte */
+ if (size == 1 && addr < R_MAPPER_END) {
+ r = p->mapper[addr];
+ goto out;
+ }
+
+ /* Rest is 4 byte */
+ if (size != 4 || (addr % 4)) {
+ goto out;
+ }
+
+ if (addr >= R_PERCORE_ISR(0) &&
+ addr < R_PERCORE_ISR(NUM_CORES)) {
+ int core = (addr - R_PERCORE_ISR(0)) / 4;
+ r = p->per_core_isr[core];
+ goto out;
+ }
+
+ switch (addr) {
+ case R_ISR:
+ r = p->isr;
+ break;
+ case R_IEN:
+ r = p->ien;
+ break;
+ default:
+ break;
+ }
+
+out:
+ D(qemu_log("%s: size=%d addr=%lx val=%x\n", __func__, size, addr, r));
+ return r;
+}
+
+static void
+liointc_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ struct loongson_liointc *p = opaque;
+ uint32_t value = val64;
+
+ D(qemu_log("%s: size=%d, addr=%lx val=%x\n", __func__, size, addr, value));
+
+ /* Mapper is 1 byte */
+ if (size == 1 && addr < R_MAPPER_END) {
+ p->mapper[addr] = value;
+ goto out;
+ }
+
+ /* Rest is 4 byte */
+ if (size != 4 || (addr % 4)) {
+ goto out;
+ }
+
+ if (addr >= R_PERCORE_ISR(0) &&
+ addr < R_PERCORE_ISR(NUM_CORES)) {
+ int core = (addr - R_PERCORE_ISR(0)) / 4;
+ p->per_core_isr[core] = value;
+ goto out;
+ }
+
+ switch (addr) {
+ case R_IEN_SET:
+ p->ien |= value;
+ break;
+ case R_IEN_CLR:
+ p->ien &= ~value;
+ break;
+ default:
+ break;
+ }
+
+out:
+ update_irq(p);
+}
+
+static const MemoryRegionOps pic_ops = {
+ .read = liointc_read,
+ .write = liointc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ }
+};
+
+static void irq_handler(void *opaque, int irq, int level)
+{
+ struct loongson_liointc *p = opaque;
+
+ p->pin_state &= ~(1 << irq);
+ p->pin_state |= level << irq;
+ update_irq(p);
+}
+
+static void loongson_liointc_init(Object *obj)
+{
+ struct loongson_liointc *p = LOONGSON_LIOINTC(obj);
+ int i;
+
+ qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
+
+ for (i = 0; i < NUM_PARENTS; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq[i]);
+ }
+
+ memory_region_init_io(&p->mmio, obj, &pic_ops, p,
+ "loongson.liointc", R_END);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
+}
+
+static const TypeInfo loongson_liointc_info = {
+ .name = TYPE_LOONGSON_LIOINTC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct loongson_liointc),
+ .instance_init = loongson_liointc_init,
+};
+
+static void loongson_liointc_register_types(void)
+{
+ type_register_static(&loongson_liointc_info);
+}
+
+type_init(loongson_liointc_register_types)
--
2.7.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V6 3/4] hw/mips: Add Loongson-3 machine support (with KVM)
2020-06-24 10:45 [PATCH V6 0/4] mips: Add Loongson-3 machine support (with KVM) Huacai Chen
2020-06-24 10:45 ` [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass Huacai Chen
2020-06-24 10:45 ` [PATCH V6 2/4] hw/intc: Add Loongson liointc support Huacai Chen
@ 2020-06-24 10:45 ` Huacai Chen
2020-06-24 11:50 ` Aleksandar Markovic
2020-06-24 10:45 ` [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer Huacai Chen
3 siblings, 1 reply; 14+ messages in thread
From: Huacai Chen @ 2020-06-24 10:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
Add Loongson-3 based machine support, it use liointc as the interrupt
controler and use GPEX as the pci controller. Currently it can only work
with KVM, but we will add TCG support in future.
As the machine model is not based on any exiting physical hardware, the
name of the machine is "loongson3-virt". It may be superseded in future
by a real machine model. If this happens, then a regular deprecation
procedure shall occur for "loongson3-virt" machine.
We now already have a full functional Linux kernel (based on Linux-5.4.x
LTS, the kvm host side has been upstream in Linux-5.8, but the kvm guest
side has not been upstream yet) here:
https://github.com/chenhuacai/linux
How to use QEMU/Loongson-3?
1, Download kernel source from the above URL;
2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
3, Boot the a Loongson-3A4000 host with this kernel;
4, Build QEMU-master with this patchset;
5, modprobe kvm;
6, Use QEMU with TCG (available in future):
qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ...
Use QEMU with KVM (available at present):
qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
default-configs/mips64el-softmmu.mak | 1 +
hw/mips/Kconfig | 11 +
hw/mips/Makefile.objs | 1 +
hw/mips/loongson3_virt.c | 978 +++++++++++++++++++++++++++++++++++
4 files changed, 991 insertions(+)
create mode 100644 hw/mips/loongson3_virt.c
diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
index 9f8a3ef..26c660a 100644
--- a/default-configs/mips64el-softmmu.mak
+++ b/default-configs/mips64el-softmmu.mak
@@ -3,6 +3,7 @@
include mips-softmmu-common.mak
CONFIG_IDE_VIA=y
CONFIG_FULOONG=y
+CONFIG_LOONGSON3V=y
CONFIG_ATI_VGA=y
CONFIG_RTL8139_PCI=y
CONFIG_JAZZ=y
diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index 67d39c5..cc5609b 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -45,6 +45,17 @@ config FULOONG
bool
select PCI_BONITO
+config LOONGSON3V
+ bool
+ select PCKBD
+ select SERIAL
+ select GOLDFISH_RTC
+ select LOONGSON_LIOINTC
+ select PCI_EXPRESS_GENERIC_BRIDGE
+ select VIRTIO_VGA
+ select QXL if SPICE
+ select MSI_NONBROKEN
+
config MIPS_CPS
bool
select PTIMER
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 739e2b7..0993852 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -4,5 +4,6 @@ obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o
obj-$(CONFIG_MIPSSIM) += mipssim.o
obj-$(CONFIG_JAZZ) += jazz.o
obj-$(CONFIG_FULOONG) += fuloong2e.o
+obj-$(CONFIG_LOONGSON3V) += loongson3_virt.o
obj-$(CONFIG_MIPS_CPS) += cps.o
obj-$(CONFIG_MIPS_BOSTON) += boston.o
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
new file mode 100644
index 0000000..e0e1939
--- /dev/null
+++ b/hw/mips/loongson3_virt.c
@@ -0,0 +1,978 @@
+/*
+ * Generic Loongson-3 Platform support
+ *
+ * Copyright (c) 2016-2020 Huacai Chen (chenhc@lemote.com)
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
+ * extensions, 800~2000MHz)
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "elf.h"
+#include "kvm_mips.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/mips/mips.h"
+#include "hw/mips/cpudevs.h"
+#include "hw/misc/empty_slot.h"
+#include "hw/intc/i8259.h"
+#include "hw/loader.h"
+#include "hw/isa/superio.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb.h"
+#include "net/net.h"
+#include "exec/address-spaces.h"
+#include "sysemu/kvm.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+
+#define PM_CNTL_MODE 0x10
+
+/* Overall MMIO & Memory layout */
+enum {
+ VIRT_LOWMEM,
+ VIRT_PM,
+ VIRT_FW_CFG,
+ VIRT_RTC,
+ VIRT_PCIE_PIO,
+ VIRT_PCIE_ECAM,
+ VIRT_BIOS_ROM,
+ VIRT_UART,
+ VIRT_LIOINTC,
+ VIRT_PCIE_MMIO,
+ VIRT_HIGHMEM
+};
+
+/* Low MEM layout for QEMU kernel loader */
+enum {
+ LOADER_KERNEL,
+ LOADER_INITRD,
+ LOADER_CMDLINE
+};
+
+/* BIOS ROM layout for QEMU kernel loader */
+enum {
+ LOADER_BOOTROM,
+ LOADER_PARAM,
+};
+
+struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+};
+
+/* Data for BIOS to identify machine */
+#define FW_CFG_MACHINE_VERSION (FW_CFG_ARCH_LOCAL + 0)
+#define FW_CFG_CPU_FREQ (FW_CFG_ARCH_LOCAL + 1)
+
+/*
+ * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structrues
+ * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux kernel
+ */
+struct efi_memory_map_loongson {
+ uint16_t vers; /* version of efi_memory_map */
+ uint32_t nr_map; /* number of memory_maps */
+ uint32_t mem_freq; /* memory frequence */
+ struct mem_map {
+ uint32_t node_id; /* node_id which memory attached to */
+ uint32_t mem_type; /* system memory, pci memory, pci io, etc. */
+ uint64_t mem_start; /* memory map start address */
+ uint32_t mem_size; /* each memory_map size, not the total size */
+ } map[128];
+} __attribute__((packed));
+
+enum loongson_cpu_type {
+ Legacy_2E = 0x0,
+ Legacy_2F = 0x1,
+ Legacy_3A = 0x2,
+ Legacy_3B = 0x3,
+ Legacy_1A = 0x4,
+ Legacy_1B = 0x5,
+ Legacy_2G = 0x6,
+ Legacy_2H = 0x7,
+ Loongson_1A = 0x100,
+ Loongson_1B = 0x101,
+ Loongson_2E = 0x200,
+ Loongson_2F = 0x201,
+ Loongson_2G = 0x202,
+ Loongson_2H = 0x203,
+ Loongson_3A = 0x300,
+ Loongson_3B = 0x301
+};
+
+/*
+ * Capability and feature descriptor structure for MIPS CPU
+ */
+struct efi_cpuinfo_loongson {
+ uint16_t vers; /* version of efi_cpuinfo_loongson */
+ uint32_t processor_id; /* PRID, e.g. 6305, 6306 */
+ uint32_t cputype; /* Loongson_3A/3B, etc. */
+ uint32_t total_node; /* num of total numa nodes */
+ uint16_t cpu_startup_core_id; /* Boot core id */
+ uint16_t reserved_cores_mask;
+ uint32_t cpu_clock_freq; /* cpu_clock */
+ uint32_t nr_cpus;
+ char cpuname[64];
+} __attribute__((packed));
+
+#define MAX_UARTS 64
+struct uart_device {
+ uint32_t iotype;
+ uint32_t uartclk;
+ uint32_t int_offset;
+ uint64_t uart_base;
+} __attribute__((packed));
+
+#define MAX_SENSORS 64
+#define SENSOR_TEMPER 0x00000001
+#define SENSOR_VOLTAGE 0x00000002
+#define SENSOR_FAN 0x00000004
+struct sensor_device {
+ char name[32]; /* a formal name */
+ char label[64]; /* a flexible description */
+ uint32_t type; /* SENSOR_* */
+ uint32_t id; /* instance id of a sensor-class */
+ uint32_t fan_policy; /* step speed or constant speed */
+ uint32_t fan_percent;/* only for constant speed policy */
+ uint64_t base_addr; /* base address of device registers */
+} __attribute__((packed));
+
+struct system_loongson {
+ uint16_t vers; /* version of system_loongson */
+ uint32_t ccnuma_smp; /* 0: no numa; 1: has numa */
+ uint32_t sing_double_channel;/* 1: single; 2: double */
+ uint32_t nr_uarts;
+ struct uart_device uarts[MAX_UARTS];
+ uint32_t nr_sensors;
+ struct sensor_device sensors[MAX_SENSORS];
+ char has_ec;
+ char ec_name[32];
+ uint64_t ec_base_addr;
+ char has_tcm;
+ char tcm_name[32];
+ uint64_t tcm_base_addr;
+ uint64_t workarounds;
+ uint64_t of_dtb_addr; /* NULL if not support */
+} __attribute__((packed));
+
+struct irq_source_routing_table {
+ uint16_t vers;
+ uint16_t size;
+ uint16_t rtr_bus;
+ uint16_t rtr_devfn;
+ uint32_t vendor;
+ uint32_t device;
+ uint32_t PIC_type; /* conform use HT or PCI to route to CPU-PIC */
+ uint64_t ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
+ uint64_t ht_enable; /* irqs used in this PIC */
+ uint32_t node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
+ uint64_t pci_mem_start_addr;
+ uint64_t pci_mem_end_addr;
+ uint64_t pci_io_start_addr;
+ uint64_t pci_io_end_addr;
+ uint64_t pci_config_addr;
+ uint16_t dma_mask_bits;
+ uint16_t dma_noncoherent;
+} __attribute__((packed));
+
+struct interface_info {
+ uint16_t vers; /* version of the specificition */
+ uint16_t size;
+ uint8_t flag;
+ char description[64];
+} __attribute__((packed));
+
+#define MAX_RESOURCE_NUMBER 128
+struct resource_loongson {
+ uint64_t start; /* resource start address */
+ uint64_t end; /* resource end address */
+ char name[64];
+ uint32_t flags;
+};
+
+struct archdev_data {}; /* arch specific additions */
+
+struct board_devices {
+ char name[64]; /* hold the device name */
+ uint32_t num_resources; /* number of device_resource */
+ /* for each device's resource */
+ struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+ /* arch specific additions */
+ struct archdev_data archdata;
+};
+
+struct loongson_special_attribute {
+ uint16_t vers; /* version of this special */
+ char special_name[64]; /* special_atribute_name */
+ uint32_t loongson_special_type; /* type of special device */
+ /* for each device's resource */
+ struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+};
+
+struct loongson_params {
+ uint64_t memory_offset; /* efi_memory_map_loongson struct offset */
+ uint64_t cpu_offset; /* efi_cpuinfo_loongson struct offset */
+ uint64_t system_offset; /* system_loongson struct offset */
+ uint64_t irq_offset; /* irq_source_routing_table struct offset */
+ uint64_t interface_offset; /* interface_info struct offset */
+ uint64_t special_offset; /* loongson_special_attribute struct offset */
+ uint64_t boarddev_table_offset; /* board_devices offset */
+};
+
+struct smbios_tables {
+ uint16_t vers; /* version of smbios */
+ uint64_t vga_bios; /* vga_bios address */
+ struct loongson_params lp;
+};
+
+struct efi_reset_system_t {
+ uint64_t ResetCold;
+ uint64_t ResetWarm;
+ uint64_t ResetType;
+ uint64_t Shutdown;
+ uint64_t DoSuspend; /* NULL if not support */
+};
+
+struct efi_loongson {
+ uint64_t mps; /* MPS table */
+ uint64_t acpi; /* ACPI table (IA64 ext 0.71) */
+ uint64_t acpi20; /* ACPI table (ACPI 2.0) */
+ struct smbios_tables smbios; /* SM BIOS table */
+ uint64_t sal_systab; /* SAL system table */
+ uint64_t boot_info; /* boot info table */
+};
+
+struct boot_params {
+ struct efi_loongson efi;
+ struct efi_reset_system_t reset_system;
+};
+
+#define LOONGSON_MAX_VCPUS 16
+
+#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
+
+#define UART_IRQ 0
+#define RTC_IRQ 1
+#define PCIE_IRQ_BASE 2
+
+#define align(x) (((x) + 63) & ~63)
+
+static const struct MemmapEntry virt_memmap[] = {
+ [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
+ [VIRT_PM] = { 0x10080000, 0x100 },
+ [VIRT_FW_CFG] = { 0x10080100, 0x100 },
+ [VIRT_RTC] = { 0x10081000, 0x1000 },
+ [VIRT_PCIE_PIO] = { 0x18000000, 0xc0000 },
+ [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
+ [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
+ [VIRT_UART] = { 0x1fe001e0, 0x8 },
+ [VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
+ [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
+ [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
+};
+
+static const struct MemmapEntry loader_memmap[] = {
+ [LOADER_KERNEL] = { 0x00000000, 0x4000000 },
+ [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */
+ [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 },
+};
+
+static const struct MemmapEntry loader_rommap[] = {
+ [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 },
+ [LOADER_PARAM] = { 0x1fc01000, 0x10000 },
+};
+
+static struct _loaderparams {
+ uint64_t ram_size;
+ const char *kernel_cmdline;
+ const char *kernel_filename;
+ const char *initrd_filename;
+ uint64_t kernel_entry;
+ uint64_t a0, a1, a2;
+} loaderparams;
+
+static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return 0;
+}
+
+static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+ if (addr != PM_CNTL_MODE) {
+ return;
+ }
+
+ switch (val) {
+ case 0x00:
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
+ case 0xff:
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ return;
+ default:
+ return;
+ }
+}
+
+static const MemoryRegionOps loongson3_pm_ops = {
+ .read = loongson3_pm_read,
+ .write = loongson3_pm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static struct efi_memory_map_loongson *init_memory_map(void *g_map)
+{
+ struct efi_memory_map_loongson *emap = g_map;
+
+ emap->nr_map = 2;
+ emap->mem_freq = 300000000;
+
+ emap->map[0].node_id = 0;
+ emap->map[0].mem_type = 1;
+ emap->map[0].mem_start = 0x0;
+ emap->map[0].mem_size = (loaderparams.ram_size > 0x10000000
+ ? 256 : (loaderparams.ram_size >> 20)) - 16;
+
+ emap->map[1].node_id = 0;
+ emap->map[1].mem_type = 2;
+ emap->map[1].mem_start = 0x90000000;
+ emap->map[1].mem_size = (loaderparams.ram_size > 0x10000000
+ ? (loaderparams.ram_size >> 20) - 256 : 0);
+
+ return emap;
+}
+
+#define BUFLEN 1024
+
+static uint32_t get_cpu_freq(void)
+{
+ int fd = 0, freq = 0;
+ char buf[BUFLEN], *buf_p;
+
+ fd = open("/proc/cpuinfo", O_RDONLY);
+ if (fd == -1) {
+ fprintf(stderr, "Failed to open /proc/cpuinfo!\n");
+ return 0;
+ }
+
+ if (read(fd, buf, BUFLEN) < 0) {
+ close(fd);
+ fprintf(stderr, "Failed to read /proc/cpuinfo!\n");
+ return 0;
+ }
+ close(fd);
+
+ buf_p = strstr(buf, "model name");
+ while (*buf_p != '@') {
+ buf_p++;
+ }
+
+ buf_p += 2;
+ memcpy(buf, buf_p, 12);
+ buf_p = buf;
+ while ((*buf_p >= '0') && (*buf_p <= '9')) {
+ buf_p++;
+ }
+ *buf_p = '\0';
+
+ freq = atoi(buf);
+
+ return freq * 1000 * 1000;
+}
+
+static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo_loongson)
+{
+ struct efi_cpuinfo_loongson *c = g_cpuinfo_loongson;
+
+ c->cputype = Loongson_3A;
+ c->processor_id = MIPS_CPU(first_cpu)->env.CP0_PRid;
+ c->cpu_clock_freq = get_cpu_freq();
+ if (!c->cpu_clock_freq) {
+ c->cpu_clock_freq = 500000000;
+ }
+
+ c->cpu_startup_core_id = 0;
+ c->nr_cpus = current_machine->smp.cpus;
+ c->total_node = (current_machine->smp.cpus + 3) / 4;
+
+ return c;
+}
+
+static struct system_loongson *init_system_loongson(void *g_system)
+{
+ struct system_loongson *s = g_system;
+
+ s->ccnuma_smp = 0;
+ s->sing_double_channel = 1;
+ s->nr_uarts = 1;
+ s->uarts[0].iotype = 2;
+ s->uarts[0].int_offset = 2;
+ s->uarts[0].uartclk = 25000000; /* Random value */
+ s->uarts[0].uart_base = virt_memmap[VIRT_UART].base;
+
+ return s;
+}
+
+static struct irq_source_routing_table *init_irq_source(void *g_irq_source)
+{
+ struct irq_source_routing_table *irq_info = g_irq_source;
+
+ irq_info->node_id = 0;
+ irq_info->PIC_type = 0;
+ irq_info->dma_mask_bits = 64;
+ irq_info->pci_mem_start_addr = virt_memmap[VIRT_PCIE_MMIO].base;
+ irq_info->pci_mem_end_addr = virt_memmap[VIRT_PCIE_MMIO].base +
+ virt_memmap[VIRT_PCIE_MMIO].size - 1;
+ irq_info->pci_io_start_addr = virt_memmap[VIRT_PCIE_PIO].base;
+
+ return irq_info;
+}
+
+static struct interface_info *init_interface_info(void *g_interface)
+{
+ struct interface_info *interface = g_interface;
+
+ interface->vers = 0x01;
+ strcpy(interface->description, "UEFI_Version_v1.0");
+
+ return interface;
+}
+
+static struct board_devices *board_devices_info(void *g_board)
+{
+ struct board_devices *bd = g_board;
+
+ strcpy(bd->name, "Loongson-3A-VIRT-1w-V1.00-demo");
+
+ return bd;
+}
+
+static struct loongson_special_attribute *init_special_info(void *g_special)
+{
+ struct loongson_special_attribute *special = g_special;
+
+ strcpy(special->special_name, "2016-08-01");
+
+ return special;
+}
+
+static void init_loongson_params(struct loongson_params *lp, void *p)
+{
+ lp->memory_offset = (unsigned long long)init_memory_map(p)
+ - (unsigned long long)lp;
+ p += align(sizeof(struct efi_memory_map_loongson));
+
+ lp->cpu_offset = (unsigned long long)init_cpu_info(p)
+ - (unsigned long long)lp;
+ p += align(sizeof(struct efi_cpuinfo_loongson));
+
+ lp->system_offset = (unsigned long long)init_system_loongson(p)
+ - (unsigned long long)lp;
+ p += align(sizeof(struct system_loongson));
+
+ lp->irq_offset = (unsigned long long)init_irq_source(p)
+ - (unsigned long long)lp;
+ p += align(sizeof(struct irq_source_routing_table));
+
+ lp->interface_offset = (unsigned long long)init_interface_info(p)
+ - (unsigned long long)lp;
+ p += align(sizeof(struct interface_info));
+
+ lp->boarddev_table_offset = (unsigned long long)board_devices_info(p)
+ - (unsigned long long)lp;
+ p += align(sizeof(struct board_devices));
+
+ lp->special_offset = (unsigned long long)init_special_info(p)
+ - (unsigned long long)lp;
+ p += align(sizeof(struct loongson_special_attribute));
+}
+
+static void init_reset_system(struct efi_reset_system_t *reset)
+{
+ reset->Shutdown = 0xffffffffbfc000a8;
+ reset->ResetCold = 0xffffffffbfc00080;
+ reset->ResetWarm = 0xffffffffbfc00080;
+}
+
+static void init_boot_param(void)
+{
+ void *p;
+ struct boot_params *bp;
+
+ p = g_malloc0(loader_rommap[LOADER_PARAM].size);
+ bp = p;
+
+ bp->efi.smbios.vers = 1;
+ init_reset_system(&(bp->reset_system));
+ p += align(sizeof(struct boot_params));
+ init_loongson_params(&(bp->efi.smbios.lp), p);
+
+ rom_add_blob_fixed("params_rom", bp,
+ loader_rommap[LOADER_PARAM].size,
+ loader_rommap[LOADER_PARAM].base);
+
+ g_free(bp);
+
+ loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL,
+ loader_rommap[LOADER_PARAM].base);
+}
+
+static void init_boot_rom(void)
+{
+ const unsigned int boot_code[] = {
+ 0x40086000, /* mfc0 t0, CP0_STATUS */
+ 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */
+ 0x01094025, /* or t0, t0, t1 */
+ 0x3C090040, /* lui t1, 0x40 #set bev */
+ 0x01094025, /* or t0, t0, t1 */
+ 0x40886000, /* mtc0 t0, CP0_STATUS */
+ 0x00000000,
+ 0x40806800, /* mtc0 zero, CP0_CAUSE */
+ 0x00000000,
+ 0x400A7801, /* mfc0 t2, $15, 1 */
+ 0x314A00FF, /* andi t2, 0x0ff */
+ 0x3C089000, /* dli t0, 0x900000003ff01000 */
+ 0x00084438,
+ 0x35083FF0,
+ 0x00084438,
+ 0x35081000,
+ 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */
+ 0x000B5A00, /* sll t3, 8 */
+ 0x010B4025, /* or t0, t0, t3 */
+ 0x314C000C, /* andi t4, t2, 0xc #node id */
+ 0x000C62BC, /* dsll t4, 42 */
+ 0x010C4025, /* or t0, t0, t4 */
+ /* WaitForInit: */
+ 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */
+ 0x1040FFFE, /* beqz v0, WaitForInit */
+ 0x00000000, /* nop */
+ 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */
+ 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */
+ 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */
+ 0x00400008, /* jr v0 #byebye */
+ 0x00000000, /* nop */
+ 0x1000FFFF, /* 1: b 1b */
+ 0x00000000, /* nop */
+
+ /* Reset */
+ 0x3C0C9000, /* dli t0, 0x9000000010080010 */
+ 0x358C0000,
+ 0x000C6438,
+ 0x358C1008,
+ 0x000C6438,
+ 0x358C0010,
+ 0x240D0000, /* li t1, 0x00 */
+ 0xA18D0000, /* sb t1, (t0) */
+ 0x1000FFFF, /* 1: b 1b */
+ 0x00000000, /* nop */
+
+ /* Shutdown */
+ 0x3C0C9000, /* dli t0, 0x9000000010080010 */
+ 0x358C0000,
+ 0x000C6438,
+ 0x358C1008,
+ 0x000C6438,
+ 0x358C0010,
+ 0x240D00FF, /* li t1, 0xff */
+ 0xA18D0000, /* sb t1, (t0) */
+ 0x1000FFFF, /* 1: b 1b */
+ 0x00000000 /* nop */
+ };
+
+ rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
+ loader_rommap[LOADER_BOOTROM].base);
+}
+
+static void fw_cfg_boot_set(void *opaque, const char *boot_device,
+ Error **errp)
+{
+ fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
+}
+
+static void fw_conf_init(unsigned long ram_size)
+{
+ FWCfgState *fw_cfg;
+ hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
+
+ fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq());
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
+}
+
+static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
+{
+ hwaddr cmdline_vaddr;
+ char memenv[32];
+ char highmemenv[32];
+ void *cmdline_buf;
+ unsigned int *parg_env;
+ int ret = 0;
+
+ /* Allocate cmdline_buf for command line. */
+ cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
+ cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
+ loader_memmap[LOADER_CMDLINE].base);
+
+ /*
+ * Layout of cmdline_buf looks like this:
+ * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
+ * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
+ */
+ parg_env = (void *)cmdline_buf;
+
+ ret = (3 + 1) * 4;
+ *parg_env++ = cmdline_vaddr + ret;
+ ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
+
+ /* argv1 */
+ *parg_env++ = cmdline_vaddr + ret;
+ if (initrd_size > 0)
+ ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
+ "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
+ cpu_mips_phys_to_kseg0(NULL, initrd_offset),
+ initrd_size, loaderparams.kernel_cmdline));
+ else
+ ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
+ loaderparams.kernel_cmdline));
+
+ /* argv2 */
+ *parg_env++ = cmdline_vaddr + 4 * ret;
+
+ /* env */
+ sprintf(memenv, "%ld", loaderparams.ram_size > 0x10000000
+ ? 256 : (loaderparams.ram_size >> 20));
+ sprintf(highmemenv, "%ld", loaderparams.ram_size > 0x10000000
+ ? (loaderparams.ram_size >> 20) - 256 : 0);
+
+ rom_add_blob_fixed("cmdline", cmdline_buf,
+ loader_memmap[LOADER_CMDLINE].size,
+ loader_memmap[LOADER_CMDLINE].base);
+
+ g_free(cmdline_buf);
+
+ loaderparams.a0 = 2;
+ loaderparams.a1 = cmdline_vaddr;
+
+ return 0;
+}
+
+static uint64_t load_kernel(CPUMIPSState *env)
+{
+ long kernel_size;
+ ram_addr_t initrd_offset;
+ uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
+
+ kernel_size = load_elf(loaderparams.kernel_filename, NULL,
+ cpu_mips_kseg0_to_phys, NULL,
+ (uint64_t *)&kernel_entry,
+ (uint64_t *)&kernel_low, (uint64_t *)&kernel_high,
+ NULL, 0, EM_MIPS, 1, 0);
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s': %s",
+ loaderparams.kernel_filename,
+ load_elf_strerror(kernel_size));
+ exit(1);
+ }
+
+ /* load initrd */
+ initrd_size = 0;
+ initrd_offset = 0;
+ if (loaderparams.initrd_filename) {
+ initrd_size = get_image_size(loaderparams.initrd_filename);
+ if (initrd_size > 0) {
+ initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
+ INITRD_PAGE_MASK;
+ initrd_offset = MAX(initrd_offset,
+ loader_memmap[LOADER_INITRD].base);
+
+ if (initrd_offset + initrd_size > ram_size) {
+ error_report("memory too small for initial ram disk '%s'",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+
+ initrd_size = load_image_targphys(loaderparams.initrd_filename,
+ initrd_offset,
+ ram_size - initrd_offset);
+ }
+
+ if (initrd_size == (target_ulong) -1) {
+ error_report("could not load initial ram disk '%s'",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+ }
+
+ /* Setup prom cmdline. */
+ set_prom_cmdline(initrd_offset, initrd_size);
+
+ return kernel_entry;
+}
+
+static void main_cpu_reset(void *opaque)
+{
+ MIPSCPU *cpu = opaque;
+ CPUMIPSState *env = &cpu->env;
+
+ cpu_reset(CPU(cpu));
+
+ /* Loongson-3 reset stuff */
+ if (loaderparams.kernel_filename) {
+ if (cpu == MIPS_CPU(first_cpu)) {
+ env->active_tc.gpr[4] = loaderparams.a0;
+ env->active_tc.gpr[5] = loaderparams.a1;
+ env->active_tc.gpr[6] = loaderparams.a2;
+ env->active_tc.PC = loaderparams.kernel_entry;
+ }
+ env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
+ }
+}
+
+static inline void loongson3_virt_devices_init(MachineState *machine, DeviceState *pic)
+{
+ int i;
+ qemu_irq irq;
+ PCIBus *pci_bus;
+ DeviceState *dev;
+ MemoryRegion *pio_alias;
+ MemoryRegion *mmio_alias, *mmio_reg;
+ MemoryRegion *ecam_alias, *ecam_reg;
+
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+ ecam_alias = g_new0(MemoryRegion, 1);
+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
+ ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
+ memory_region_add_subregion(get_system_memory(),
+ virt_memmap[VIRT_PCIE_ECAM].base, ecam_alias);
+
+ mmio_alias = g_new0(MemoryRegion, 1);
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
+ mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
+ virt_memmap[VIRT_PCIE_MMIO].size);
+ memory_region_add_subregion(get_system_memory(),
+ virt_memmap[VIRT_PCIE_MMIO].base, mmio_alias);
+
+ pio_alias = g_new0(MemoryRegion, 1);
+ memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
+ get_system_io(), 0, virt_memmap[VIRT_PCIE_PIO].size);
+ memory_region_add_subregion(get_system_memory(),
+ virt_memmap[VIRT_PCIE_PIO].base, pio_alias);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
+
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
+ gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
+ }
+
+ pci_vga_init(pci_bus);
+
+ if (defaults_enabled()) {
+ pci_create_simple(pci_bus, -1, "pci-ohci");
+ usb_create_simple(usb_bus_find(-1), "usb-kbd");
+ usb_create_simple(usb_bus_find(-1), "usb-tablet");
+ }
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
+}
+
+static void mips_loongson3_virt_init(MachineState *machine)
+{
+ int i;
+ long bios_size;
+ MIPSCPU *cpu;
+ CPUMIPSState *env;
+ DeviceState *liointc;
+ char *filename;
+ const char *kernel_cmdline = machine->kernel_cmdline;
+ const char *kernel_filename = machine->kernel_filename;
+ const char *initrd_filename = machine->initrd_filename;
+ ram_addr_t ram_size = machine->ram_size;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
+
+ /* TODO: TCG will support all CPU types */
+ if (!kvm_enabled()) {
+ if (!machine->cpu_type) {
+ machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
+ }
+ if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
+ error_report("Loongson-3/TCG need cpu type Loongson-3A1000");
+ exit(1);
+ }
+ } else {
+ if (!machine->cpu_type) {
+ machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
+ }
+ if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
+ error_report("Loongson-3/KVM need cpu type Loongson-3A4000");
+ exit(1);
+ }
+ }
+
+ if (ram_size < 512 * 0x100000) {
+ error_report("Loongson-3 need at least 512MB memory");
+ exit(1);
+ }
+
+ /*
+ * The whole MMIO range among configure registers doesn't generate
+ * exception when accessing invalid memory. Create an empty slot to
+ * emulate this feature.
+ */
+ empty_slot_init("fallback", 0, 0x80000000);
+
+ liointc = qdev_new("loongson.liointc");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
+
+ for (i = 0; i < machine->smp.cpus; i++) {
+ int ip;
+
+ /* init CPUs */
+ cpu = MIPS_CPU(cpu_create(machine->cpu_type));
+
+ /* Init internal devices */
+ cpu_mips_irq_init_cpu(cpu);
+ cpu_mips_clock_init(cpu);
+ qemu_register_reset(main_cpu_reset, cpu);
+
+ if (i >= 4) {
+ continue; /* Only node-0 can be connected to LIOINTC */
+ }
+
+ for (ip = 0; ip < 4 ; ip++) {
+ int pin = i * 4 + ip;
+ sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
+ pin, cpu->env.irq[ip + 2]);
+ }
+ }
+ env = &MIPS_CPU(first_cpu)->env;
+
+ /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
+ memory_region_init_rom(bios, NULL, "loongson3.bios",
+ virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
+ memory_region_init_alias(ram, NULL, "loongson3.lowmem",
+ machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
+ memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
+ NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
+
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_LOWMEM].base, ram);
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_BIOS_ROM].base, bios);
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_HIGHMEM].base, machine->ram);
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_PM].base, iomem);
+
+ /*
+ * We do not support flash operation, just loading bios.bin as raw BIOS.
+ * Please use -L to set the BIOS path and -bios to set bios name.
+ */
+
+ if (kernel_filename) {
+ loaderparams.ram_size = ram_size;
+ loaderparams.kernel_filename = kernel_filename;
+ loaderparams.kernel_cmdline = kernel_cmdline;
+ loaderparams.initrd_filename = initrd_filename;
+ loaderparams.kernel_entry = load_kernel(env);
+
+ init_boot_rom();
+ init_boot_param();
+ } else {
+ if (bios_name == NULL) {
+ bios_name = LOONGSON3_BIOSNAME;
+ }
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ bios_size = load_image_targphys(filename,
+ virt_memmap[VIRT_BIOS_ROM].base,
+ virt_memmap[VIRT_BIOS_ROM].size);
+ g_free(filename);
+ } else {
+ bios_size = -1;
+ }
+
+ if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
+ !kernel_filename && !qtest_enabled()) {
+ error_report("Could not load MIPS bios '%s'", bios_name);
+ exit(1);
+ }
+
+ fw_conf_init(ram_size);
+ }
+
+ msi_nonbroken = true;
+ loongson3_virt_devices_init(machine, liointc);
+
+ sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
+ qdev_get_gpio_in(liointc, RTC_IRQ));
+
+ if (serial_hd(0)) {
+ serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
+ qdev_get_gpio_in(liointc, UART_IRQ), 115200,
+ serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ }
+}
+
+static void mips_loongson3_virt_machine_init(MachineClass *mc)
+{
+ mc->desc = "Loongson-3 Virtualization Platform";
+ mc->init = mips_loongson3_virt_init;
+ mc->block_default_type = IF_IDE;
+ mc->max_cpus = LOONGSON_MAX_VCPUS;
+ mc->default_ram_id = "loongson3.highram";
+ /* 1500MB is the requirement of distros for Loongson-3 */
+ mc->default_ram_size = 1500 * MiB;
+ mc->kvm_type = mips_kvm_type;
+ mc->minimum_page_bits = 14;
+}
+
+DEFINE_MACHINE("loongson3-virt", mips_loongson3_virt_machine_init)
--
2.7.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer
2020-06-24 10:45 [PATCH V6 0/4] mips: Add Loongson-3 machine support (with KVM) Huacai Chen
` (2 preceding siblings ...)
2020-06-24 10:45 ` [PATCH V6 3/4] hw/mips: Add Loongson-3 machine support (with KVM) Huacai Chen
@ 2020-06-24 10:45 ` Huacai Chen
2020-06-25 10:41 ` Aleksandar Markovic
2020-06-27 17:53 ` Aleksandar Markovic
3 siblings, 2 replies; 14+ messages in thread
From: Huacai Chen @ 2020-06-24 10:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
Add myself as a maintainer of Loongson-3 virtual platform, and also add
Jiaxun Yang as a reviewer.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 51a4570..0226a74 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1095,6 +1095,13 @@ F: hw/isa/vt82c686.c
F: hw/pci-host/bonito.c
F: include/hw/isa/vt82c686.h
+Loongson-3 Virtual Platform
+M: Huacai Chen <chenhc@lemote.com>
+R: Jiaxun Yang <jiaxun.yang@flygoat.com>
+S: Maintained
+F: hw/mips/loongson3_virt.c
+F: hw/intc/loongson_liointc.c
+
Boston
M: Paul Burton <pburton@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
--
2.7.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH V6 3/4] hw/mips: Add Loongson-3 machine support (with KVM)
2020-06-24 10:45 ` [PATCH V6 3/4] hw/mips: Add Loongson-3 machine support (with KVM) Huacai Chen
@ 2020-06-24 11:50 ` Aleksandar Markovic
2020-06-26 11:30 ` Huacai Chen
0 siblings, 1 reply; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-24 11:50 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
QEMU Developers, Huacai Chen, Aurelien Jarno
сре, 24. јун 2020. у 12:45 Huacai Chen <zltjiangshi@gmail.com> је написао/ла:
>
> Add Loongson-3 based machine support, it use liointc as the interrupt
> controler and use GPEX as the pci controller. Currently it can only work
> with KVM, but we will add TCG support in future.
>
> As the machine model is not based on any exiting physical hardware, the
> name of the machine is "loongson3-virt". It may be superseded in future
> by a real machine model. If this happens, then a regular deprecation
> procedure shall occur for "loongson3-virt" machine.
>
> We now already have a full functional Linux kernel (based on Linux-5.4.x
> LTS, the kvm host side has been upstream in Linux-5.8, but the kvm guest
> side has not been upstream yet) here:
>
Hi, Huacai,
Can you please enumerate here links to all patches in your kernel
repository that are not yet upstreamed, but are necessary for the
scenario below to work?
Thanks,
Aleksandar
> https://github.com/chenhuacai/linux
>
> How to use QEMU/Loongson-3?
> 1, Download kernel source from the above URL;
> 2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
> 3, Boot the a Loongson-3A4000 host with this kernel;
> 4, Build QEMU-master with this patchset;
> 5, modprobe kvm;
> 6, Use QEMU with TCG (available in future):
> qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ...
> Use QEMU with KVM (available at present):
> qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ...
>
> The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> default-configs/mips64el-softmmu.mak | 1 +
> hw/mips/Kconfig | 11 +
> hw/mips/Makefile.objs | 1 +
> hw/mips/loongson3_virt.c | 978 +++++++++++++++++++++++++++++++++++
> 4 files changed, 991 insertions(+)
> create mode 100644 hw/mips/loongson3_virt.c
>
> diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
> index 9f8a3ef..26c660a 100644
> --- a/default-configs/mips64el-softmmu.mak
> +++ b/default-configs/mips64el-softmmu.mak
> @@ -3,6 +3,7 @@
> include mips-softmmu-common.mak
> CONFIG_IDE_VIA=y
> CONFIG_FULOONG=y
> +CONFIG_LOONGSON3V=y
> CONFIG_ATI_VGA=y
> CONFIG_RTL8139_PCI=y
> CONFIG_JAZZ=y
> diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
> index 67d39c5..cc5609b 100644
> --- a/hw/mips/Kconfig
> +++ b/hw/mips/Kconfig
> @@ -45,6 +45,17 @@ config FULOONG
> bool
> select PCI_BONITO
>
> +config LOONGSON3V
> + bool
> + select PCKBD
> + select SERIAL
> + select GOLDFISH_RTC
> + select LOONGSON_LIOINTC
> + select PCI_EXPRESS_GENERIC_BRIDGE
> + select VIRTIO_VGA
> + select QXL if SPICE
> + select MSI_NONBROKEN
> +
> config MIPS_CPS
> bool
> select PTIMER
> diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
> index 739e2b7..0993852 100644
> --- a/hw/mips/Makefile.objs
> +++ b/hw/mips/Makefile.objs
> @@ -4,5 +4,6 @@ obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o
> obj-$(CONFIG_MIPSSIM) += mipssim.o
> obj-$(CONFIG_JAZZ) += jazz.o
> obj-$(CONFIG_FULOONG) += fuloong2e.o
> +obj-$(CONFIG_LOONGSON3V) += loongson3_virt.o
> obj-$(CONFIG_MIPS_CPS) += cps.o
> obj-$(CONFIG_MIPS_BOSTON) += boston.o
> diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
> new file mode 100644
> index 0000000..e0e1939
> --- /dev/null
> +++ b/hw/mips/loongson3_virt.c
> @@ -0,0 +1,978 @@
> +/*
> + * Generic Loongson-3 Platform support
> + *
> + * Copyright (c) 2016-2020 Huacai Chen (chenhc@lemote.com)
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> + */
> +
> +/*
> + * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
> + * extensions, 800~2000MHz)
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "qemu/units.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "elf.h"
> +#include "kvm_mips.h"
> +#include "hw/boards.h"
> +#include "hw/char/serial.h"
> +#include "hw/mips/mips.h"
> +#include "hw/mips/cpudevs.h"
> +#include "hw/misc/empty_slot.h"
> +#include "hw/intc/i8259.h"
> +#include "hw/loader.h"
> +#include "hw/isa/superio.h"
> +#include "hw/pci/msi.h"
> +#include "hw/pci/pci.h"
> +#include "hw/pci/pci_host.h"
> +#include "hw/pci-host/gpex.h"
> +#include "hw/rtc/mc146818rtc.h"
> +#include "hw/usb.h"
> +#include "net/net.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/kvm.h"
> +#include "sysemu/qtest.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
> +#include "qemu/log.h"
> +#include "qemu/error-report.h"
> +
> +#define PM_CNTL_MODE 0x10
> +
> +/* Overall MMIO & Memory layout */
> +enum {
> + VIRT_LOWMEM,
> + VIRT_PM,
> + VIRT_FW_CFG,
> + VIRT_RTC,
> + VIRT_PCIE_PIO,
> + VIRT_PCIE_ECAM,
> + VIRT_BIOS_ROM,
> + VIRT_UART,
> + VIRT_LIOINTC,
> + VIRT_PCIE_MMIO,
> + VIRT_HIGHMEM
> +};
> +
> +/* Low MEM layout for QEMU kernel loader */
> +enum {
> + LOADER_KERNEL,
> + LOADER_INITRD,
> + LOADER_CMDLINE
> +};
> +
> +/* BIOS ROM layout for QEMU kernel loader */
> +enum {
> + LOADER_BOOTROM,
> + LOADER_PARAM,
> +};
> +
> +struct MemmapEntry {
> + hwaddr base;
> + hwaddr size;
> +};
> +
> +/* Data for BIOS to identify machine */
> +#define FW_CFG_MACHINE_VERSION (FW_CFG_ARCH_LOCAL + 0)
> +#define FW_CFG_CPU_FREQ (FW_CFG_ARCH_LOCAL + 1)
> +
> +/*
> + * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structrues
> + * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux kernel
> + */
> +struct efi_memory_map_loongson {
> + uint16_t vers; /* version of efi_memory_map */
> + uint32_t nr_map; /* number of memory_maps */
> + uint32_t mem_freq; /* memory frequence */
> + struct mem_map {
> + uint32_t node_id; /* node_id which memory attached to */
> + uint32_t mem_type; /* system memory, pci memory, pci io, etc. */
> + uint64_t mem_start; /* memory map start address */
> + uint32_t mem_size; /* each memory_map size, not the total size */
> + } map[128];
> +} __attribute__((packed));
> +
> +enum loongson_cpu_type {
> + Legacy_2E = 0x0,
> + Legacy_2F = 0x1,
> + Legacy_3A = 0x2,
> + Legacy_3B = 0x3,
> + Legacy_1A = 0x4,
> + Legacy_1B = 0x5,
> + Legacy_2G = 0x6,
> + Legacy_2H = 0x7,
> + Loongson_1A = 0x100,
> + Loongson_1B = 0x101,
> + Loongson_2E = 0x200,
> + Loongson_2F = 0x201,
> + Loongson_2G = 0x202,
> + Loongson_2H = 0x203,
> + Loongson_3A = 0x300,
> + Loongson_3B = 0x301
> +};
> +
> +/*
> + * Capability and feature descriptor structure for MIPS CPU
> + */
> +struct efi_cpuinfo_loongson {
> + uint16_t vers; /* version of efi_cpuinfo_loongson */
> + uint32_t processor_id; /* PRID, e.g. 6305, 6306 */
> + uint32_t cputype; /* Loongson_3A/3B, etc. */
> + uint32_t total_node; /* num of total numa nodes */
> + uint16_t cpu_startup_core_id; /* Boot core id */
> + uint16_t reserved_cores_mask;
> + uint32_t cpu_clock_freq; /* cpu_clock */
> + uint32_t nr_cpus;
> + char cpuname[64];
> +} __attribute__((packed));
> +
> +#define MAX_UARTS 64
> +struct uart_device {
> + uint32_t iotype;
> + uint32_t uartclk;
> + uint32_t int_offset;
> + uint64_t uart_base;
> +} __attribute__((packed));
> +
> +#define MAX_SENSORS 64
> +#define SENSOR_TEMPER 0x00000001
> +#define SENSOR_VOLTAGE 0x00000002
> +#define SENSOR_FAN 0x00000004
> +struct sensor_device {
> + char name[32]; /* a formal name */
> + char label[64]; /* a flexible description */
> + uint32_t type; /* SENSOR_* */
> + uint32_t id; /* instance id of a sensor-class */
> + uint32_t fan_policy; /* step speed or constant speed */
> + uint32_t fan_percent;/* only for constant speed policy */
> + uint64_t base_addr; /* base address of device registers */
> +} __attribute__((packed));
> +
> +struct system_loongson {
> + uint16_t vers; /* version of system_loongson */
> + uint32_t ccnuma_smp; /* 0: no numa; 1: has numa */
> + uint32_t sing_double_channel;/* 1: single; 2: double */
> + uint32_t nr_uarts;
> + struct uart_device uarts[MAX_UARTS];
> + uint32_t nr_sensors;
> + struct sensor_device sensors[MAX_SENSORS];
> + char has_ec;
> + char ec_name[32];
> + uint64_t ec_base_addr;
> + char has_tcm;
> + char tcm_name[32];
> + uint64_t tcm_base_addr;
> + uint64_t workarounds;
> + uint64_t of_dtb_addr; /* NULL if not support */
> +} __attribute__((packed));
> +
> +struct irq_source_routing_table {
> + uint16_t vers;
> + uint16_t size;
> + uint16_t rtr_bus;
> + uint16_t rtr_devfn;
> + uint32_t vendor;
> + uint32_t device;
> + uint32_t PIC_type; /* conform use HT or PCI to route to CPU-PIC */
> + uint64_t ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
> + uint64_t ht_enable; /* irqs used in this PIC */
> + uint32_t node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
> + uint64_t pci_mem_start_addr;
> + uint64_t pci_mem_end_addr;
> + uint64_t pci_io_start_addr;
> + uint64_t pci_io_end_addr;
> + uint64_t pci_config_addr;
> + uint16_t dma_mask_bits;
> + uint16_t dma_noncoherent;
> +} __attribute__((packed));
> +
> +struct interface_info {
> + uint16_t vers; /* version of the specificition */
> + uint16_t size;
> + uint8_t flag;
> + char description[64];
> +} __attribute__((packed));
> +
> +#define MAX_RESOURCE_NUMBER 128
> +struct resource_loongson {
> + uint64_t start; /* resource start address */
> + uint64_t end; /* resource end address */
> + char name[64];
> + uint32_t flags;
> +};
> +
> +struct archdev_data {}; /* arch specific additions */
> +
> +struct board_devices {
> + char name[64]; /* hold the device name */
> + uint32_t num_resources; /* number of device_resource */
> + /* for each device's resource */
> + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> + /* arch specific additions */
> + struct archdev_data archdata;
> +};
> +
> +struct loongson_special_attribute {
> + uint16_t vers; /* version of this special */
> + char special_name[64]; /* special_atribute_name */
> + uint32_t loongson_special_type; /* type of special device */
> + /* for each device's resource */
> + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> +};
> +
> +struct loongson_params {
> + uint64_t memory_offset; /* efi_memory_map_loongson struct offset */
> + uint64_t cpu_offset; /* efi_cpuinfo_loongson struct offset */
> + uint64_t system_offset; /* system_loongson struct offset */
> + uint64_t irq_offset; /* irq_source_routing_table struct offset */
> + uint64_t interface_offset; /* interface_info struct offset */
> + uint64_t special_offset; /* loongson_special_attribute struct offset */
> + uint64_t boarddev_table_offset; /* board_devices offset */
> +};
> +
> +struct smbios_tables {
> + uint16_t vers; /* version of smbios */
> + uint64_t vga_bios; /* vga_bios address */
> + struct loongson_params lp;
> +};
> +
> +struct efi_reset_system_t {
> + uint64_t ResetCold;
> + uint64_t ResetWarm;
> + uint64_t ResetType;
> + uint64_t Shutdown;
> + uint64_t DoSuspend; /* NULL if not support */
> +};
> +
> +struct efi_loongson {
> + uint64_t mps; /* MPS table */
> + uint64_t acpi; /* ACPI table (IA64 ext 0.71) */
> + uint64_t acpi20; /* ACPI table (ACPI 2.0) */
> + struct smbios_tables smbios; /* SM BIOS table */
> + uint64_t sal_systab; /* SAL system table */
> + uint64_t boot_info; /* boot info table */
> +};
> +
> +struct boot_params {
> + struct efi_loongson efi;
> + struct efi_reset_system_t reset_system;
> +};
> +
> +#define LOONGSON_MAX_VCPUS 16
> +
> +#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
> +
> +#define UART_IRQ 0
> +#define RTC_IRQ 1
> +#define PCIE_IRQ_BASE 2
> +
> +#define align(x) (((x) + 63) & ~63)
> +
> +static const struct MemmapEntry virt_memmap[] = {
> + [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
> + [VIRT_PM] = { 0x10080000, 0x100 },
> + [VIRT_FW_CFG] = { 0x10080100, 0x100 },
> + [VIRT_RTC] = { 0x10081000, 0x1000 },
> + [VIRT_PCIE_PIO] = { 0x18000000, 0xc0000 },
> + [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
> + [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
> + [VIRT_UART] = { 0x1fe001e0, 0x8 },
> + [VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
> + [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
> + [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
> +};
> +
> +static const struct MemmapEntry loader_memmap[] = {
> + [LOADER_KERNEL] = { 0x00000000, 0x4000000 },
> + [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */
> + [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 },
> +};
> +
> +static const struct MemmapEntry loader_rommap[] = {
> + [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 },
> + [LOADER_PARAM] = { 0x1fc01000, 0x10000 },
> +};
> +
> +static struct _loaderparams {
> + uint64_t ram_size;
> + const char *kernel_cmdline;
> + const char *kernel_filename;
> + const char *initrd_filename;
> + uint64_t kernel_entry;
> + uint64_t a0, a1, a2;
> +} loaderparams;
> +
> +static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + return 0;
> +}
> +
> +static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
> +{
> + if (addr != PM_CNTL_MODE) {
> + return;
> + }
> +
> + switch (val) {
> + case 0x00:
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + return;
> + case 0xff:
> + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
> + return;
> + default:
> + return;
> + }
> +}
> +
> +static const MemoryRegionOps loongson3_pm_ops = {
> + .read = loongson3_pm_read,
> + .write = loongson3_pm_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static struct efi_memory_map_loongson *init_memory_map(void *g_map)
> +{
> + struct efi_memory_map_loongson *emap = g_map;
> +
> + emap->nr_map = 2;
> + emap->mem_freq = 300000000;
> +
> + emap->map[0].node_id = 0;
> + emap->map[0].mem_type = 1;
> + emap->map[0].mem_start = 0x0;
> + emap->map[0].mem_size = (loaderparams.ram_size > 0x10000000
> + ? 256 : (loaderparams.ram_size >> 20)) - 16;
> +
> + emap->map[1].node_id = 0;
> + emap->map[1].mem_type = 2;
> + emap->map[1].mem_start = 0x90000000;
> + emap->map[1].mem_size = (loaderparams.ram_size > 0x10000000
> + ? (loaderparams.ram_size >> 20) - 256 : 0);
> +
> + return emap;
> +}
> +
> +#define BUFLEN 1024
> +
> +static uint32_t get_cpu_freq(void)
> +{
> + int fd = 0, freq = 0;
> + char buf[BUFLEN], *buf_p;
> +
> + fd = open("/proc/cpuinfo", O_RDONLY);
> + if (fd == -1) {
> + fprintf(stderr, "Failed to open /proc/cpuinfo!\n");
> + return 0;
> + }
> +
> + if (read(fd, buf, BUFLEN) < 0) {
> + close(fd);
> + fprintf(stderr, "Failed to read /proc/cpuinfo!\n");
> + return 0;
> + }
> + close(fd);
> +
> + buf_p = strstr(buf, "model name");
> + while (*buf_p != '@') {
> + buf_p++;
> + }
> +
> + buf_p += 2;
> + memcpy(buf, buf_p, 12);
> + buf_p = buf;
> + while ((*buf_p >= '0') && (*buf_p <= '9')) {
> + buf_p++;
> + }
> + *buf_p = '\0';
> +
> + freq = atoi(buf);
> +
> + return freq * 1000 * 1000;
> +}
> +
> +static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo_loongson)
> +{
> + struct efi_cpuinfo_loongson *c = g_cpuinfo_loongson;
> +
> + c->cputype = Loongson_3A;
> + c->processor_id = MIPS_CPU(first_cpu)->env.CP0_PRid;
> + c->cpu_clock_freq = get_cpu_freq();
> + if (!c->cpu_clock_freq) {
> + c->cpu_clock_freq = 500000000;
> + }
> +
> + c->cpu_startup_core_id = 0;
> + c->nr_cpus = current_machine->smp.cpus;
> + c->total_node = (current_machine->smp.cpus + 3) / 4;
> +
> + return c;
> +}
> +
> +static struct system_loongson *init_system_loongson(void *g_system)
> +{
> + struct system_loongson *s = g_system;
> +
> + s->ccnuma_smp = 0;
> + s->sing_double_channel = 1;
> + s->nr_uarts = 1;
> + s->uarts[0].iotype = 2;
> + s->uarts[0].int_offset = 2;
> + s->uarts[0].uartclk = 25000000; /* Random value */
> + s->uarts[0].uart_base = virt_memmap[VIRT_UART].base;
> +
> + return s;
> +}
> +
> +static struct irq_source_routing_table *init_irq_source(void *g_irq_source)
> +{
> + struct irq_source_routing_table *irq_info = g_irq_source;
> +
> + irq_info->node_id = 0;
> + irq_info->PIC_type = 0;
> + irq_info->dma_mask_bits = 64;
> + irq_info->pci_mem_start_addr = virt_memmap[VIRT_PCIE_MMIO].base;
> + irq_info->pci_mem_end_addr = virt_memmap[VIRT_PCIE_MMIO].base +
> + virt_memmap[VIRT_PCIE_MMIO].size - 1;
> + irq_info->pci_io_start_addr = virt_memmap[VIRT_PCIE_PIO].base;
> +
> + return irq_info;
> +}
> +
> +static struct interface_info *init_interface_info(void *g_interface)
> +{
> + struct interface_info *interface = g_interface;
> +
> + interface->vers = 0x01;
> + strcpy(interface->description, "UEFI_Version_v1.0");
> +
> + return interface;
> +}
> +
> +static struct board_devices *board_devices_info(void *g_board)
> +{
> + struct board_devices *bd = g_board;
> +
> + strcpy(bd->name, "Loongson-3A-VIRT-1w-V1.00-demo");
> +
> + return bd;
> +}
> +
> +static struct loongson_special_attribute *init_special_info(void *g_special)
> +{
> + struct loongson_special_attribute *special = g_special;
> +
> + strcpy(special->special_name, "2016-08-01");
> +
> + return special;
> +}
> +
> +static void init_loongson_params(struct loongson_params *lp, void *p)
> +{
> + lp->memory_offset = (unsigned long long)init_memory_map(p)
> + - (unsigned long long)lp;
> + p += align(sizeof(struct efi_memory_map_loongson));
> +
> + lp->cpu_offset = (unsigned long long)init_cpu_info(p)
> + - (unsigned long long)lp;
> + p += align(sizeof(struct efi_cpuinfo_loongson));
> +
> + lp->system_offset = (unsigned long long)init_system_loongson(p)
> + - (unsigned long long)lp;
> + p += align(sizeof(struct system_loongson));
> +
> + lp->irq_offset = (unsigned long long)init_irq_source(p)
> + - (unsigned long long)lp;
> + p += align(sizeof(struct irq_source_routing_table));
> +
> + lp->interface_offset = (unsigned long long)init_interface_info(p)
> + - (unsigned long long)lp;
> + p += align(sizeof(struct interface_info));
> +
> + lp->boarddev_table_offset = (unsigned long long)board_devices_info(p)
> + - (unsigned long long)lp;
> + p += align(sizeof(struct board_devices));
> +
> + lp->special_offset = (unsigned long long)init_special_info(p)
> + - (unsigned long long)lp;
> + p += align(sizeof(struct loongson_special_attribute));
> +}
> +
> +static void init_reset_system(struct efi_reset_system_t *reset)
> +{
> + reset->Shutdown = 0xffffffffbfc000a8;
> + reset->ResetCold = 0xffffffffbfc00080;
> + reset->ResetWarm = 0xffffffffbfc00080;
> +}
> +
> +static void init_boot_param(void)
> +{
> + void *p;
> + struct boot_params *bp;
> +
> + p = g_malloc0(loader_rommap[LOADER_PARAM].size);
> + bp = p;
> +
> + bp->efi.smbios.vers = 1;
> + init_reset_system(&(bp->reset_system));
> + p += align(sizeof(struct boot_params));
> + init_loongson_params(&(bp->efi.smbios.lp), p);
> +
> + rom_add_blob_fixed("params_rom", bp,
> + loader_rommap[LOADER_PARAM].size,
> + loader_rommap[LOADER_PARAM].base);
> +
> + g_free(bp);
> +
> + loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL,
> + loader_rommap[LOADER_PARAM].base);
> +}
> +
> +static void init_boot_rom(void)
> +{
> + const unsigned int boot_code[] = {
> + 0x40086000, /* mfc0 t0, CP0_STATUS */
> + 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */
> + 0x01094025, /* or t0, t0, t1 */
> + 0x3C090040, /* lui t1, 0x40 #set bev */
> + 0x01094025, /* or t0, t0, t1 */
> + 0x40886000, /* mtc0 t0, CP0_STATUS */
> + 0x00000000,
> + 0x40806800, /* mtc0 zero, CP0_CAUSE */
> + 0x00000000,
> + 0x400A7801, /* mfc0 t2, $15, 1 */
> + 0x314A00FF, /* andi t2, 0x0ff */
> + 0x3C089000, /* dli t0, 0x900000003ff01000 */
> + 0x00084438,
> + 0x35083FF0,
> + 0x00084438,
> + 0x35081000,
> + 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */
> + 0x000B5A00, /* sll t3, 8 */
> + 0x010B4025, /* or t0, t0, t3 */
> + 0x314C000C, /* andi t4, t2, 0xc #node id */
> + 0x000C62BC, /* dsll t4, 42 */
> + 0x010C4025, /* or t0, t0, t4 */
> + /* WaitForInit: */
> + 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */
> + 0x1040FFFE, /* beqz v0, WaitForInit */
> + 0x00000000, /* nop */
> + 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */
> + 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */
> + 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */
> + 0x00400008, /* jr v0 #byebye */
> + 0x00000000, /* nop */
> + 0x1000FFFF, /* 1: b 1b */
> + 0x00000000, /* nop */
> +
> + /* Reset */
> + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> + 0x358C0000,
> + 0x000C6438,
> + 0x358C1008,
> + 0x000C6438,
> + 0x358C0010,
> + 0x240D0000, /* li t1, 0x00 */
> + 0xA18D0000, /* sb t1, (t0) */
> + 0x1000FFFF, /* 1: b 1b */
> + 0x00000000, /* nop */
> +
> + /* Shutdown */
> + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> + 0x358C0000,
> + 0x000C6438,
> + 0x358C1008,
> + 0x000C6438,
> + 0x358C0010,
> + 0x240D00FF, /* li t1, 0xff */
> + 0xA18D0000, /* sb t1, (t0) */
> + 0x1000FFFF, /* 1: b 1b */
> + 0x00000000 /* nop */
> + };
> +
> + rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
> + loader_rommap[LOADER_BOOTROM].base);
> +}
> +
> +static void fw_cfg_boot_set(void *opaque, const char *boot_device,
> + Error **errp)
> +{
> + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
> +}
> +
> +static void fw_conf_init(unsigned long ram_size)
> +{
> + FWCfgState *fw_cfg;
> + hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
> +
> + fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
> + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> + fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
> + fw_cfg_add_i32(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq());
> + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> +}
> +
> +static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
> +{
> + hwaddr cmdline_vaddr;
> + char memenv[32];
> + char highmemenv[32];
> + void *cmdline_buf;
> + unsigned int *parg_env;
> + int ret = 0;
> +
> + /* Allocate cmdline_buf for command line. */
> + cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
> + cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
> + loader_memmap[LOADER_CMDLINE].base);
> +
> + /*
> + * Layout of cmdline_buf looks like this:
> + * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
> + * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
> + */
> + parg_env = (void *)cmdline_buf;
> +
> + ret = (3 + 1) * 4;
> + *parg_env++ = cmdline_vaddr + ret;
> + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
> +
> + /* argv1 */
> + *parg_env++ = cmdline_vaddr + ret;
> + if (initrd_size > 0)
> + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
> + "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
> + cpu_mips_phys_to_kseg0(NULL, initrd_offset),
> + initrd_size, loaderparams.kernel_cmdline));
> + else
> + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
> + loaderparams.kernel_cmdline));
> +
> + /* argv2 */
> + *parg_env++ = cmdline_vaddr + 4 * ret;
> +
> + /* env */
> + sprintf(memenv, "%ld", loaderparams.ram_size > 0x10000000
> + ? 256 : (loaderparams.ram_size >> 20));
> + sprintf(highmemenv, "%ld", loaderparams.ram_size > 0x10000000
> + ? (loaderparams.ram_size >> 20) - 256 : 0);
> +
> + rom_add_blob_fixed("cmdline", cmdline_buf,
> + loader_memmap[LOADER_CMDLINE].size,
> + loader_memmap[LOADER_CMDLINE].base);
> +
> + g_free(cmdline_buf);
> +
> + loaderparams.a0 = 2;
> + loaderparams.a1 = cmdline_vaddr;
> +
> + return 0;
> +}
> +
> +static uint64_t load_kernel(CPUMIPSState *env)
> +{
> + long kernel_size;
> + ram_addr_t initrd_offset;
> + uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
> +
> + kernel_size = load_elf(loaderparams.kernel_filename, NULL,
> + cpu_mips_kseg0_to_phys, NULL,
> + (uint64_t *)&kernel_entry,
> + (uint64_t *)&kernel_low, (uint64_t *)&kernel_high,
> + NULL, 0, EM_MIPS, 1, 0);
> + if (kernel_size < 0) {
> + error_report("could not load kernel '%s': %s",
> + loaderparams.kernel_filename,
> + load_elf_strerror(kernel_size));
> + exit(1);
> + }
> +
> + /* load initrd */
> + initrd_size = 0;
> + initrd_offset = 0;
> + if (loaderparams.initrd_filename) {
> + initrd_size = get_image_size(loaderparams.initrd_filename);
> + if (initrd_size > 0) {
> + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
> + INITRD_PAGE_MASK;
> + initrd_offset = MAX(initrd_offset,
> + loader_memmap[LOADER_INITRD].base);
> +
> + if (initrd_offset + initrd_size > ram_size) {
> + error_report("memory too small for initial ram disk '%s'",
> + loaderparams.initrd_filename);
> + exit(1);
> + }
> +
> + initrd_size = load_image_targphys(loaderparams.initrd_filename,
> + initrd_offset,
> + ram_size - initrd_offset);
> + }
> +
> + if (initrd_size == (target_ulong) -1) {
> + error_report("could not load initial ram disk '%s'",
> + loaderparams.initrd_filename);
> + exit(1);
> + }
> + }
> +
> + /* Setup prom cmdline. */
> + set_prom_cmdline(initrd_offset, initrd_size);
> +
> + return kernel_entry;
> +}
> +
> +static void main_cpu_reset(void *opaque)
> +{
> + MIPSCPU *cpu = opaque;
> + CPUMIPSState *env = &cpu->env;
> +
> + cpu_reset(CPU(cpu));
> +
> + /* Loongson-3 reset stuff */
> + if (loaderparams.kernel_filename) {
> + if (cpu == MIPS_CPU(first_cpu)) {
> + env->active_tc.gpr[4] = loaderparams.a0;
> + env->active_tc.gpr[5] = loaderparams.a1;
> + env->active_tc.gpr[6] = loaderparams.a2;
> + env->active_tc.PC = loaderparams.kernel_entry;
> + }
> + env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
> + }
> +}
> +
> +static inline void loongson3_virt_devices_init(MachineState *machine, DeviceState *pic)
> +{
> + int i;
> + qemu_irq irq;
> + PCIBus *pci_bus;
> + DeviceState *dev;
> + MemoryRegion *pio_alias;
> + MemoryRegion *mmio_alias, *mmio_reg;
> + MemoryRegion *ecam_alias, *ecam_reg;
> +
> + dev = qdev_new(TYPE_GPEX_HOST);
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> + pci_bus = PCI_HOST_BRIDGE(dev)->bus;
> +
> + ecam_alias = g_new0(MemoryRegion, 1);
> + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
> + ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
> + memory_region_add_subregion(get_system_memory(),
> + virt_memmap[VIRT_PCIE_ECAM].base, ecam_alias);
> +
> + mmio_alias = g_new0(MemoryRegion, 1);
> + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
> + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
> + mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
> + virt_memmap[VIRT_PCIE_MMIO].size);
> + memory_region_add_subregion(get_system_memory(),
> + virt_memmap[VIRT_PCIE_MMIO].base, mmio_alias);
> +
> + pio_alias = g_new0(MemoryRegion, 1);
> + memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
> + get_system_io(), 0, virt_memmap[VIRT_PCIE_PIO].size);
> + memory_region_add_subregion(get_system_memory(),
> + virt_memmap[VIRT_PCIE_PIO].base, pio_alias);
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
> +
> + for (i = 0; i < GPEX_NUM_IRQS; i++) {
> + irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
> + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
> + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
> + }
> +
> + pci_vga_init(pci_bus);
> +
> + if (defaults_enabled()) {
> + pci_create_simple(pci_bus, -1, "pci-ohci");
> + usb_create_simple(usb_bus_find(-1), "usb-kbd");
> + usb_create_simple(usb_bus_find(-1), "usb-tablet");
> + }
> +
> + for (i = 0; i < nb_nics; i++) {
> + NICInfo *nd = &nd_table[i];
> +
> + if (!nd->model) {
> + nd->model = g_strdup("virtio");
> + }
> +
> + pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
> + }
> +}
> +
> +static void mips_loongson3_virt_init(MachineState *machine)
> +{
> + int i;
> + long bios_size;
> + MIPSCPU *cpu;
> + CPUMIPSState *env;
> + DeviceState *liointc;
> + char *filename;
> + const char *kernel_cmdline = machine->kernel_cmdline;
> + const char *kernel_filename = machine->kernel_filename;
> + const char *initrd_filename = machine->initrd_filename;
> + ram_addr_t ram_size = machine->ram_size;
> + MemoryRegion *address_space_mem = get_system_memory();
> + MemoryRegion *ram = g_new(MemoryRegion, 1);
> + MemoryRegion *bios = g_new(MemoryRegion, 1);
> + MemoryRegion *iomem = g_new(MemoryRegion, 1);
> +
> + /* TODO: TCG will support all CPU types */
> + if (!kvm_enabled()) {
> + if (!machine->cpu_type) {
> + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
> + }
> + if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
> + error_report("Loongson-3/TCG need cpu type Loongson-3A1000");
> + exit(1);
> + }
> + } else {
> + if (!machine->cpu_type) {
> + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
> + }
> + if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
> + error_report("Loongson-3/KVM need cpu type Loongson-3A4000");
> + exit(1);
> + }
> + }
> +
> + if (ram_size < 512 * 0x100000) {
> + error_report("Loongson-3 need at least 512MB memory");
> + exit(1);
> + }
> +
> + /*
> + * The whole MMIO range among configure registers doesn't generate
> + * exception when accessing invalid memory. Create an empty slot to
> + * emulate this feature.
> + */
> + empty_slot_init("fallback", 0, 0x80000000);
> +
> + liointc = qdev_new("loongson.liointc");
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
> +
> + for (i = 0; i < machine->smp.cpus; i++) {
> + int ip;
> +
> + /* init CPUs */
> + cpu = MIPS_CPU(cpu_create(machine->cpu_type));
> +
> + /* Init internal devices */
> + cpu_mips_irq_init_cpu(cpu);
> + cpu_mips_clock_init(cpu);
> + qemu_register_reset(main_cpu_reset, cpu);
> +
> + if (i >= 4) {
> + continue; /* Only node-0 can be connected to LIOINTC */
> + }
> +
> + for (ip = 0; ip < 4 ; ip++) {
> + int pin = i * 4 + ip;
> + sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
> + pin, cpu->env.irq[ip + 2]);
> + }
> + }
> + env = &MIPS_CPU(first_cpu)->env;
> +
> + /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
> + memory_region_init_rom(bios, NULL, "loongson3.bios",
> + virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
> + memory_region_init_alias(ram, NULL, "loongson3.lowmem",
> + machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
> + memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
> + NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
> +
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_LOWMEM].base, ram);
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_BIOS_ROM].base, bios);
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_HIGHMEM].base, machine->ram);
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_PM].base, iomem);
> +
> + /*
> + * We do not support flash operation, just loading bios.bin as raw BIOS.
> + * Please use -L to set the BIOS path and -bios to set bios name.
> + */
> +
> + if (kernel_filename) {
> + loaderparams.ram_size = ram_size;
> + loaderparams.kernel_filename = kernel_filename;
> + loaderparams.kernel_cmdline = kernel_cmdline;
> + loaderparams.initrd_filename = initrd_filename;
> + loaderparams.kernel_entry = load_kernel(env);
> +
> + init_boot_rom();
> + init_boot_param();
> + } else {
> + if (bios_name == NULL) {
> + bios_name = LOONGSON3_BIOSNAME;
> + }
> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> + if (filename) {
> + bios_size = load_image_targphys(filename,
> + virt_memmap[VIRT_BIOS_ROM].base,
> + virt_memmap[VIRT_BIOS_ROM].size);
> + g_free(filename);
> + } else {
> + bios_size = -1;
> + }
> +
> + if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
> + !kernel_filename && !qtest_enabled()) {
> + error_report("Could not load MIPS bios '%s'", bios_name);
> + exit(1);
> + }
> +
> + fw_conf_init(ram_size);
> + }
> +
> + msi_nonbroken = true;
> + loongson3_virt_devices_init(machine, liointc);
> +
> + sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
> + qdev_get_gpio_in(liointc, RTC_IRQ));
> +
> + if (serial_hd(0)) {
> + serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
> + qdev_get_gpio_in(liointc, UART_IRQ), 115200,
> + serial_hd(0), DEVICE_NATIVE_ENDIAN);
> + }
> +}
> +
> +static void mips_loongson3_virt_machine_init(MachineClass *mc)
> +{
> + mc->desc = "Loongson-3 Virtualization Platform";
> + mc->init = mips_loongson3_virt_init;
> + mc->block_default_type = IF_IDE;
> + mc->max_cpus = LOONGSON_MAX_VCPUS;
> + mc->default_ram_id = "loongson3.highram";
> + /* 1500MB is the requirement of distros for Loongson-3 */
> + mc->default_ram_size = 1500 * MiB;
> + mc->kvm_type = mips_kvm_type;
> + mc->minimum_page_bits = 14;
> +}
> +
> +DEFINE_MACHINE("loongson3-virt", mips_loongson3_virt_machine_init)
> --
> 2.7.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 2/4] hw/intc: Add Loongson liointc support
2020-06-24 10:45 ` [PATCH V6 2/4] hw/intc: Add Loongson liointc support Huacai Chen
@ 2020-06-25 10:35 ` Aleksandar Markovic
2020-06-27 17:54 ` Aleksandar Markovic
1 sibling, 0 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-25 10:35 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
Jiaxun Yang, QEMU Developers, Huacai Chen, Aurelien Jarno
сре, 24. јун 2020. у 12:44 Huacai Chen <zltjiangshi@gmail.com> је написао/ла:
>
> Loongson-3 has an integrated liointc (Local I/O interrupt controller).
> It is similar to goldfish interrupt controller, but more powerful (e.g.,
> it can route external interrupt to multi-cores).
>
> Documents about Loongson-3's liointc:
> 1, https://wiki.godson.ac.cn/ip_block:liointc;
> 2, The "I/O中断" section of Loongson-3's user mannual, part 1.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> hw/intc/Kconfig | 3 +
> hw/intc/Makefile.objs | 1 +
> hw/intc/loongson_liointc.c | 241 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 245 insertions(+)
> create mode 100644 hw/intc/loongson_liointc.c
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f562342..2ae1e89 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -64,3 +64,6 @@ config OMPIC
>
> config RX_ICU
> bool
> +
> +config LOONGSON_LIOINTC
> + bool
> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> index a420263..3ac2b40 100644
> --- a/hw/intc/Makefile.objs
> +++ b/hw/intc/Makefile.objs
> @@ -51,3 +51,4 @@ obj-$(CONFIG_MIPS_CPS) += mips_gic.o
> obj-$(CONFIG_NIOS2) += nios2_iic.o
> obj-$(CONFIG_OMPIC) += ompic.o
> obj-$(CONFIG_IBEX) += ibex_plic.o
> +obj-$(CONFIG_LOONGSON_LIOINTC) += loongson_liointc.o
> diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c
> new file mode 100644
> index 0000000..e39e39e
> --- /dev/null
> +++ b/hw/intc/loongson_liointc.c
> @@ -0,0 +1,241 @@
> +/*
> + * QEMU Loongson Local I/O interrupt controler.
> + *
> + * Copyright (c) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "qemu/module.h"
> +#include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> +
> +#define D(x)
> +
> +#define NUM_IRQS 32
> +
> +#define NUM_CORES 4
> +#define NUM_IPS 4
> +#define NUM_PARENTS (NUM_CORES * NUM_IPS)
> +#define PARENT_COREx_IPy(x, y) (NUM_IPS * x + y)
> +
> +#define R_MAPPER_START 0x0
> +#define R_MAPPER_END 0x20
> +#define R_ISR R_MAPPER_END
> +#define R_IEN 0x24
> +#define R_IEN_SET 0x28
> +#define R_IEN_CLR 0x2c
> +#define R_PERCORE_ISR(x) (0x40 + 0x8 * x)
> +#define R_END 0x64
> +
> +#define TYPE_LOONGSON_LIOINTC "loongson.liointc"
> +#define LOONGSON_LIOINTC(obj) \
> + OBJECT_CHECK(struct loongson_liointc, (obj), TYPE_LOONGSON_LIOINTC)
> +
> +struct loongson_liointc {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> + qemu_irq parent_irq[NUM_PARENTS];
> +
> + uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */
> + uint32_t isr;
> + uint32_t ien;
> + uint32_t per_core_isr[NUM_CORES];
> +
> + /* state of the interrupt input pins */
> + uint32_t pin_state;
> + bool parent_state[NUM_PARENTS];
> +};
> +
> +static void update_irq(struct loongson_liointc *p)
> +{
> + uint32_t irq, core, ip;
> + uint32_t per_ip_isr[NUM_IPS] = {0};
> +
> + /* level triggered interrupt */
> + p->isr = p->pin_state;
> +
> + /* Clear disabled IRQs */
> + p->isr &= p->ien;
> +
> + /* Clear per_core_isr */
> + for (core = 0; core < NUM_CORES; core++) {
> + p->per_core_isr[core] = 0;
> + }
> +
> + /* Update per_core_isr and per_ip_isr */
> + for (irq = 0; irq < NUM_IRQS; irq++) {
> + if (!(p->isr & (1 << irq))) {
> + continue;
> + }
> +
> + for (core = 0; core < NUM_CORES; core++) {
> + if ((p->mapper[irq] & (1 << core))) {
> + p->per_core_isr[core] |= (1 << irq);
> + }
> + }
> +
> + for (ip = 0; ip < NUM_IPS; ip++) {
> + if ((p->mapper[irq] & (1 << (ip + 4)))) {
> + per_ip_isr[ip] |= (1 << irq);
> + }
> + }
> + }
> +
> + /* Emit IRQ to parent! */
> + for (core = 0; core < NUM_CORES; core++) {
> + for (ip = 0; ip < NUM_IPS; ip++) {
> + int parent = PARENT_COREx_IPy(core, ip);
> + if (p->parent_state[parent] !=
> + (!!p->per_core_isr[core] && !!per_ip_isr[ip])) {
> + p->parent_state[parent] = !p->parent_state[parent];
> + qemu_set_irq(p->parent_irq[parent], p->parent_state[parent]);
> + }
> + }
> + }
> +}
> +
> +static uint64_t
> +liointc_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + struct loongson_liointc *p = opaque;
> + uint32_t r = 0;
> +
> + /* Mapper is 1 byte */
> + if (size == 1 && addr < R_MAPPER_END) {
> + r = p->mapper[addr];
> + goto out;
> + }
> +
> + /* Rest is 4 byte */
> + if (size != 4 || (addr % 4)) {
> + goto out;
> + }
> +
> + if (addr >= R_PERCORE_ISR(0) &&
> + addr < R_PERCORE_ISR(NUM_CORES)) {
> + int core = (addr - R_PERCORE_ISR(0)) / 4;
> + r = p->per_core_isr[core];
> + goto out;
> + }
> +
> + switch (addr) {
> + case R_ISR:
> + r = p->isr;
> + break;
> + case R_IEN:
> + r = p->ien;
> + break;
> + default:
> + break;
> + }
> +
> +out:
> + D(qemu_log("%s: size=%d addr=%lx val=%x\n", __func__, size, addr, r));
> + return r;
> +}
> +
> +static void
> +liointc_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + struct loongson_liointc *p = opaque;
> + uint32_t value = val64;
> +
> + D(qemu_log("%s: size=%d, addr=%lx val=%x\n", __func__, size, addr, value));
> +
> + /* Mapper is 1 byte */
> + if (size == 1 && addr < R_MAPPER_END) {
> + p->mapper[addr] = value;
> + goto out;
> + }
> +
> + /* Rest is 4 byte */
> + if (size != 4 || (addr % 4)) {
> + goto out;
> + }
> +
> + if (addr >= R_PERCORE_ISR(0) &&
> + addr < R_PERCORE_ISR(NUM_CORES)) {
> + int core = (addr - R_PERCORE_ISR(0)) / 4;
> + p->per_core_isr[core] = value;
> + goto out;
> + }
> +
> + switch (addr) {
> + case R_IEN_SET:
> + p->ien |= value;
> + break;
> + case R_IEN_CLR:
> + p->ien &= ~value;
> + break;
> + default:
> + break;
> + }
> +
> +out:
> + update_irq(p);
> +}
> +
> +static const MemoryRegionOps pic_ops = {
> + .read = liointc_read,
> + .write = liointc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4
> + }
> +};
> +
> +static void irq_handler(void *opaque, int irq, int level)
> +{
> + struct loongson_liointc *p = opaque;
> +
> + p->pin_state &= ~(1 << irq);
> + p->pin_state |= level << irq;
> + update_irq(p);
> +}
> +
> +static void loongson_liointc_init(Object *obj)
> +{
> + struct loongson_liointc *p = LOONGSON_LIOINTC(obj);
> + int i;
> +
> + qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
> +
> + for (i = 0; i < NUM_PARENTS; i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq[i]);
> + }
> +
> + memory_region_init_io(&p->mmio, obj, &pic_ops, p,
> + "loongson.liointc", R_END);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
> +}
> +
> +static const TypeInfo loongson_liointc_info = {
> + .name = TYPE_LOONGSON_LIOINTC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(struct loongson_liointc),
> + .instance_init = loongson_liointc_init,
> +};
> +
> +static void loongson_liointc_register_types(void)
> +{
> + type_register_static(&loongson_liointc_info);
> +}
> +
> +type_init(loongson_liointc_register_types)
> --
> 2.7.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer
2020-06-24 10:45 ` [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer Huacai Chen
@ 2020-06-25 10:41 ` Aleksandar Markovic
2020-06-27 17:53 ` Aleksandar Markovic
1 sibling, 0 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-25 10:41 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
QEMU Developers, Huacai Chen, Aurelien Jarno
сре, 24. јун 2020. у 12:45 Huacai Chen <zltjiangshi@gmail.com> је написао/ла:
>
> Add myself as a maintainer of Loongson-3 virtual platform, and also add
> Jiaxun Yang as a reviewer.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
I am inclined to select LIOINTC patch for the next MIPS queue, even if
other patches from this series still await clarification.
If this happens, I will also accept this patch, in a a slightly
modified form, to reflect that only LIOINTC part is accepted.
I will also add this note in the commit message: "All changes related
to Loongson-3 virtual platforms will still be integrated via main MIPS
pull requests."
With these changes:
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> MAINTAINERS | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 51a4570..0226a74 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1095,6 +1095,13 @@ F: hw/isa/vt82c686.c
> F: hw/pci-host/bonito.c
> F: include/hw/isa/vt82c686.h
>
> +Loongson-3 Virtual Platform
> +M: Huacai Chen <chenhc@lemote.com>
> +R: Jiaxun Yang <jiaxun.yang@flygoat.com>
> +S: Maintained
> +F: hw/mips/loongson3_virt.c
> +F: hw/intc/loongson_liointc.c
> +
> Boston
> M: Paul Burton <pburton@wavecomp.com>
> R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
> --
> 2.7.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass
2020-06-24 10:45 ` [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass Huacai Chen
@ 2020-06-25 12:31 ` Aleksandar Markovic
2020-06-25 13:25 ` Aleksandar Markovic
2020-06-27 17:51 ` Aleksandar Markovic
1 sibling, 1 reply; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-25 12:31 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
QEMU Developers, Huacai Chen, Aurelien Jarno
сре, 24. јун 2020. у 12:44 Huacai Chen <zltjiangshi@gmail.com> је написао/ла:
>
> MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we
> can't create a VZ guest in QEMU because it lacks the kvm_type() hook in
> MachineClass. This patch add the the kvm_type() hook to support both of
> the two types.
>
> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> target/mips/kvm.c | 20 ++++++++++++++++++++
> target/mips/kvm_mips.h | 11 +++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/target/mips/kvm.c b/target/mips/kvm.c
> index 96cfa10..373f582 100644
> --- a/target/mips/kvm.c
> +++ b/target/mips/kvm.c
> @@ -21,10 +21,12 @@
> #include "qemu/main-loop.h"
> #include "qemu/timer.h"
> #include "sysemu/kvm.h"
> +#include "sysemu/kvm_int.h"
> #include "sysemu/runstate.h"
> #include "sysemu/cpus.h"
> #include "kvm_mips.h"
> #include "exec/memattrs.h"
> +#include "hw/boards.h"
>
> #define DEBUG_KVM 0
>
> @@ -1270,3 +1272,21 @@ int kvm_arch_msi_data_to_gsi(uint32_t data)
> {
> abort();
> }
> +
> +int mips_kvm_type(MachineState *machine, const char *vm_type)
> +{
> + int r;
> + KVMState *s = KVM_STATE(machine->accelerator);
> +
> + r = kvm_check_extension(s, KVM_CAP_MIPS_VZ);
This will not work for build systems with kernel < 4.12. You need to
provide fallback solution for that case.
> + if (r > 0) {
> + return KVM_VM_MIPS_VZ;
> + }
> +
> + r = kvm_check_extension(s, KVM_CAP_MIPS_TE);
> + if (r > 0) {
> + return KVM_VM_MIPS_TE;
> + }
> +
> + return -1;
> +}
> diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h
> index 1e40147..171d53d 100644
> --- a/target/mips/kvm_mips.h
> +++ b/target/mips/kvm_mips.h
> @@ -12,6 +12,8 @@
> #ifndef KVM_MIPS_H
> #define KVM_MIPS_H
>
> +#include "cpu.h"
> +
> /**
> * kvm_mips_reset_vcpu:
> * @cpu: MIPSCPU
> @@ -23,4 +25,13 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu);
> int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level);
> int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level);
>
> +#ifdef CONFIG_KVM
> +int mips_kvm_type(MachineState *machine, const char *vm_type);
> +#else
> +static inline int mips_kvm_type(MachineState *machine, const char *vm_type)
> +{
> + return 0;
> +}
> +#endif
> +
> #endif /* KVM_MIPS_H */
> --
> 2.7.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass
2020-06-25 12:31 ` Aleksandar Markovic
@ 2020-06-25 13:25 ` Aleksandar Markovic
0 siblings, 0 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-25 13:25 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
QEMU Developers, Huacai Chen, Aurelien Jarno
чет, 25. јун 2020. у 14:31 Aleksandar Markovic
<aleksandar.qemu.devel@gmail.com> је написао/ла:
>
> сре, 24. јун 2020. у 12:44 Huacai Chen <zltjiangshi@gmail.com> је написао/ла:
> >
> > MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we
> > can't create a VZ guest in QEMU because it lacks the kvm_type() hook in
> > MachineClass. This patch add the the kvm_type() hook to support both of
> > the two types.
> >
> > Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > ---
> > target/mips/kvm.c | 20 ++++++++++++++++++++
> > target/mips/kvm_mips.h | 11 +++++++++++
> > 2 files changed, 31 insertions(+)
> >
> > diff --git a/target/mips/kvm.c b/target/mips/kvm.c
> > index 96cfa10..373f582 100644
> > --- a/target/mips/kvm.c
> > +++ b/target/mips/kvm.c
> > @@ -21,10 +21,12 @@
> > #include "qemu/main-loop.h"
> > #include "qemu/timer.h"
> > #include "sysemu/kvm.h"
> > +#include "sysemu/kvm_int.h"
> > #include "sysemu/runstate.h"
> > #include "sysemu/cpus.h"
> > #include "kvm_mips.h"
> > #include "exec/memattrs.h"
> > +#include "hw/boards.h"
> >
> > #define DEBUG_KVM 0
> >
> > @@ -1270,3 +1272,21 @@ int kvm_arch_msi_data_to_gsi(uint32_t data)
> > {
> > abort();
> > }
> > +
> > +int mips_kvm_type(MachineState *machine, const char *vm_type)
> > +{
> > + int r;
> > + KVMState *s = KVM_STATE(machine->accelerator);
> > +
> > + r = kvm_check_extension(s, KVM_CAP_MIPS_VZ);
>
> This will not work for build systems with kernel < 4.12. You need to
> provide fallback solution for that case.
>
I am perhaps wrong here. If we pull the preprocessor constants from
imported Linux headers, than we don;t need host kernel headers
supporting KVM_CAP_MIPS_VZ. I will doublecheck.
Thanks, Aleksandar
> > + if (r > 0) {
> > + return KVM_VM_MIPS_VZ;
> > + }
> > +
> > + r = kvm_check_extension(s, KVM_CAP_MIPS_TE);
> > + if (r > 0) {
> > + return KVM_VM_MIPS_TE;
> > + }
> > +
> > + return -1;
> > +}
> > diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h
> > index 1e40147..171d53d 100644
> > --- a/target/mips/kvm_mips.h
> > +++ b/target/mips/kvm_mips.h
> > @@ -12,6 +12,8 @@
> > #ifndef KVM_MIPS_H
> > #define KVM_MIPS_H
> >
> > +#include "cpu.h"
> > +
> > /**
> > * kvm_mips_reset_vcpu:
> > * @cpu: MIPSCPU
> > @@ -23,4 +25,13 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu);
> > int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level);
> > int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level);
> >
> > +#ifdef CONFIG_KVM
> > +int mips_kvm_type(MachineState *machine, const char *vm_type);
> > +#else
> > +static inline int mips_kvm_type(MachineState *machine, const char *vm_type)
> > +{
> > + return 0;
> > +}
> > +#endif
> > +
> > #endif /* KVM_MIPS_H */
> > --
> > 2.7.0
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 3/4] hw/mips: Add Loongson-3 machine support (with KVM)
2020-06-24 11:50 ` Aleksandar Markovic
@ 2020-06-26 11:30 ` Huacai Chen
0 siblings, 0 replies; 14+ messages in thread
From: Huacai Chen @ 2020-06-26 11:30 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Huacai Chen, Aleksandar Rikalo, Philippe Mathieu-Daudé,
Aurelien Jarno, QEMU Developers
Hi, Aleksandar,
On Wed, Jun 24, 2020 at 7:50 PM Aleksandar Markovic
<aleksandar.qemu.devel@gmail.com> wrote:
>
> сре, 24. јун 2020. у 12:45 Huacai Chen <zltjiangshi@gmail.com> је написао/ла:
> >
> > Add Loongson-3 based machine support, it use liointc as the interrupt
> > controler and use GPEX as the pci controller. Currently it can only work
> > with KVM, but we will add TCG support in future.
> >
> > As the machine model is not based on any exiting physical hardware, the
> > name of the machine is "loongson3-virt". It may be superseded in future
> > by a real machine model. If this happens, then a regular deprecation
> > procedure shall occur for "loongson3-virt" machine.
> >
> > We now already have a full functional Linux kernel (based on Linux-5.4.x
> > LTS, the kvm host side has been upstream in Linux-5.8, but the kvm guest
> > side has not been upstream yet) here:
> >
>
> Hi, Huacai,
>
> Can you please enumerate here links to all patches in your kernel
> repository that are not yet upstreamed, but are necessary for the
> scenario below to work?
The code structure is different between Linux-5.4 and upstream,
because Jiaxun has been making effort to modernize Loongson64 since
5.5 (and will be mostly completed in 5.9).
For Linux-5.4, the necessary commit for guest side is
https://github.com/chenhuacai/linux/commit/f31b7c1284eb7cbeaa7728454ec6749065c12075
For upstream (mips-next), the necessary commit for guest side is
https://github.com/chenhuacai/linux/commit/56e7c7ea8eb2a6cab7037b64383e2e8faca88c02
>
> Thanks,
> Aleksandar
>
>
> > https://github.com/chenhuacai/linux
> >
> > How to use QEMU/Loongson-3?
> > 1, Download kernel source from the above URL;
> > 2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
> > 3, Boot the a Loongson-3A4000 host with this kernel;
> > 4, Build QEMU-master with this patchset;
> > 5, modprobe kvm;
> > 6, Use QEMU with TCG (available in future):
> > qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ...
> > Use QEMU with KVM (available at present):
> > qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ...
> >
> > The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically.
> >
> > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > ---
> > default-configs/mips64el-softmmu.mak | 1 +
> > hw/mips/Kconfig | 11 +
> > hw/mips/Makefile.objs | 1 +
> > hw/mips/loongson3_virt.c | 978 +++++++++++++++++++++++++++++++++++
> > 4 files changed, 991 insertions(+)
> > create mode 100644 hw/mips/loongson3_virt.c
> >
> > diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
> > index 9f8a3ef..26c660a 100644
> > --- a/default-configs/mips64el-softmmu.mak
> > +++ b/default-configs/mips64el-softmmu.mak
> > @@ -3,6 +3,7 @@
> > include mips-softmmu-common.mak
> > CONFIG_IDE_VIA=y
> > CONFIG_FULOONG=y
> > +CONFIG_LOONGSON3V=y
> > CONFIG_ATI_VGA=y
> > CONFIG_RTL8139_PCI=y
> > CONFIG_JAZZ=y
> > diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
> > index 67d39c5..cc5609b 100644
> > --- a/hw/mips/Kconfig
> > +++ b/hw/mips/Kconfig
> > @@ -45,6 +45,17 @@ config FULOONG
> > bool
> > select PCI_BONITO
> >
> > +config LOONGSON3V
> > + bool
> > + select PCKBD
> > + select SERIAL
> > + select GOLDFISH_RTC
> > + select LOONGSON_LIOINTC
> > + select PCI_EXPRESS_GENERIC_BRIDGE
> > + select VIRTIO_VGA
> > + select QXL if SPICE
> > + select MSI_NONBROKEN
> > +
> > config MIPS_CPS
> > bool
> > select PTIMER
> > diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
> > index 739e2b7..0993852 100644
> > --- a/hw/mips/Makefile.objs
> > +++ b/hw/mips/Makefile.objs
> > @@ -4,5 +4,6 @@ obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o
> > obj-$(CONFIG_MIPSSIM) += mipssim.o
> > obj-$(CONFIG_JAZZ) += jazz.o
> > obj-$(CONFIG_FULOONG) += fuloong2e.o
> > +obj-$(CONFIG_LOONGSON3V) += loongson3_virt.o
> > obj-$(CONFIG_MIPS_CPS) += cps.o
> > obj-$(CONFIG_MIPS_BOSTON) += boston.o
> > diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
> > new file mode 100644
> > index 0000000..e0e1939
> > --- /dev/null
> > +++ b/hw/mips/loongson3_virt.c
> > @@ -0,0 +1,978 @@
> > +/*
> > + * Generic Loongson-3 Platform support
> > + *
> > + * Copyright (c) 2016-2020 Huacai Chen (chenhc@lemote.com)
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation, either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> > + */
> > +
> > +/*
> > + * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
> > + * extensions, 800~2000MHz)
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu-common.h"
> > +#include "qemu/units.h"
> > +#include "qapi/error.h"
> > +#include "cpu.h"
> > +#include "elf.h"
> > +#include "kvm_mips.h"
> > +#include "hw/boards.h"
> > +#include "hw/char/serial.h"
> > +#include "hw/mips/mips.h"
> > +#include "hw/mips/cpudevs.h"
> > +#include "hw/misc/empty_slot.h"
> > +#include "hw/intc/i8259.h"
> > +#include "hw/loader.h"
> > +#include "hw/isa/superio.h"
> > +#include "hw/pci/msi.h"
> > +#include "hw/pci/pci.h"
> > +#include "hw/pci/pci_host.h"
> > +#include "hw/pci-host/gpex.h"
> > +#include "hw/rtc/mc146818rtc.h"
> > +#include "hw/usb.h"
> > +#include "net/net.h"
> > +#include "exec/address-spaces.h"
> > +#include "sysemu/kvm.h"
> > +#include "sysemu/qtest.h"
> > +#include "sysemu/reset.h"
> > +#include "sysemu/runstate.h"
> > +#include "qemu/log.h"
> > +#include "qemu/error-report.h"
> > +
> > +#define PM_CNTL_MODE 0x10
> > +
> > +/* Overall MMIO & Memory layout */
> > +enum {
> > + VIRT_LOWMEM,
> > + VIRT_PM,
> > + VIRT_FW_CFG,
> > + VIRT_RTC,
> > + VIRT_PCIE_PIO,
> > + VIRT_PCIE_ECAM,
> > + VIRT_BIOS_ROM,
> > + VIRT_UART,
> > + VIRT_LIOINTC,
> > + VIRT_PCIE_MMIO,
> > + VIRT_HIGHMEM
> > +};
> > +
> > +/* Low MEM layout for QEMU kernel loader */
> > +enum {
> > + LOADER_KERNEL,
> > + LOADER_INITRD,
> > + LOADER_CMDLINE
> > +};
> > +
> > +/* BIOS ROM layout for QEMU kernel loader */
> > +enum {
> > + LOADER_BOOTROM,
> > + LOADER_PARAM,
> > +};
> > +
> > +struct MemmapEntry {
> > + hwaddr base;
> > + hwaddr size;
> > +};
> > +
> > +/* Data for BIOS to identify machine */
> > +#define FW_CFG_MACHINE_VERSION (FW_CFG_ARCH_LOCAL + 0)
> > +#define FW_CFG_CPU_FREQ (FW_CFG_ARCH_LOCAL + 1)
> > +
> > +/*
> > + * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structrues
> > + * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux kernel
> > + */
> > +struct efi_memory_map_loongson {
> > + uint16_t vers; /* version of efi_memory_map */
> > + uint32_t nr_map; /* number of memory_maps */
> > + uint32_t mem_freq; /* memory frequence */
> > + struct mem_map {
> > + uint32_t node_id; /* node_id which memory attached to */
> > + uint32_t mem_type; /* system memory, pci memory, pci io, etc. */
> > + uint64_t mem_start; /* memory map start address */
> > + uint32_t mem_size; /* each memory_map size, not the total size */
> > + } map[128];
> > +} __attribute__((packed));
> > +
> > +enum loongson_cpu_type {
> > + Legacy_2E = 0x0,
> > + Legacy_2F = 0x1,
> > + Legacy_3A = 0x2,
> > + Legacy_3B = 0x3,
> > + Legacy_1A = 0x4,
> > + Legacy_1B = 0x5,
> > + Legacy_2G = 0x6,
> > + Legacy_2H = 0x7,
> > + Loongson_1A = 0x100,
> > + Loongson_1B = 0x101,
> > + Loongson_2E = 0x200,
> > + Loongson_2F = 0x201,
> > + Loongson_2G = 0x202,
> > + Loongson_2H = 0x203,
> > + Loongson_3A = 0x300,
> > + Loongson_3B = 0x301
> > +};
> > +
> > +/*
> > + * Capability and feature descriptor structure for MIPS CPU
> > + */
> > +struct efi_cpuinfo_loongson {
> > + uint16_t vers; /* version of efi_cpuinfo_loongson */
> > + uint32_t processor_id; /* PRID, e.g. 6305, 6306 */
> > + uint32_t cputype; /* Loongson_3A/3B, etc. */
> > + uint32_t total_node; /* num of total numa nodes */
> > + uint16_t cpu_startup_core_id; /* Boot core id */
> > + uint16_t reserved_cores_mask;
> > + uint32_t cpu_clock_freq; /* cpu_clock */
> > + uint32_t nr_cpus;
> > + char cpuname[64];
> > +} __attribute__((packed));
> > +
> > +#define MAX_UARTS 64
> > +struct uart_device {
> > + uint32_t iotype;
> > + uint32_t uartclk;
> > + uint32_t int_offset;
> > + uint64_t uart_base;
> > +} __attribute__((packed));
> > +
> > +#define MAX_SENSORS 64
> > +#define SENSOR_TEMPER 0x00000001
> > +#define SENSOR_VOLTAGE 0x00000002
> > +#define SENSOR_FAN 0x00000004
> > +struct sensor_device {
> > + char name[32]; /* a formal name */
> > + char label[64]; /* a flexible description */
> > + uint32_t type; /* SENSOR_* */
> > + uint32_t id; /* instance id of a sensor-class */
> > + uint32_t fan_policy; /* step speed or constant speed */
> > + uint32_t fan_percent;/* only for constant speed policy */
> > + uint64_t base_addr; /* base address of device registers */
> > +} __attribute__((packed));
> > +
> > +struct system_loongson {
> > + uint16_t vers; /* version of system_loongson */
> > + uint32_t ccnuma_smp; /* 0: no numa; 1: has numa */
> > + uint32_t sing_double_channel;/* 1: single; 2: double */
> > + uint32_t nr_uarts;
> > + struct uart_device uarts[MAX_UARTS];
> > + uint32_t nr_sensors;
> > + struct sensor_device sensors[MAX_SENSORS];
> > + char has_ec;
> > + char ec_name[32];
> > + uint64_t ec_base_addr;
> > + char has_tcm;
> > + char tcm_name[32];
> > + uint64_t tcm_base_addr;
> > + uint64_t workarounds;
> > + uint64_t of_dtb_addr; /* NULL if not support */
> > +} __attribute__((packed));
> > +
> > +struct irq_source_routing_table {
> > + uint16_t vers;
> > + uint16_t size;
> > + uint16_t rtr_bus;
> > + uint16_t rtr_devfn;
> > + uint32_t vendor;
> > + uint32_t device;
> > + uint32_t PIC_type; /* conform use HT or PCI to route to CPU-PIC */
> > + uint64_t ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
> > + uint64_t ht_enable; /* irqs used in this PIC */
> > + uint32_t node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
> > + uint64_t pci_mem_start_addr;
> > + uint64_t pci_mem_end_addr;
> > + uint64_t pci_io_start_addr;
> > + uint64_t pci_io_end_addr;
> > + uint64_t pci_config_addr;
> > + uint16_t dma_mask_bits;
> > + uint16_t dma_noncoherent;
> > +} __attribute__((packed));
> > +
> > +struct interface_info {
> > + uint16_t vers; /* version of the specificition */
> > + uint16_t size;
> > + uint8_t flag;
> > + char description[64];
> > +} __attribute__((packed));
> > +
> > +#define MAX_RESOURCE_NUMBER 128
> > +struct resource_loongson {
> > + uint64_t start; /* resource start address */
> > + uint64_t end; /* resource end address */
> > + char name[64];
> > + uint32_t flags;
> > +};
> > +
> > +struct archdev_data {}; /* arch specific additions */
> > +
> > +struct board_devices {
> > + char name[64]; /* hold the device name */
> > + uint32_t num_resources; /* number of device_resource */
> > + /* for each device's resource */
> > + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> > + /* arch specific additions */
> > + struct archdev_data archdata;
> > +};
> > +
> > +struct loongson_special_attribute {
> > + uint16_t vers; /* version of this special */
> > + char special_name[64]; /* special_atribute_name */
> > + uint32_t loongson_special_type; /* type of special device */
> > + /* for each device's resource */
> > + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> > +};
> > +
> > +struct loongson_params {
> > + uint64_t memory_offset; /* efi_memory_map_loongson struct offset */
> > + uint64_t cpu_offset; /* efi_cpuinfo_loongson struct offset */
> > + uint64_t system_offset; /* system_loongson struct offset */
> > + uint64_t irq_offset; /* irq_source_routing_table struct offset */
> > + uint64_t interface_offset; /* interface_info struct offset */
> > + uint64_t special_offset; /* loongson_special_attribute struct offset */
> > + uint64_t boarddev_table_offset; /* board_devices offset */
> > +};
> > +
> > +struct smbios_tables {
> > + uint16_t vers; /* version of smbios */
> > + uint64_t vga_bios; /* vga_bios address */
> > + struct loongson_params lp;
> > +};
> > +
> > +struct efi_reset_system_t {
> > + uint64_t ResetCold;
> > + uint64_t ResetWarm;
> > + uint64_t ResetType;
> > + uint64_t Shutdown;
> > + uint64_t DoSuspend; /* NULL if not support */
> > +};
> > +
> > +struct efi_loongson {
> > + uint64_t mps; /* MPS table */
> > + uint64_t acpi; /* ACPI table (IA64 ext 0.71) */
> > + uint64_t acpi20; /* ACPI table (ACPI 2.0) */
> > + struct smbios_tables smbios; /* SM BIOS table */
> > + uint64_t sal_systab; /* SAL system table */
> > + uint64_t boot_info; /* boot info table */
> > +};
> > +
> > +struct boot_params {
> > + struct efi_loongson efi;
> > + struct efi_reset_system_t reset_system;
> > +};
> > +
> > +#define LOONGSON_MAX_VCPUS 16
> > +
> > +#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
> > +
> > +#define UART_IRQ 0
> > +#define RTC_IRQ 1
> > +#define PCIE_IRQ_BASE 2
> > +
> > +#define align(x) (((x) + 63) & ~63)
> > +
> > +static const struct MemmapEntry virt_memmap[] = {
> > + [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
> > + [VIRT_PM] = { 0x10080000, 0x100 },
> > + [VIRT_FW_CFG] = { 0x10080100, 0x100 },
> > + [VIRT_RTC] = { 0x10081000, 0x1000 },
> > + [VIRT_PCIE_PIO] = { 0x18000000, 0xc0000 },
> > + [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
> > + [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
> > + [VIRT_UART] = { 0x1fe001e0, 0x8 },
> > + [VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
> > + [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
> > + [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
> > +};
> > +
> > +static const struct MemmapEntry loader_memmap[] = {
> > + [LOADER_KERNEL] = { 0x00000000, 0x4000000 },
> > + [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */
> > + [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 },
> > +};
> > +
> > +static const struct MemmapEntry loader_rommap[] = {
> > + [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 },
> > + [LOADER_PARAM] = { 0x1fc01000, 0x10000 },
> > +};
> > +
> > +static struct _loaderparams {
> > + uint64_t ram_size;
> > + const char *kernel_cmdline;
> > + const char *kernel_filename;
> > + const char *initrd_filename;
> > + uint64_t kernel_entry;
> > + uint64_t a0, a1, a2;
> > +} loaderparams;
> > +
> > +static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
> > +{
> > + return 0;
> > +}
> > +
> > +static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
> > +{
> > + if (addr != PM_CNTL_MODE) {
> > + return;
> > + }
> > +
> > + switch (val) {
> > + case 0x00:
> > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> > + return;
> > + case 0xff:
> > + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
> > + return;
> > + default:
> > + return;
> > + }
> > +}
> > +
> > +static const MemoryRegionOps loongson3_pm_ops = {
> > + .read = loongson3_pm_read,
> > + .write = loongson3_pm_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > +};
> > +
> > +static struct efi_memory_map_loongson *init_memory_map(void *g_map)
> > +{
> > + struct efi_memory_map_loongson *emap = g_map;
> > +
> > + emap->nr_map = 2;
> > + emap->mem_freq = 300000000;
> > +
> > + emap->map[0].node_id = 0;
> > + emap->map[0].mem_type = 1;
> > + emap->map[0].mem_start = 0x0;
> > + emap->map[0].mem_size = (loaderparams.ram_size > 0x10000000
> > + ? 256 : (loaderparams.ram_size >> 20)) - 16;
> > +
> > + emap->map[1].node_id = 0;
> > + emap->map[1].mem_type = 2;
> > + emap->map[1].mem_start = 0x90000000;
> > + emap->map[1].mem_size = (loaderparams.ram_size > 0x10000000
> > + ? (loaderparams.ram_size >> 20) - 256 : 0);
> > +
> > + return emap;
> > +}
> > +
> > +#define BUFLEN 1024
> > +
> > +static uint32_t get_cpu_freq(void)
> > +{
> > + int fd = 0, freq = 0;
> > + char buf[BUFLEN], *buf_p;
> > +
> > + fd = open("/proc/cpuinfo", O_RDONLY);
> > + if (fd == -1) {
> > + fprintf(stderr, "Failed to open /proc/cpuinfo!\n");
> > + return 0;
> > + }
> > +
> > + if (read(fd, buf, BUFLEN) < 0) {
> > + close(fd);
> > + fprintf(stderr, "Failed to read /proc/cpuinfo!\n");
> > + return 0;
> > + }
> > + close(fd);
> > +
> > + buf_p = strstr(buf, "model name");
> > + while (*buf_p != '@') {
> > + buf_p++;
> > + }
> > +
> > + buf_p += 2;
> > + memcpy(buf, buf_p, 12);
> > + buf_p = buf;
> > + while ((*buf_p >= '0') && (*buf_p <= '9')) {
> > + buf_p++;
> > + }
> > + *buf_p = '\0';
> > +
> > + freq = atoi(buf);
> > +
> > + return freq * 1000 * 1000;
> > +}
> > +
> > +static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo_loongson)
> > +{
> > + struct efi_cpuinfo_loongson *c = g_cpuinfo_loongson;
> > +
> > + c->cputype = Loongson_3A;
> > + c->processor_id = MIPS_CPU(first_cpu)->env.CP0_PRid;
> > + c->cpu_clock_freq = get_cpu_freq();
> > + if (!c->cpu_clock_freq) {
> > + c->cpu_clock_freq = 500000000;
> > + }
> > +
> > + c->cpu_startup_core_id = 0;
> > + c->nr_cpus = current_machine->smp.cpus;
> > + c->total_node = (current_machine->smp.cpus + 3) / 4;
> > +
> > + return c;
> > +}
> > +
> > +static struct system_loongson *init_system_loongson(void *g_system)
> > +{
> > + struct system_loongson *s = g_system;
> > +
> > + s->ccnuma_smp = 0;
> > + s->sing_double_channel = 1;
> > + s->nr_uarts = 1;
> > + s->uarts[0].iotype = 2;
> > + s->uarts[0].int_offset = 2;
> > + s->uarts[0].uartclk = 25000000; /* Random value */
> > + s->uarts[0].uart_base = virt_memmap[VIRT_UART].base;
> > +
> > + return s;
> > +}
> > +
> > +static struct irq_source_routing_table *init_irq_source(void *g_irq_source)
> > +{
> > + struct irq_source_routing_table *irq_info = g_irq_source;
> > +
> > + irq_info->node_id = 0;
> > + irq_info->PIC_type = 0;
> > + irq_info->dma_mask_bits = 64;
> > + irq_info->pci_mem_start_addr = virt_memmap[VIRT_PCIE_MMIO].base;
> > + irq_info->pci_mem_end_addr = virt_memmap[VIRT_PCIE_MMIO].base +
> > + virt_memmap[VIRT_PCIE_MMIO].size - 1;
> > + irq_info->pci_io_start_addr = virt_memmap[VIRT_PCIE_PIO].base;
> > +
> > + return irq_info;
> > +}
> > +
> > +static struct interface_info *init_interface_info(void *g_interface)
> > +{
> > + struct interface_info *interface = g_interface;
> > +
> > + interface->vers = 0x01;
> > + strcpy(interface->description, "UEFI_Version_v1.0");
> > +
> > + return interface;
> > +}
> > +
> > +static struct board_devices *board_devices_info(void *g_board)
> > +{
> > + struct board_devices *bd = g_board;
> > +
> > + strcpy(bd->name, "Loongson-3A-VIRT-1w-V1.00-demo");
> > +
> > + return bd;
> > +}
> > +
> > +static struct loongson_special_attribute *init_special_info(void *g_special)
> > +{
> > + struct loongson_special_attribute *special = g_special;
> > +
> > + strcpy(special->special_name, "2016-08-01");
> > +
> > + return special;
> > +}
> > +
> > +static void init_loongson_params(struct loongson_params *lp, void *p)
> > +{
> > + lp->memory_offset = (unsigned long long)init_memory_map(p)
> > + - (unsigned long long)lp;
> > + p += align(sizeof(struct efi_memory_map_loongson));
> > +
> > + lp->cpu_offset = (unsigned long long)init_cpu_info(p)
> > + - (unsigned long long)lp;
> > + p += align(sizeof(struct efi_cpuinfo_loongson));
> > +
> > + lp->system_offset = (unsigned long long)init_system_loongson(p)
> > + - (unsigned long long)lp;
> > + p += align(sizeof(struct system_loongson));
> > +
> > + lp->irq_offset = (unsigned long long)init_irq_source(p)
> > + - (unsigned long long)lp;
> > + p += align(sizeof(struct irq_source_routing_table));
> > +
> > + lp->interface_offset = (unsigned long long)init_interface_info(p)
> > + - (unsigned long long)lp;
> > + p += align(sizeof(struct interface_info));
> > +
> > + lp->boarddev_table_offset = (unsigned long long)board_devices_info(p)
> > + - (unsigned long long)lp;
> > + p += align(sizeof(struct board_devices));
> > +
> > + lp->special_offset = (unsigned long long)init_special_info(p)
> > + - (unsigned long long)lp;
> > + p += align(sizeof(struct loongson_special_attribute));
> > +}
> > +
> > +static void init_reset_system(struct efi_reset_system_t *reset)
> > +{
> > + reset->Shutdown = 0xffffffffbfc000a8;
> > + reset->ResetCold = 0xffffffffbfc00080;
> > + reset->ResetWarm = 0xffffffffbfc00080;
> > +}
> > +
> > +static void init_boot_param(void)
> > +{
> > + void *p;
> > + struct boot_params *bp;
> > +
> > + p = g_malloc0(loader_rommap[LOADER_PARAM].size);
> > + bp = p;
> > +
> > + bp->efi.smbios.vers = 1;
> > + init_reset_system(&(bp->reset_system));
> > + p += align(sizeof(struct boot_params));
> > + init_loongson_params(&(bp->efi.smbios.lp), p);
> > +
> > + rom_add_blob_fixed("params_rom", bp,
> > + loader_rommap[LOADER_PARAM].size,
> > + loader_rommap[LOADER_PARAM].base);
> > +
> > + g_free(bp);
> > +
> > + loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL,
> > + loader_rommap[LOADER_PARAM].base);
> > +}
> > +
> > +static void init_boot_rom(void)
> > +{
> > + const unsigned int boot_code[] = {
> > + 0x40086000, /* mfc0 t0, CP0_STATUS */
> > + 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */
> > + 0x01094025, /* or t0, t0, t1 */
> > + 0x3C090040, /* lui t1, 0x40 #set bev */
> > + 0x01094025, /* or t0, t0, t1 */
> > + 0x40886000, /* mtc0 t0, CP0_STATUS */
> > + 0x00000000,
> > + 0x40806800, /* mtc0 zero, CP0_CAUSE */
> > + 0x00000000,
> > + 0x400A7801, /* mfc0 t2, $15, 1 */
> > + 0x314A00FF, /* andi t2, 0x0ff */
> > + 0x3C089000, /* dli t0, 0x900000003ff01000 */
> > + 0x00084438,
> > + 0x35083FF0,
> > + 0x00084438,
> > + 0x35081000,
> > + 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */
> > + 0x000B5A00, /* sll t3, 8 */
> > + 0x010B4025, /* or t0, t0, t3 */
> > + 0x314C000C, /* andi t4, t2, 0xc #node id */
> > + 0x000C62BC, /* dsll t4, 42 */
> > + 0x010C4025, /* or t0, t0, t4 */
> > + /* WaitForInit: */
> > + 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */
> > + 0x1040FFFE, /* beqz v0, WaitForInit */
> > + 0x00000000, /* nop */
> > + 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */
> > + 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */
> > + 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */
> > + 0x00400008, /* jr v0 #byebye */
> > + 0x00000000, /* nop */
> > + 0x1000FFFF, /* 1: b 1b */
> > + 0x00000000, /* nop */
> > +
> > + /* Reset */
> > + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> > + 0x358C0000,
> > + 0x000C6438,
> > + 0x358C1008,
> > + 0x000C6438,
> > + 0x358C0010,
> > + 0x240D0000, /* li t1, 0x00 */
> > + 0xA18D0000, /* sb t1, (t0) */
> > + 0x1000FFFF, /* 1: b 1b */
> > + 0x00000000, /* nop */
> > +
> > + /* Shutdown */
> > + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> > + 0x358C0000,
> > + 0x000C6438,
> > + 0x358C1008,
> > + 0x000C6438,
> > + 0x358C0010,
> > + 0x240D00FF, /* li t1, 0xff */
> > + 0xA18D0000, /* sb t1, (t0) */
> > + 0x1000FFFF, /* 1: b 1b */
> > + 0x00000000 /* nop */
> > + };
> > +
> > + rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
> > + loader_rommap[LOADER_BOOTROM].base);
> > +}
> > +
> > +static void fw_cfg_boot_set(void *opaque, const char *boot_device,
> > + Error **errp)
> > +{
> > + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
> > +}
> > +
> > +static void fw_conf_init(unsigned long ram_size)
> > +{
> > + FWCfgState *fw_cfg;
> > + hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
> > +
> > + fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
> > + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
> > + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
> > + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> > + fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
> > + fw_cfg_add_i32(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq());
> > + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> > +}
> > +
> > +static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
> > +{
> > + hwaddr cmdline_vaddr;
> > + char memenv[32];
> > + char highmemenv[32];
> > + void *cmdline_buf;
> > + unsigned int *parg_env;
> > + int ret = 0;
> > +
> > + /* Allocate cmdline_buf for command line. */
> > + cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
> > + cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
> > + loader_memmap[LOADER_CMDLINE].base);
> > +
> > + /*
> > + * Layout of cmdline_buf looks like this:
> > + * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
> > + * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
> > + */
> > + parg_env = (void *)cmdline_buf;
> > +
> > + ret = (3 + 1) * 4;
> > + *parg_env++ = cmdline_vaddr + ret;
> > + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
> > +
> > + /* argv1 */
> > + *parg_env++ = cmdline_vaddr + ret;
> > + if (initrd_size > 0)
> > + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
> > + "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
> > + cpu_mips_phys_to_kseg0(NULL, initrd_offset),
> > + initrd_size, loaderparams.kernel_cmdline));
> > + else
> > + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
> > + loaderparams.kernel_cmdline));
> > +
> > + /* argv2 */
> > + *parg_env++ = cmdline_vaddr + 4 * ret;
> > +
> > + /* env */
> > + sprintf(memenv, "%ld", loaderparams.ram_size > 0x10000000
> > + ? 256 : (loaderparams.ram_size >> 20));
> > + sprintf(highmemenv, "%ld", loaderparams.ram_size > 0x10000000
> > + ? (loaderparams.ram_size >> 20) - 256 : 0);
> > +
> > + rom_add_blob_fixed("cmdline", cmdline_buf,
> > + loader_memmap[LOADER_CMDLINE].size,
> > + loader_memmap[LOADER_CMDLINE].base);
> > +
> > + g_free(cmdline_buf);
> > +
> > + loaderparams.a0 = 2;
> > + loaderparams.a1 = cmdline_vaddr;
> > +
> > + return 0;
> > +}
> > +
> > +static uint64_t load_kernel(CPUMIPSState *env)
> > +{
> > + long kernel_size;
> > + ram_addr_t initrd_offset;
> > + uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
> > +
> > + kernel_size = load_elf(loaderparams.kernel_filename, NULL,
> > + cpu_mips_kseg0_to_phys, NULL,
> > + (uint64_t *)&kernel_entry,
> > + (uint64_t *)&kernel_low, (uint64_t *)&kernel_high,
> > + NULL, 0, EM_MIPS, 1, 0);
> > + if (kernel_size < 0) {
> > + error_report("could not load kernel '%s': %s",
> > + loaderparams.kernel_filename,
> > + load_elf_strerror(kernel_size));
> > + exit(1);
> > + }
> > +
> > + /* load initrd */
> > + initrd_size = 0;
> > + initrd_offset = 0;
> > + if (loaderparams.initrd_filename) {
> > + initrd_size = get_image_size(loaderparams.initrd_filename);
> > + if (initrd_size > 0) {
> > + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
> > + INITRD_PAGE_MASK;
> > + initrd_offset = MAX(initrd_offset,
> > + loader_memmap[LOADER_INITRD].base);
> > +
> > + if (initrd_offset + initrd_size > ram_size) {
> > + error_report("memory too small for initial ram disk '%s'",
> > + loaderparams.initrd_filename);
> > + exit(1);
> > + }
> > +
> > + initrd_size = load_image_targphys(loaderparams.initrd_filename,
> > + initrd_offset,
> > + ram_size - initrd_offset);
> > + }
> > +
> > + if (initrd_size == (target_ulong) -1) {
> > + error_report("could not load initial ram disk '%s'",
> > + loaderparams.initrd_filename);
> > + exit(1);
> > + }
> > + }
> > +
> > + /* Setup prom cmdline. */
> > + set_prom_cmdline(initrd_offset, initrd_size);
> > +
> > + return kernel_entry;
> > +}
> > +
> > +static void main_cpu_reset(void *opaque)
> > +{
> > + MIPSCPU *cpu = opaque;
> > + CPUMIPSState *env = &cpu->env;
> > +
> > + cpu_reset(CPU(cpu));
> > +
> > + /* Loongson-3 reset stuff */
> > + if (loaderparams.kernel_filename) {
> > + if (cpu == MIPS_CPU(first_cpu)) {
> > + env->active_tc.gpr[4] = loaderparams.a0;
> > + env->active_tc.gpr[5] = loaderparams.a1;
> > + env->active_tc.gpr[6] = loaderparams.a2;
> > + env->active_tc.PC = loaderparams.kernel_entry;
> > + }
> > + env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
> > + }
> > +}
> > +
> > +static inline void loongson3_virt_devices_init(MachineState *machine, DeviceState *pic)
> > +{
> > + int i;
> > + qemu_irq irq;
> > + PCIBus *pci_bus;
> > + DeviceState *dev;
> > + MemoryRegion *pio_alias;
> > + MemoryRegion *mmio_alias, *mmio_reg;
> > + MemoryRegion *ecam_alias, *ecam_reg;
> > +
> > + dev = qdev_new(TYPE_GPEX_HOST);
> > + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> > + pci_bus = PCI_HOST_BRIDGE(dev)->bus;
> > +
> > + ecam_alias = g_new0(MemoryRegion, 1);
> > + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> > + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
> > + ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
> > + memory_region_add_subregion(get_system_memory(),
> > + virt_memmap[VIRT_PCIE_ECAM].base, ecam_alias);
> > +
> > + mmio_alias = g_new0(MemoryRegion, 1);
> > + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
> > + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
> > + mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
> > + virt_memmap[VIRT_PCIE_MMIO].size);
> > + memory_region_add_subregion(get_system_memory(),
> > + virt_memmap[VIRT_PCIE_MMIO].base, mmio_alias);
> > +
> > + pio_alias = g_new0(MemoryRegion, 1);
> > + memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
> > + get_system_io(), 0, virt_memmap[VIRT_PCIE_PIO].size);
> > + memory_region_add_subregion(get_system_memory(),
> > + virt_memmap[VIRT_PCIE_PIO].base, pio_alias);
> > + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
> > +
> > + for (i = 0; i < GPEX_NUM_IRQS; i++) {
> > + irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
> > + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
> > + }
> > +
> > + pci_vga_init(pci_bus);
> > +
> > + if (defaults_enabled()) {
> > + pci_create_simple(pci_bus, -1, "pci-ohci");
> > + usb_create_simple(usb_bus_find(-1), "usb-kbd");
> > + usb_create_simple(usb_bus_find(-1), "usb-tablet");
> > + }
> > +
> > + for (i = 0; i < nb_nics; i++) {
> > + NICInfo *nd = &nd_table[i];
> > +
> > + if (!nd->model) {
> > + nd->model = g_strdup("virtio");
> > + }
> > +
> > + pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
> > + }
> > +}
> > +
> > +static void mips_loongson3_virt_init(MachineState *machine)
> > +{
> > + int i;
> > + long bios_size;
> > + MIPSCPU *cpu;
> > + CPUMIPSState *env;
> > + DeviceState *liointc;
> > + char *filename;
> > + const char *kernel_cmdline = machine->kernel_cmdline;
> > + const char *kernel_filename = machine->kernel_filename;
> > + const char *initrd_filename = machine->initrd_filename;
> > + ram_addr_t ram_size = machine->ram_size;
> > + MemoryRegion *address_space_mem = get_system_memory();
> > + MemoryRegion *ram = g_new(MemoryRegion, 1);
> > + MemoryRegion *bios = g_new(MemoryRegion, 1);
> > + MemoryRegion *iomem = g_new(MemoryRegion, 1);
> > +
> > + /* TODO: TCG will support all CPU types */
> > + if (!kvm_enabled()) {
> > + if (!machine->cpu_type) {
> > + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
> > + }
> > + if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
> > + error_report("Loongson-3/TCG need cpu type Loongson-3A1000");
> > + exit(1);
> > + }
> > + } else {
> > + if (!machine->cpu_type) {
> > + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
> > + }
> > + if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
> > + error_report("Loongson-3/KVM need cpu type Loongson-3A4000");
> > + exit(1);
> > + }
> > + }
> > +
> > + if (ram_size < 512 * 0x100000) {
> > + error_report("Loongson-3 need at least 512MB memory");
> > + exit(1);
> > + }
> > +
> > + /*
> > + * The whole MMIO range among configure registers doesn't generate
> > + * exception when accessing invalid memory. Create an empty slot to
> > + * emulate this feature.
> > + */
> > + empty_slot_init("fallback", 0, 0x80000000);
> > +
> > + liointc = qdev_new("loongson.liointc");
> > + sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
> > +
> > + sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
> > +
> > + for (i = 0; i < machine->smp.cpus; i++) {
> > + int ip;
> > +
> > + /* init CPUs */
> > + cpu = MIPS_CPU(cpu_create(machine->cpu_type));
> > +
> > + /* Init internal devices */
> > + cpu_mips_irq_init_cpu(cpu);
> > + cpu_mips_clock_init(cpu);
> > + qemu_register_reset(main_cpu_reset, cpu);
> > +
> > + if (i >= 4) {
> > + continue; /* Only node-0 can be connected to LIOINTC */
> > + }
> > +
> > + for (ip = 0; ip < 4 ; ip++) {
> > + int pin = i * 4 + ip;
> > + sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
> > + pin, cpu->env.irq[ip + 2]);
> > + }
> > + }
> > + env = &MIPS_CPU(first_cpu)->env;
> > +
> > + /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
> > + memory_region_init_rom(bios, NULL, "loongson3.bios",
> > + virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
> > + memory_region_init_alias(ram, NULL, "loongson3.lowmem",
> > + machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
> > + memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
> > + NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
> > +
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_LOWMEM].base, ram);
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_BIOS_ROM].base, bios);
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_HIGHMEM].base, machine->ram);
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_PM].base, iomem);
> > +
> > + /*
> > + * We do not support flash operation, just loading bios.bin as raw BIOS.
> > + * Please use -L to set the BIOS path and -bios to set bios name.
> > + */
> > +
> > + if (kernel_filename) {
> > + loaderparams.ram_size = ram_size;
> > + loaderparams.kernel_filename = kernel_filename;
> > + loaderparams.kernel_cmdline = kernel_cmdline;
> > + loaderparams.initrd_filename = initrd_filename;
> > + loaderparams.kernel_entry = load_kernel(env);
> > +
> > + init_boot_rom();
> > + init_boot_param();
> > + } else {
> > + if (bios_name == NULL) {
> > + bios_name = LOONGSON3_BIOSNAME;
> > + }
> > + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> > + if (filename) {
> > + bios_size = load_image_targphys(filename,
> > + virt_memmap[VIRT_BIOS_ROM].base,
> > + virt_memmap[VIRT_BIOS_ROM].size);
> > + g_free(filename);
> > + } else {
> > + bios_size = -1;
> > + }
> > +
> > + if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
> > + !kernel_filename && !qtest_enabled()) {
> > + error_report("Could not load MIPS bios '%s'", bios_name);
> > + exit(1);
> > + }
> > +
> > + fw_conf_init(ram_size);
> > + }
> > +
> > + msi_nonbroken = true;
> > + loongson3_virt_devices_init(machine, liointc);
> > +
> > + sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
> > + qdev_get_gpio_in(liointc, RTC_IRQ));
> > +
> > + if (serial_hd(0)) {
> > + serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
> > + qdev_get_gpio_in(liointc, UART_IRQ), 115200,
> > + serial_hd(0), DEVICE_NATIVE_ENDIAN);
> > + }
> > +}
> > +
> > +static void mips_loongson3_virt_machine_init(MachineClass *mc)
> > +{
> > + mc->desc = "Loongson-3 Virtualization Platform";
> > + mc->init = mips_loongson3_virt_init;
> > + mc->block_default_type = IF_IDE;
> > + mc->max_cpus = LOONGSON_MAX_VCPUS;
> > + mc->default_ram_id = "loongson3.highram";
> > + /* 1500MB is the requirement of distros for Loongson-3 */
> > + mc->default_ram_size = 1500 * MiB;
> > + mc->kvm_type = mips_kvm_type;
> > + mc->minimum_page_bits = 14;
> > +}
> > +
> > +DEFINE_MACHINE("loongson3-virt", mips_loongson3_virt_machine_init)
> > --
> > 2.7.0
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass
2020-06-24 10:45 ` [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass Huacai Chen
2020-06-25 12:31 ` Aleksandar Markovic
@ 2020-06-27 17:51 ` Aleksandar Markovic
1 sibling, 0 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-27 17:51 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
QEMU Developers, Aleksandar Markovic, Huacai Chen,
Aurelien Jarno
On Wed, Jun 24, 2020 at 12:44 PM Huacai Chen <zltjiangshi@gmail.com> wrote:
>
> MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we
> can't create a VZ guest in QEMU because it lacks the kvm_type() hook in
> MachineClass. This patch add the the kvm_type() hook to support both of
> the two types.
>
> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
Applied to MIPS queue, with some minor changes.
> target/mips/kvm.c | 20 ++++++++++++++++++++
> target/mips/kvm_mips.h | 11 +++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/target/mips/kvm.c b/target/mips/kvm.c
> index 96cfa10..373f582 100644
> --- a/target/mips/kvm.c
> +++ b/target/mips/kvm.c
> @@ -21,10 +21,12 @@
> #include "qemu/main-loop.h"
> #include "qemu/timer.h"
> #include "sysemu/kvm.h"
> +#include "sysemu/kvm_int.h"
> #include "sysemu/runstate.h"
> #include "sysemu/cpus.h"
> #include "kvm_mips.h"
> #include "exec/memattrs.h"
> +#include "hw/boards.h"
>
> #define DEBUG_KVM 0
>
> @@ -1270,3 +1272,21 @@ int kvm_arch_msi_data_to_gsi(uint32_t data)
> {
> abort();
> }
> +
> +int mips_kvm_type(MachineState *machine, const char *vm_type)
> +{
> + int r;
> + KVMState *s = KVM_STATE(machine->accelerator);
> +
> + r = kvm_check_extension(s, KVM_CAP_MIPS_VZ);
> + if (r > 0) {
> + return KVM_VM_MIPS_VZ;
> + }
> +
> + r = kvm_check_extension(s, KVM_CAP_MIPS_TE);
> + if (r > 0) {
> + return KVM_VM_MIPS_TE;
> + }
> +
> + return -1;
> +}
> diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h
> index 1e40147..171d53d 100644
> --- a/target/mips/kvm_mips.h
> +++ b/target/mips/kvm_mips.h
> @@ -12,6 +12,8 @@
> #ifndef KVM_MIPS_H
> #define KVM_MIPS_H
>
> +#include "cpu.h"
> +
> /**
> * kvm_mips_reset_vcpu:
> * @cpu: MIPSCPU
> @@ -23,4 +25,13 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu);
> int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level);
> int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level);
>
> +#ifdef CONFIG_KVM
> +int mips_kvm_type(MachineState *machine, const char *vm_type);
> +#else
> +static inline int mips_kvm_type(MachineState *machine, const char *vm_type)
> +{
> + return 0;
> +}
> +#endif
> +
> #endif /* KVM_MIPS_H */
> --
> 2.7.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer
2020-06-24 10:45 ` [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer Huacai Chen
2020-06-25 10:41 ` Aleksandar Markovic
@ 2020-06-27 17:53 ` Aleksandar Markovic
1 sibling, 0 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-27 17:53 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
QEMU Developers, Aleksandar Markovic, Huacai Chen,
Aurelien Jarno
On Wed, Jun 24, 2020 at 12:46 PM Huacai Chen <zltjiangshi@gmail.com> wrote:
>
> Add myself as a maintainer of Loongson-3 virtual platform, and also add
> Jiaxun Yang as a reviewer.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
Applied to MIPS queue, for now without one of two files mentioned in
the section "Loongson-3 Virtual Platform". Also, "Loongson-3 Virtual Platform"
is changed to "Loongson-3 virtual platforms" to allow future extensions.
> MAINTAINERS | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 51a4570..0226a74 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1095,6 +1095,13 @@ F: hw/isa/vt82c686.c
> F: hw/pci-host/bonito.c
> F: include/hw/isa/vt82c686.h
>
> +Loongson-3 Virtual Platform
> +M: Huacai Chen <chenhc@lemote.com>
> +R: Jiaxun Yang <jiaxun.yang@flygoat.com>
> +S: Maintained
> +F: hw/mips/loongson3_virt.c
> +F: hw/intc/loongson_liointc.c
> +
> Boston
> M: Paul Burton <pburton@wavecomp.com>
> R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
> --
> 2.7.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V6 2/4] hw/intc: Add Loongson liointc support
2020-06-24 10:45 ` [PATCH V6 2/4] hw/intc: Add Loongson liointc support Huacai Chen
2020-06-25 10:35 ` Aleksandar Markovic
@ 2020-06-27 17:54 ` Aleksandar Markovic
1 sibling, 0 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-27 17:54 UTC (permalink / raw)
To: Huacai Chen
Cc: Aleksandar Rikalo, Huacai Chen, Philippe Mathieu-Daudé,
Jiaxun Yang, QEMU Developers, Aleksandar Markovic, Huacai Chen,
Aurelien Jarno
On Wed, Jun 24, 2020 at 12:48 PM Huacai Chen <zltjiangshi@gmail.com> wrote:
>
> Loongson-3 has an integrated liointc (Local I/O interrupt controller).
> It is similar to goldfish interrupt controller, but more powerful (e.g.,
> it can route external interrupt to multi-cores).
>
> Documents about Loongson-3's liointc:
> 1, https://wiki.godson.ac.cn/ip_block:liointc;
> 2, The "I/O中断" section of Loongson-3's user mannual, part 1.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
Applied to MIPS QUEUE, with some purely cosmetic changes.
> hw/intc/Kconfig | 3 +
> hw/intc/Makefile.objs | 1 +
> hw/intc/loongson_liointc.c | 241 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 245 insertions(+)
> create mode 100644 hw/intc/loongson_liointc.c
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f562342..2ae1e89 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -64,3 +64,6 @@ config OMPIC
>
> config RX_ICU
> bool
> +
> +config LOONGSON_LIOINTC
> + bool
> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> index a420263..3ac2b40 100644
> --- a/hw/intc/Makefile.objs
> +++ b/hw/intc/Makefile.objs
> @@ -51,3 +51,4 @@ obj-$(CONFIG_MIPS_CPS) += mips_gic.o
> obj-$(CONFIG_NIOS2) += nios2_iic.o
> obj-$(CONFIG_OMPIC) += ompic.o
> obj-$(CONFIG_IBEX) += ibex_plic.o
> +obj-$(CONFIG_LOONGSON_LIOINTC) += loongson_liointc.o
> diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c
> new file mode 100644
> index 0000000..e39e39e
> --- /dev/null
> +++ b/hw/intc/loongson_liointc.c
> @@ -0,0 +1,241 @@
> +/*
> + * QEMU Loongson Local I/O interrupt controler.
> + *
> + * Copyright (c) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "qemu/module.h"
> +#include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> +
> +#define D(x)
> +
> +#define NUM_IRQS 32
> +
> +#define NUM_CORES 4
> +#define NUM_IPS 4
> +#define NUM_PARENTS (NUM_CORES * NUM_IPS)
> +#define PARENT_COREx_IPy(x, y) (NUM_IPS * x + y)
> +
> +#define R_MAPPER_START 0x0
> +#define R_MAPPER_END 0x20
> +#define R_ISR R_MAPPER_END
> +#define R_IEN 0x24
> +#define R_IEN_SET 0x28
> +#define R_IEN_CLR 0x2c
> +#define R_PERCORE_ISR(x) (0x40 + 0x8 * x)
> +#define R_END 0x64
> +
> +#define TYPE_LOONGSON_LIOINTC "loongson.liointc"
> +#define LOONGSON_LIOINTC(obj) \
> + OBJECT_CHECK(struct loongson_liointc, (obj), TYPE_LOONGSON_LIOINTC)
> +
> +struct loongson_liointc {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> + qemu_irq parent_irq[NUM_PARENTS];
> +
> + uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */
> + uint32_t isr;
> + uint32_t ien;
> + uint32_t per_core_isr[NUM_CORES];
> +
> + /* state of the interrupt input pins */
> + uint32_t pin_state;
> + bool parent_state[NUM_PARENTS];
> +};
> +
> +static void update_irq(struct loongson_liointc *p)
> +{
> + uint32_t irq, core, ip;
> + uint32_t per_ip_isr[NUM_IPS] = {0};
> +
> + /* level triggered interrupt */
> + p->isr = p->pin_state;
> +
> + /* Clear disabled IRQs */
> + p->isr &= p->ien;
> +
> + /* Clear per_core_isr */
> + for (core = 0; core < NUM_CORES; core++) {
> + p->per_core_isr[core] = 0;
> + }
> +
> + /* Update per_core_isr and per_ip_isr */
> + for (irq = 0; irq < NUM_IRQS; irq++) {
> + if (!(p->isr & (1 << irq))) {
> + continue;
> + }
> +
> + for (core = 0; core < NUM_CORES; core++) {
> + if ((p->mapper[irq] & (1 << core))) {
> + p->per_core_isr[core] |= (1 << irq);
> + }
> + }
> +
> + for (ip = 0; ip < NUM_IPS; ip++) {
> + if ((p->mapper[irq] & (1 << (ip + 4)))) {
> + per_ip_isr[ip] |= (1 << irq);
> + }
> + }
> + }
> +
> + /* Emit IRQ to parent! */
> + for (core = 0; core < NUM_CORES; core++) {
> + for (ip = 0; ip < NUM_IPS; ip++) {
> + int parent = PARENT_COREx_IPy(core, ip);
> + if (p->parent_state[parent] !=
> + (!!p->per_core_isr[core] && !!per_ip_isr[ip])) {
> + p->parent_state[parent] = !p->parent_state[parent];
> + qemu_set_irq(p->parent_irq[parent], p->parent_state[parent]);
> + }
> + }
> + }
> +}
> +
> +static uint64_t
> +liointc_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + struct loongson_liointc *p = opaque;
> + uint32_t r = 0;
> +
> + /* Mapper is 1 byte */
> + if (size == 1 && addr < R_MAPPER_END) {
> + r = p->mapper[addr];
> + goto out;
> + }
> +
> + /* Rest is 4 byte */
> + if (size != 4 || (addr % 4)) {
> + goto out;
> + }
> +
> + if (addr >= R_PERCORE_ISR(0) &&
> + addr < R_PERCORE_ISR(NUM_CORES)) {
> + int core = (addr - R_PERCORE_ISR(0)) / 4;
> + r = p->per_core_isr[core];
> + goto out;
> + }
> +
> + switch (addr) {
> + case R_ISR:
> + r = p->isr;
> + break;
> + case R_IEN:
> + r = p->ien;
> + break;
> + default:
> + break;
> + }
> +
> +out:
> + D(qemu_log("%s: size=%d addr=%lx val=%x\n", __func__, size, addr, r));
> + return r;
> +}
> +
> +static void
> +liointc_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + struct loongson_liointc *p = opaque;
> + uint32_t value = val64;
> +
> + D(qemu_log("%s: size=%d, addr=%lx val=%x\n", __func__, size, addr, value));
> +
> + /* Mapper is 1 byte */
> + if (size == 1 && addr < R_MAPPER_END) {
> + p->mapper[addr] = value;
> + goto out;
> + }
> +
> + /* Rest is 4 byte */
> + if (size != 4 || (addr % 4)) {
> + goto out;
> + }
> +
> + if (addr >= R_PERCORE_ISR(0) &&
> + addr < R_PERCORE_ISR(NUM_CORES)) {
> + int core = (addr - R_PERCORE_ISR(0)) / 4;
> + p->per_core_isr[core] = value;
> + goto out;
> + }
> +
> + switch (addr) {
> + case R_IEN_SET:
> + p->ien |= value;
> + break;
> + case R_IEN_CLR:
> + p->ien &= ~value;
> + break;
> + default:
> + break;
> + }
> +
> +out:
> + update_irq(p);
> +}
> +
> +static const MemoryRegionOps pic_ops = {
> + .read = liointc_read,
> + .write = liointc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4
> + }
> +};
> +
> +static void irq_handler(void *opaque, int irq, int level)
> +{
> + struct loongson_liointc *p = opaque;
> +
> + p->pin_state &= ~(1 << irq);
> + p->pin_state |= level << irq;
> + update_irq(p);
> +}
> +
> +static void loongson_liointc_init(Object *obj)
> +{
> + struct loongson_liointc *p = LOONGSON_LIOINTC(obj);
> + int i;
> +
> + qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
> +
> + for (i = 0; i < NUM_PARENTS; i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq[i]);
> + }
> +
> + memory_region_init_io(&p->mmio, obj, &pic_ops, p,
> + "loongson.liointc", R_END);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
> +}
> +
> +static const TypeInfo loongson_liointc_info = {
> + .name = TYPE_LOONGSON_LIOINTC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(struct loongson_liointc),
> + .instance_init = loongson_liointc_init,
> +};
> +
> +static void loongson_liointc_register_types(void)
> +{
> + type_register_static(&loongson_liointc_info);
> +}
> +
> +type_init(loongson_liointc_register_types)
> --
> 2.7.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-06-27 17:55 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-24 10:45 [PATCH V6 0/4] mips: Add Loongson-3 machine support (with KVM) Huacai Chen
2020-06-24 10:45 ` [PATCH V6 1/4] hw/mips: Implement the kvm_type() hook in MachineClass Huacai Chen
2020-06-25 12:31 ` Aleksandar Markovic
2020-06-25 13:25 ` Aleksandar Markovic
2020-06-27 17:51 ` Aleksandar Markovic
2020-06-24 10:45 ` [PATCH V6 2/4] hw/intc: Add Loongson liointc support Huacai Chen
2020-06-25 10:35 ` Aleksandar Markovic
2020-06-27 17:54 ` Aleksandar Markovic
2020-06-24 10:45 ` [PATCH V6 3/4] hw/mips: Add Loongson-3 machine support (with KVM) Huacai Chen
2020-06-24 11:50 ` Aleksandar Markovic
2020-06-26 11:30 ` Huacai Chen
2020-06-24 10:45 ` [PATCH V6 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer Huacai Chen
2020-06-25 10:41 ` Aleksandar Markovic
2020-06-27 17:53 ` Aleksandar Markovic
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