Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

[Michael Rolnik <mrolnik@gmail.com>]

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Aleksandar.

enjoy your vacation.

Regards,
Michael Rolnik

On Tue, Dec 3, 2019 at 3:48 AM Aleksandar Markovic <
aleksandar.m.mail@gmail.com> wrote:

>
>
> On Tuesday, December 3, 2019, Aleksandar Markovic <
> aleksandar.m.mail@gmail.com> wrote:
>
>>
>>
>> On Tuesday, December 3, 2019, Aleksandar Markovic <
>> aleksandar.m.mail@gmail.com> wrote:
>>
>>>
>>>
>>> On Monday, December 2, 2019, Aleksandar Markovic <
>>> aleksandar.m.mail@gmail.com> wrote:
>>>
>>>>
>>>>
>>>> On Monday, December 2, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:
>>>>
>>>>> how can I get this elf flags from within QEMU?
>>>>>
>>>>>>
>>>>>>
>>>> In one of files from your "machine" patch, you have this snippet:
>>>>
>>>> +        bytes_loaded = load_elf(
>>>> +            filename, NULL, NULL, NULL, NULL, NULL, NULL, 0, EM_NONE,
>>>> 0, 0);
>>>>
>>>> With this line you a kind of "blindly" load whatever you find in the
>>>> file "filename". I think you need to modify load_elf() to fetch the
>>>> information on what core the elf in question is compiled for. Additionally,
>>>> you most likely have to check if the elf file is compiled for AVR at all.
>>>>
>>>> I don't know enough about AVR-specifics of ELF format, but I know that
>>>> we in MIPS read successfuly some MIPS-specific things we need to know. Do
>>>> some research for ELF format headrr content for AVR.
>>>>
>>>> This is really missing in your series, seriously.
>>>>
>>>> Please keep in mind that I don't have right now at hand any dev system,
>>>> so all I said here is off of my head.
>>>>
>>>> You have to do some code digging.
>>>>
>>>>
>>> First, you need to update
>>>
>>> https://github.com/qemu/qemu/blob/master/include/elf.h
>>>
>>> with bits and pieces for AVR.
>>>
>>> In binutils file:
>>>
>>> https://github.com/bminor/binutils-gdb/blob/master/include/elf/common.h
>>>
>>> you will spot the line:
>>>
>>> #define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */
>>>
>>> that is the value of e_machine field for AVR, which you need to insert
>>> in qemu's include/elf.h about at line 162.
>>>
>>> Then, in another binutils file:
>>>
>>> https://github.com/bminor/binutils-gdb/blob/master/include/elf/avr.h
>>>
>>> you find the lines:
>>>
>>> #define E_AVR_MACH_AVR1 1
>>> #define E_AVR_MACH_AVR2 2
>>> #define E_AVR_MACH_AVR25 25
>>> #define E_AVR_MACH_AVR3 3
>>> #define E_AVR_MACH_AVR31 31
>>> #define E_AVR_MACH_AVR35 35
>>> #define E_AVR_MACH_AVR4 4
>>> #define E_AVR_MACH_AVR5 5
>>> #define E_AVR_MACH_AVR51 51
>>> #define E_AVR_MACH_AVR6 6
>>> #define E_AVR_MACH_AVRTINY 100
>>> #define E_AVR_MACH_XMEGA1 101
>>> #define E_AVR_MACH_XMEGA2 102
>>> #define E_AVR_MACH_XMEGA3 103
>>> #define E_AVR_MACH_XMEGA4 104
>>> #define E_AVR_MACH_XMEGA5 105
>>> #define E_AVR_MACH_XMEGA6 106
>>> #define E_AVR_MACH_XMEGA7 107
>>>
>>> That you also need to insert in qemu's include/elf.h, probably at the
>>> end of tge foke or elsewhere.
>>>
>>> Perhaps something more you need to insert into that file, you'll see.
>>>
>>> Than, you need to modify the file where load_elf() resides with AVR
>>> support, take a look at other architectures' support, and adjust to what
>>> you need.
>>>
>>> I know it will be contrieved at times, but, personally, similar ELF
>>> support must be done for any upcoming platform. Only if there is some
>>> unsourmantable obstacle, that support can be omitted.
>>>
>>> I am on vacation next 10 days.
>>>
>>>
>> In the source of readelf utility:
>>
>>
>> static void
>> decode_AVR_machine_flags (unsigned e_flags, char buf[], size_t size)
>> {
>>   --size; /* Leave space for null terminator.  */
>>
>>   switch (e_flags & EF_AVR_MACH)
>>     {
>>     case E_AVR_MACH_AVR1:
>>       strncat (buf, ", avr:1", size);
>>       break;
>>     case E_AVR_MACH_AVR2:
>>       strncat (buf, ", avr:2", size);
>>       break;
>>     case E_AVR_MACH_AVR25:
>>       strncat (buf, ", avr:25", size);
>>       break;
>>     case E_AVR_MACH_AVR3:
>>       strncat (buf, ", avr:3", size);
>>       break;
>>     case E_AVR_MACH_AVR31:
>>       strncat (buf, ", avr:31", size);
>>       break;
>>     case E_AVR_MACH_AVR35:
>>       strncat (buf, ", avr:35", size);
>>       break;
>>     case E_AVR_MACH_AVR4:
>>       strncat (buf, ", avr:4", size);
>>       break;
>>     case E_AVR_MACH_AVR5:
>>       strncat (buf, ", avr:5", size);
>>       break;
>>     case E_AVR_MACH_AVR51:
>>       strncat (buf, ", avr:51", size);
>>       break;
>>     case E_AVR_MACH_AVR6:
>>       strncat (buf, ", avr:6", size);
>>       break;
>>     case E_AVR_MACH_AVRTINY:
>>       strncat (buf, ", avr:100", size);
>>       break;
>>     case E_AVR_MACH_XMEGA1:
>>       strncat (buf, ", avr:101", size);
>>       break;
>>     case E_AVR_MACH_XMEGA2:
>>       strncat (buf, ", avr:102", size);
>>       break;
>>     case E_AVR_MACH_XMEGA3:
>>       strncat (buf, ", avr:103", size);
>>       break;
>>     case E_AVR_MACH_XMEGA4:
>>       strncat (buf, ", avr:104", size);
>>       break;
>>     case E_AVR_MACH_XMEGA5:
>>       strncat (buf, ", avr:105", size);
>>       break;
>>     case E_AVR_MACH_XMEGA6:
>>       strncat (buf, ", avr:106", size);
>>       break;
>>     case E_AVR_MACH_XMEGA7:
>>       strncat (buf, ", avr:107", size);
>>       break;
>>     default:
>>       strncat (buf, ", avr:<unknown>", size);
>>       break;
>>     }
>>
>>
>> So, it looks, for 8-bit AVR, e_machine must be 83 (EM_AVR), while e_flags
>> is one of E_AVR_MACH_XXX constants. You just need to store somewhere
>> E_AVR_MACH_XXX that you read from given ELF file, and compare it with core
>> specified by "-cpu" command line option.
>>
>>
> Looking further into the code, it looks that load_elf() that you use to
> load given AVR elf file is simply not suitable for reading info you wanr.
> That is because that function is used for loading kernels for other
> platforms, and AVR case is quite different you load an executable.
>
> You may want to write your own version of load_elf(), called let's say
> load_elf_avr() (but place it in AVR-specific location), that will load elf,
> but aso read e_machine and e_flags fields that you will later pass to
> appropriate logic, compare with "-cpu" given core, and decide further what
> to do.
>
> Please take all my advices with reservation, I am writing without a
> computer dev system.
>
> I am off on vacation!
>
> Take care!
>
> Aleksandar
>
>
>>
>>> Yours,
>>> Aleksandar
>>>
>>> .
>>>
>>>> Best regards, Aleksandar
>>>>
>>>>
>>>>> On Mon, Dec 2, 2019 at 4:01 PM Aleksandar Markovic <
>>>>> aleksandar.m.mail@gmail.com> wrote:
>>>>>
>>>>>>
>>>>>>
>>>>>> On Monday, December 2, 2019, Michael Rolnik <mrolnik@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> No, I don't.
>>>>>>> but I also can load and execute a binary file which does not have
>>>>>>> this information.
>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>> OK. Let's think about that for a while. I currently think you have
>>>>>> here an opportunity to add a really clean interface from the outset of AVR
>>>>>> support in QEMU (that even some established platforms don't have in full),
>>>>>> which is, trust me, very important for future. And it not that difficult to
>>>>>> implement at all. But let's both think for a while.
>>>>>>
>>>>>> Best regards,
>>>>>> Aleksandar
>>>>>>
>>>>>>
>>>>>>
>>>>>>> On Mon, Dec 2, 2019 at 11:59 AM Aleksandar Markovic <
>>>>>>> aleksandar.m.mail@gmail.com> wrote:
>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On Monday, December 2, 2019, Aleksandar Markovic <
>>>>>>>> aleksandar.m.mail@gmail.com> wrote:
>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On Saturday, November 30, 2019, Michael Rolnik <mrolnik@gmail.com>
>>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>>> There is *-cpu *option where you can specify what CPU you want,
>>>>>>>>>> if this option is not specified avr6 (avr6-avr-cpu) is chosen.
>>>>>>>>>>
>>>>>>>>>> *./avr-softmmu/qemu-system-avr -cpu help*
>>>>>>>>>> avr1-avr-cpu
>>>>>>>>>> avr2-avr-cpu
>>>>>>>>>> avr25-avr-cpu
>>>>>>>>>> avr3-avr-cpu
>>>>>>>>>> avr31-avr-cpu
>>>>>>>>>> avr35-avr-cpu
>>>>>>>>>> avr4-avr-cpu
>>>>>>>>>> avr5-avr-cpu
>>>>>>>>>> avr51-avr-cpu
>>>>>>>>>> avr6-avr-cpu
>>>>>>>>>> xmega2-avr-cpu
>>>>>>>>>> xmega4-avr-cpu
>>>>>>>>>> xmega5-avr-cpu
>>>>>>>>>> xmega6-avr-cpu
>>>>>>>>>> xmega7-avr-cpu
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>> What happens if you specify a core via -cpu, and supply elf file
>>>>>>>>> compiled for another core?
>>>>>>>>>
>>>>>>>>>
>>>>>>>> It looks there is some related info written in ELF header. This is
>>>>>>>> from a binutils header:
>>>>>>>>
>>>>>>>> (so it looks you could detect the core from elf file - do you do
>>>>>>>> that detection right now?)
>>>>>>>>
>>>>>>>> #define E_AVR_MACH_AVR1     1
>>>>>>>> #define E_AVR_MACH_AVR2     2
>>>>>>>> #define E_AVR_MACH_AVR25   25
>>>>>>>> #define E_AVR_MACH_AVR3     3
>>>>>>>> #define E_AVR_MACH_AVR31   31
>>>>>>>> #define E_AVR_MACH_AVR35   35
>>>>>>>> #define E_AVR_MACH_AVR4     4
>>>>>>>> #define E_AVR_MACH_AVR5     5
>>>>>>>> #define E_AVR_MACH_AVR51   51
>>>>>>>> #define E_AVR_MACH_AVR6     6
>>>>>>>> #define E_AVR_MACH_AVRTINY 100
>>>>>>>> #define E_AVR_MACH_XMEGA1  101
>>>>>>>> #define E_AVR_MACH_XMEGA2  102
>>>>>>>> #define E_AVR_MACH_XMEGA3  103
>>>>>>>> #define E_AVR_MACH_XMEGA4  104
>>>>>>>> #define E_AVR_MACH_XMEGA5  105
>>>>>>>> #define E_AVR_MACH_XMEGA6  106
>>>>>>>> #define E_AVR_MACH_XMEGA7  107
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> Best regards,
>>>>>>>>> Akeksandar
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>> Regards,
>>>>>>>>>> Michael Rolnik
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On Sat, Nov 30, 2019 at 1:28 PM Aleksandar Markovic <
>>>>>>>>>> aleksandar.m.mail@gmail.com> wrote:
>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> On Wednesday, November 27, 2019, Michael Rolnik <
>>>>>>>>>>> mrolnik@gmail.com> wrote:
>>>>>>>>>>>
>>>>>>>>>>>> This series of patches adds 8bit AVR cores to QEMU.
>>>>>>>>>>>> All instruction, except BREAK/DES/SPM/SPMX, are implemented.
>>>>>>>>>>>> Not fully tested yet.
>>>>>>>>>>>> However I was able to execute simple code with functions. e.g
>>>>>>>>>>>> fibonacci calculation.
>>>>>>>>>>>> This series of patches include a non real, sample board.
>>>>>>>>>>>> No fuses support yet. PC is set to 0 at reset.
>>>>>>>>>>>>
>>>>>>>>>>>> Following are examples of possible usages, assuming program.elf
>>>>>>>>>>>> is compiled for AVR cpu
>>>>>>>>>>>> 1.  Continious non interrupted execution
>>>>>>>>>>>>     run `qemu-system-avr -kernel program.elf`
>>>>>>>>>>>> 2.  Continious non interrupted execution with serial output
>>>>>>>>>>>> into telnet window
>>>>>>>>>>>>     run `qemu-system-avr -kernel program.elf -serial
>>>>>>>>>>>> tcp::5678,server,nowait -nographic `
>>>>>>>>>>>>     run `telent localhost 5678`
>>>>>>>>>>>> 3.  Continious non interrupted execution with serial output
>>>>>>>>>>>> into stdout
>>>>>>>>>>>>     run `qemu-system-avr -kernel program.elf -serial stdio`
>>>>>>>>>>>> 4.  Debugging wit GDB debugger
>>>>>>>>>>>>     run `qemu-system-avr -kernel program.elf -s -S`
>>>>>>>>>>>>     run `avr-gdb program.elf` and then within GDB shell `target
>>>>>>>>>>>> remote :1234`
>>>>>>>>>>>> 5.  Print out executed instructions
>>>>>>>>>>>>     run `qemu-system-avr -kernel program.elf -d in_asm`
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>> Hi, Michael.
>>>>>>>>>>>
>>>>>>>>>>> Can you explain to me the mechanisms of recognition of what
>>>>>>>>>>> core/microcontroller QEMU is supposed to emulate in the examples above?
>>>>>>>>>>>
>>>>>>>>>>> Yours, Aleksandar
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>> the patches include the following
>>>>>>>>>>>> 1. just a basic 8bit AVR CPU, without instruction decoding or
>>>>>>>>>>>> translation
>>>>>>>>>>>> 2. CPU features which allow define the following 8bit AVR cores
>>>>>>>>>>>>      avr1
>>>>>>>>>>>>      avr2 avr25
>>>>>>>>>>>>      avr3 avr31 avr35
>>>>>>>>>>>>      avr4
>>>>>>>>>>>>      avr5 avr51
>>>>>>>>>>>>      avr6
>>>>>>>>>>>>      xmega2 xmega4 xmega5 xmega6 xmega7
>>>>>>>>>>>> 3. a definition of sample machine with SRAM, FLASH and CPU
>>>>>>>>>>>> which allows to execute simple code
>>>>>>>>>>>> 4. encoding for all AVR instructions
>>>>>>>>>>>> 5. interrupt handling
>>>>>>>>>>>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
>>>>>>>>>>>> 7. a decoder which given an opcode decides what istruction it is
>>>>>>>>>>>> 8. translation of AVR instruction into TCG
>>>>>>>>>>>> 9. all features together
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v3
>>>>>>>>>>>> 1. rampD/X/Y/Z registers are encoded as 0x00ff0000 (instead of
>>>>>>>>>>>> 0x000000ff) for faster address manipulaton
>>>>>>>>>>>> 2. ffs changed to ctz32
>>>>>>>>>>>> 3. duplicate code removed at avr_cpu_do_interrupt
>>>>>>>>>>>> 4. using andc instead of not + and
>>>>>>>>>>>> 5. fixing V flag calculation in varios instructions
>>>>>>>>>>>> 6. freeing local variables in PUSH
>>>>>>>>>>>> 7. tcg_const_local_i32 -> tcg_const_i32
>>>>>>>>>>>> 8. using sextract32 instead of my implementation
>>>>>>>>>>>> 9. fixing BLD instruction
>>>>>>>>>>>> 10.xor(r) instead of 0xff - r at COM
>>>>>>>>>>>> 11.fixing MULS/MULSU not to modify inputs' content
>>>>>>>>>>>> 12.using SUB for NEG
>>>>>>>>>>>> 13.fixing tcg_gen_qemu_ld/st call in XCH
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v4
>>>>>>>>>>>> 1. target is now defined as big endian in order to optimize
>>>>>>>>>>>> push_ret/pop_ret
>>>>>>>>>>>> 2. all style warnings are fixed
>>>>>>>>>>>> 3. adding cpu_set/get_sreg functions
>>>>>>>>>>>> 4. simplifying gen_goto_tb as there is no real paging
>>>>>>>>>>>> 5. env->pc -> env->pc_w
>>>>>>>>>>>> 6. making flag dump more compact
>>>>>>>>>>>> 7. more spacing
>>>>>>>>>>>> 8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX
>>>>>>>>>>>> 9. removing avr_set_feature
>>>>>>>>>>>> 10. SPL/SPH set bug fix
>>>>>>>>>>>> 11. switching stb_phys to cpu_stb_data
>>>>>>>>>>>> 12. cleaning up avr_decode
>>>>>>>>>>>> 13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm)
>>>>>>>>>>>> 14. saving CPU features (savevm)
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v5
>>>>>>>>>>>> 1. BLD bug fix
>>>>>>>>>>>> 2. decoder generator is added
>>>>>>>>>>>>
>>>>>>>>>>>> chages since v6
>>>>>>>>>>>> 1. using cpu_get_sreg/cpu_set_sreg in
>>>>>>>>>>>> avr_cpu_gdb_read_register/avr_cpu_gdb_write_register
>>>>>>>>>>>> 2. configure the target as little endian because otherwise GDB
>>>>>>>>>>>> does not work
>>>>>>>>>>>> 3. fixing and testing gen_push_ret/gen_pop_ret
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v7
>>>>>>>>>>>> 1. folding back v6
>>>>>>>>>>>> 2. logging at helper_outb and helper_inb are done for non
>>>>>>>>>>>> supported yet registers only
>>>>>>>>>>>> 3. MAINTAINERS updated
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v8
>>>>>>>>>>>> 1. removing hw/avr from hw/Makefile.obj as it should not be
>>>>>>>>>>>> built for all
>>>>>>>>>>>> 2. making linux compilable
>>>>>>>>>>>> 3. testing on
>>>>>>>>>>>>     a. Mac, Apple LLVM version 7.0.0
>>>>>>>>>>>>     b. Ubuntu 12.04, gcc 4.9.2
>>>>>>>>>>>>     c. Fedora 23, gcc 5.3.1
>>>>>>>>>>>> 4. folding back some patches
>>>>>>>>>>>> 5. translation bug fixes for ORI, CPI, XOR instructions
>>>>>>>>>>>> 6. propper handling of cpu register writes though memory
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v9
>>>>>>>>>>>> 1. removing forward declarations of static functions
>>>>>>>>>>>> 2. disabling debug prints
>>>>>>>>>>>> 3. switching to case range instead of if else if ...
>>>>>>>>>>>> 4. LD/ST IN/OUT accessing CPU maintainder registers are not
>>>>>>>>>>>> routed to any device
>>>>>>>>>>>> 5. commenst about sample board and sample IO device added
>>>>>>>>>>>> 6. sample board description is more descriptive now
>>>>>>>>>>>> 7. memory_region_allocate_system_memory is used to create RAM
>>>>>>>>>>>> 8. now there are helper_fullrd & helper_fullwr when LD/ST try
>>>>>>>>>>>> to access registers
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v10
>>>>>>>>>>>> 1. movig back fullwr & fullrd into the commit where outb and
>>>>>>>>>>>> inb were introduced
>>>>>>>>>>>> 2. changing tlb_fill function signature
>>>>>>>>>>>> 3. adding empty line between functions
>>>>>>>>>>>> 4. adding newline on the last line of the file
>>>>>>>>>>>> 5. using tb->flags to generae full access ST/LD instructions
>>>>>>>>>>>> 6. fixing SBRC bug
>>>>>>>>>>>> 7. folding back 10th commit
>>>>>>>>>>>> 8. whenever a new file is introduced it's added to Makefile.objs
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v11
>>>>>>>>>>>> 1. updating to v2.7.0-rc
>>>>>>>>>>>> 2. removing assignment to env->fullacc from
>>>>>>>>>>>> gen_intermediate_code
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v12
>>>>>>>>>>>> 1. fixing spacing
>>>>>>>>>>>> 2. fixing get/put_segment functions
>>>>>>>>>>>> 3. removing target-avr/machine.h file
>>>>>>>>>>>> 4. VMSTATE_SINGLE_TEST -> VMSTATE_SINGLE
>>>>>>>>>>>> 5. comment spelling
>>>>>>>>>>>> 6. removing hw/avr/sample_io.c
>>>>>>>>>>>> 7. char const* -> const char*
>>>>>>>>>>>> 8. proper ram allocation
>>>>>>>>>>>> 9. fixing breakpoint functionality.
>>>>>>>>>>>> 10.env1 -> env
>>>>>>>>>>>> 11.fixing avr_cpu_gdb_write_register &
>>>>>>>>>>>> avr_cpu_gdb_read_register functions
>>>>>>>>>>>> 12.any cpu is removed
>>>>>>>>>>>> 12.feature bits are not saved into vm state
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v13
>>>>>>>>>>>> 1. rebasing to v2.7.0-rc1
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v14
>>>>>>>>>>>> 1. I made self review with git gui tool. (I did not know such a
>>>>>>>>>>>> thing exists)
>>>>>>>>>>>> 2. removing all double/tripple spaces
>>>>>>>>>>>> 3. removing comment reference to SampleIO
>>>>>>>>>>>> 4. folding back some changes, so there is not deleted lines in
>>>>>>>>>>>> my code
>>>>>>>>>>>> 5. moving avr configuration, within configure file, before chris
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v15
>>>>>>>>>>>> 1. removing IO registers cache from CPU
>>>>>>>>>>>> 2. implementing CBI/SBI as read(helper_inb), modify,
>>>>>>>>>>>> write(helper_outb)
>>>>>>>>>>>> 3. implementing CBIC/SBIC as read(helper_inb), check, branch
>>>>>>>>>>>> 4. adding missing tcg_temp_free_i32 for tcg_const_i32
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v16
>>>>>>>>>>>> 1. removing EXT IO registers knoledge from CPU. These registers
>>>>>>>>>>>> are accessible
>>>>>>>>>>>>    by LD/ST only. CPU has no interest in them
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v17 (by Richard Henderson)
>>>>>>>>>>>> This is Michael's v17, with some adjustments of my own:
>>>>>>>>>>>>
>>>>>>>>>>>> 1. Fix the whitespace errors reported by "git am",
>>>>>>>>>>>> 2. Replace the utf-8 characters with normal ascii,
>>>>>>>>>>>> 3. Ditch the separate compilation of translate.c.
>>>>>>>>>>>>
>>>>>>>>>>>> I retained the two separate files that could be regenerated
>>>>>>>>>>>> from the included cpugen program, but merged in
>>>>>>>>>>>> translate-insn.c.
>>>>>>>>>>>> Not that it matters, but the code generated is about 3k smaller.
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v18
>>>>>>>>>>>> 1.  moving target-avr into target/avr
>>>>>>>>>>>> 2.  do not call cpu_exec_initfn function from avr_cpu_initfn
>>>>>>>>>>>> 3.  call cpu_exec_realizefn avr_cpu_realizefn
>>>>>>>>>>>> 4.  do not fail sample machine creation if no rom is suplied
>>>>>>>>>>>> 5.  add tcg_gen_exit_tb(0) for BS_BRANCH in
>>>>>>>>>>>> gen_intermediate_code
>>>>>>>>>>>> 6.  fix a register getters/setters in machine.c
>>>>>>>>>>>> 7.  changing QEMU_ARCH_AVR from 1<<17 to 1<<18
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v19
>>>>>>>>>>>> 1.  use decodetree.py tool to decode instructions
>>>>>>>>>>>> 2.  adding USART
>>>>>>>>>>>> 3.  adding 16 bit timer peripherals
>>>>>>>>>>>> 4.  changing QEMU_ARCH_AVR from 1<<18 to 1<<20
>>>>>>>>>>>> 5.  renaming tlb_fill to avr_cpu_tlb_fill
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v20
>>>>>>>>>>>> 1.  use one CPU naming convention
>>>>>>>>>>>> 2.  merging insn16.decode & insn32.decode files
>>>>>>>>>>>> 3.  modifying skip next instruction mechanizm
>>>>>>>>>>>> 4.  translate BREAK as NOP for now
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v21
>>>>>>>>>>>> 1.  Reorganize bstate.
>>>>>>>>>>>>     This will make transition to <exec/translator.h> easier,
>>>>>>>>>>>> and fixes a couple of bugs wrt single stepping
>>>>>>>>>>>>     by richard.henderson@linaro.org
>>>>>>>>>>>> 2.  Drop cpc and fix page cross condition.
>>>>>>>>>>>>     by richard.henderson@linaro.org
>>>>>>>>>>>> 3.  Refactor checking supported/unsupported instructions
>>>>>>>>>>>> 4.  Add gdb-xml/avr-cpu.xml
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v22
>>>>>>>>>>>> 1.  Rebase
>>>>>>>>>>>> 2.  Split long comment
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v23
>>>>>>>>>>>> 1.  remove avr_cpu_list_compare function
>>>>>>>>>>>> 2.  modify avr_cpu_class_by_name function
>>>>>>>>>>>> 3.  modify avr_cpu_list_entry function
>>>>>>>>>>>> 4.  modify avr_cpu_list function
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v24
>>>>>>>>>>>> 1.  remove AVR_CPU_TYPE_NAME macro
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v25
>>>>>>>>>>>> 1.  fix patches. every file belong to one patch only
>>>>>>>>>>>> 2.  change copyright year from 2016 to 2019
>>>>>>>>>>>> 3.  create mask device to emulate prr0/prr1
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v26
>>>>>>>>>>>> 1.  add avocado acceptence test
>>>>>>>>>>>> 2.  add boot serial test
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v27
>>>>>>>>>>>> 1.  list atmel2560 devices as unimplemented
>>>>>>>>>>>> 2.  fix sram base/size
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v28
>>>>>>>>>>>> 1.  rebase
>>>>>>>>>>>> 2.  fix includes & build
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v29
>>>>>>>>>>>> 1.  fixing ownership
>>>>>>>>>>>> 2.  using 'since' instread of 'added in'
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v30
>>>>>>>>>>>> 1.  rebase
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v31
>>>>>>>>>>>> 1.  splitting 'Add instruction translation' commit
>>>>>>>>>>>> 2.  fixing typo in qapi/machine.json sicne -> since
>>>>>>>>>>>> 3.  removing unintended changes in configure file
>>>>>>>>>>>> 4.  adding Richard Henderson as a co developer to 'Add
>>>>>>>>>>>> instruction translation - CPU main translation funcions' commit
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v32
>>>>>>>>>>>> 1.  modify cpu_get_sreg to treat sreg C as other flags, except
>>>>>>>>>>>> sreg Z
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v33
>>>>>>>>>>>> 1.  ensure flag C is always calculated as one bit
>>>>>>>>>>>> 2.  calculate flag Z as one bit, without using inverse logic
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v34
>>>>>>>>>>>> 1.  rebase
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v35
>>>>>>>>>>>> 1.  rebase
>>>>>>>>>>>> 2.  use NANOSECONDS_PER_SECOND instead of 1000000000 in
>>>>>>>>>>>> avr_timer16.c
>>>>>>>>>>>> 3.  split "target/avr: Register AVR support with the rest of
>>>>>>>>>>>> QEMU" into three patches
>>>>>>>>>>>>     1.  "target/avr: Register AVR support with the rest of QEMU"
>>>>>>>>>>>>     2.  "target/avr: Update build system"
>>>>>>>>>>>>     3.  "target/avr: Update MAINTAINERS file"
>>>>>>>>>>>> 4.  split "target/avr: Add tests" patch into two patches
>>>>>>>>>>>>     1.  "target/avr: Add Avocado test"
>>>>>>>>>>>>     2.  "target/avr: Add boot serial test"
>>>>>>>>>>>> 5.  Add instruction disassembly function
>>>>>>>>>>>> 6.  change "since 4.2" to "since 5.0"
>>>>>>>>>>>>
>>>>>>>>>>>> changes since v36
>>>>>>>>>>>> 1.  rebase
>>>>>>>>>>>> 2.  tename
>>>>>>>>>>>>     1.  NO_CPU_REGISTERS    -> NUMBER_OF_CPU_REGISTERS
>>>>>>>>>>>>     2.  NO_IO_REGISTERS     -> NUMBER_OF_IO_REGISTERS
>>>>>>>>>>>>     3.  to_A                -> to_regs_16_31_by_one
>>>>>>>>>>>>     4.  to_B                -> to_regs_16_23_by_one
>>>>>>>>>>>>     5.  to_C                -> to_regs_24_30_by_two
>>>>>>>>>>>>     6.  to_D                -> to_regs_00_30_by_two
>>>>>>>>>>>> 3.  add missing licences
>>>>>>>>>>>> 4.  add usage example (see above)
>>>>>>>>>>>> 5.  ass Sarah Harris <S.E.Harris@kent.ac.uk> as a reviewer to
>>>>>>>>>>>> MAINTAINERS
>>>>>>>>>>>> 7.  use git commit sha1 instead of `master`` in avocado test
>>>>>>>>>>>>
>>>>>>>>>>>> Michael Rolnik (16):
>>>>>>>>>>>>   target/avr: Add outward facing interfaces and core CPU logic
>>>>>>>>>>>>   target/avr: Add instruction helpers
>>>>>>>>>>>>   target/avr: Add instruction decoding
>>>>>>>>>>>>   target/avr: Add instruction translation - Registers definition
>>>>>>>>>>>>   target/avr: Add instruction translation - Arithmetic and Logic
>>>>>>>>>>>>     Instructions
>>>>>>>>>>>>   target/avr: Add instruction translation - Branch Instructions
>>>>>>>>>>>>   target/avr: Add instruction translation - Bit and Bit-test
>>>>>>>>>>>>     Instructions
>>>>>>>>>>>>   target/avr: Add instruction translation - MCU Control
>>>>>>>>>>>> Instructions
>>>>>>>>>>>>   target/avr: Add instruction translation - CPU main translation
>>>>>>>>>>>>     function
>>>>>>>>>>>>   target/avr: Add instruction disassembly function
>>>>>>>>>>>>   target/avr: Add example board configuration
>>>>>>>>>>>>   target/avr: Register AVR support with the rest of QEMU
>>>>>>>>>>>>   target/avr: Update build system
>>>>>>>>>>>>   target/avr: Add boot serial test
>>>>>>>>>>>>   target/avr: Add Avocado test
>>>>>>>>>>>>   target/avr: Update MAINTAINERS file
>>>>>>>>>>>>
>>>>>>>>>>>> Sarah Harris (1):
>>>>>>>>>>>>   target/avr: Add limited support for USART and 16 bit timer
>>>>>>>>>>>> peripherals
>>>>>>>>>>>>
>>>>>>>>>>>>  configure                        |    7 +
>>>>>>>>>>>>  default-configs/avr-softmmu.mak  |    5 +
>>>>>>>>>>>>  qapi/machine.json                |    3 +-
>>>>>>>>>>>>  include/disas/dis-asm.h          |    6 +
>>>>>>>>>>>>  include/hw/char/avr_usart.h      |   97 +
>>>>>>>>>>>>  include/hw/misc/avr_mask.h       |   47 +
>>>>>>>>>>>>  include/hw/timer/avr_timer16.h   |   97 +
>>>>>>>>>>>>  include/sysemu/arch_init.h       |    1 +
>>>>>>>>>>>>  target/avr/cpu-param.h           |   37 +
>>>>>>>>>>>>  target/avr/cpu-qom.h             |   54 +
>>>>>>>>>>>>  target/avr/cpu.h                 |  254 +++
>>>>>>>>>>>>  target/avr/helper.h              |   29 +
>>>>>>>>>>>>  arch_init.c                      |    2 +
>>>>>>>>>>>>  hw/avr/sample.c                  |  282 +++
>>>>>>>>>>>>  hw/char/avr_usart.c              |  324 ++++
>>>>>>>>>>>>  hw/misc/avr_mask.c               |  112 ++
>>>>>>>>>>>>  hw/timer/avr_timer16.c           |  605 ++++++
>>>>>>>>>>>>  target/avr/cpu.c                 |  576 ++++++
>>>>>>>>>>>>  target/avr/disas.c               |  228 +++
>>>>>>>>>>>>  target/avr/gdbstub.c             |   85 +
>>>>>>>>>>>>  target/avr/helper.c              |  354 ++++
>>>>>>>>>>>>  target/avr/machine.c             |  121 ++
>>>>>>>>>>>>  target/avr/translate.c           | 3052
>>>>>>>>>>>> ++++++++++++++++++++++++++++++
>>>>>>>>>>>>  tests/boot-serial-test.c         |   10 +
>>>>>>>>>>>>  tests/machine-none-test.c        |    1 +
>>>>>>>>>>>>  MAINTAINERS                      |   11 +
>>>>>>>>>>>>  gdb-xml/avr-cpu.xml              |   49 +
>>>>>>>>>>>>  hw/Kconfig                       |    1 +
>>>>>>>>>>>>  hw/avr/Kconfig                   |    6 +
>>>>>>>>>>>>  hw/avr/Makefile.objs             |    1 +
>>>>>>>>>>>>  hw/char/Kconfig                  |    3 +
>>>>>>>>>>>>  hw/char/Makefile.objs            |    1 +
>>>>>>>>>>>>  hw/misc/Kconfig                  |    3 +
>>>>>>>>>>>>  hw/misc/Makefile.objs            |    2 +
>>>>>>>>>>>>  hw/timer/Kconfig                 |    3 +
>>>>>>>>>>>>  hw/timer/Makefile.objs           |    2 +
>>>>>>>>>>>>  target/avr/Makefile.objs         |   34 +
>>>>>>>>>>>>  target/avr/insn.decode           |  194 ++
>>>>>>>>>>>>  tests/Makefile.include           |    2 +
>>>>>>>>>>>>  tests/acceptance/machine_avr6.py |   56 +
>>>>>>>>>>>>  40 files changed, 6756 insertions(+), 1 deletion(-)
>>>>>>>>>>>>  create mode 100644 default-configs/avr-softmmu.mak
>>>>>>>>>>>>  create mode 100644 include/hw/char/avr_usart.h
>>>>>>>>>>>>  create mode 100644 include/hw/misc/avr_mask.h
>>>>>>>>>>>>  create mode 100644 include/hw/timer/avr_timer16.h
>>>>>>>>>>>>  create mode 100644 target/avr/cpu-param.h
>>>>>>>>>>>>  create mode 100644 target/avr/cpu-qom.h
>>>>>>>>>>>>  create mode 100644 target/avr/cpu.h
>>>>>>>>>>>>  create mode 100644 target/avr/helper.h
>>>>>>>>>>>>  create mode 100644 hw/avr/sample.c
>>>>>>>>>>>>  create mode 100644 hw/char/avr_usart.c
>>>>>>>>>>>>  create mode 100644 hw/misc/avr_mask.c
>>>>>>>>>>>>  create mode 100644 hw/timer/avr_timer16.c
>>>>>>>>>>>>  create mode 100644 target/avr/cpu.c
>>>>>>>>>>>>  create mode 100644 target/avr/disas.c
>>>>>>>>>>>>  create mode 100644 target/avr/gdbstub.c
>>>>>>>>>>>>  create mode 100644 target/avr/helper.c
>>>>>>>>>>>>  create mode 100644 target/avr/machine.c
>>>>>>>>>>>>  create mode 100644 target/avr/translate.c
>>>>>>>>>>>>  create mode 100644 gdb-xml/avr-cpu.xml
>>>>>>>>>>>>  create mode 100644 hw/avr/Kconfig
>>>>>>>>>>>>  create mode 100644 hw/avr/Makefile.objs
>>>>>>>>>>>>  create mode 100644 target/avr/Makefile.objs
>>>>>>>>>>>>  create mode 100644 target/avr/insn.decode
>>>>>>>>>>>>  create mode 100644 tests/acceptance/machine_avr6.py
>>>>>>>>>>>>
>>>>>>>>>>>> --
>>>>>>>>>>>> 2.17.2 (Apple Git-113)
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> --
>>>>>>>>>> Best Regards,
>>>>>>>>>> Michael Rolnik
>>>>>>>>>>
>>>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> Best Regards,
>>>>>>> Michael Rolnik
>>>>>>>
>>>>>>
>>>>>
>>>>> --
>>>>> Best Regards,
>>>>> Michael Rolnik
>>>>>
>>>>

-- 
Best Regards,
Michael Rolnik

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