* [PATCH v2 0/2] target/riscv: Add support for Zaamo & Zalrsc
@ 2024-01-19 11:21 Rob Bradford
2024-01-19 11:21 ` [PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions Rob Bradford
2024-01-19 11:21 ` [PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions Rob Bradford
0 siblings, 2 replies; 5+ messages in thread
From: Rob Bradford @ 2024-01-19 11:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, atishp, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, Rob Bradford
Introduce support for the proposed new (fast-track) Zaamo and Zalrsc
extensions [1] which represent the AMO and LR/SC subsets of the A
extension.
The motivation for the subsets being available separately is that
certain classes of CPUs may choose to only implement a subset for
architectural convenience.
Since this extension is not frozen these are advertised by "x-zaamo" and
"x-zalrsc" options. Beyond adding the extension infrastructure the only
changes required are to allow the atomic instructions under either A or
the appropriate subset extension. To ensure compatibility enabling the
A instruction does not enable these two extensions - future hardware may
choose to advertise support for A and both these extensions for maximum
software support.
This patch is based off riscv-to-apply.next due to conflicts with
existing patches.
Cheers,
Rob
[1] - https://github.com/riscv/riscv-zaamo-zalrsc
Changes since V1:
- Fix commit message that did not account for earlier fix (Daniel)
Rob Bradford (2):
target/riscv: Add Zaamo and Zalrsc extensions
target/riscv: Check 'A' and split extensions for atomic instructions
target/riscv/cpu.c | 5 +++
target/riscv/cpu_cfg.h | 2 +
target/riscv/insn_trans/trans_rva.c.inc | 56 +++++++++++++++----------
3 files changed, 41 insertions(+), 22 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions
2024-01-19 11:21 [PATCH v2 0/2] target/riscv: Add support for Zaamo & Zalrsc Rob Bradford
@ 2024-01-19 11:21 ` Rob Bradford
2024-01-22 5:46 ` Alistair Francis
2024-01-19 11:21 ` [PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions Rob Bradford
1 sibling, 1 reply; 5+ messages in thread
From: Rob Bradford @ 2024-01-19 11:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, atishp, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, Rob Bradford
These extensions represent the atomic operations from A (Zaamo) and the
Load-Reserved/Store-Conditional operations from A (Zalrsc)
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 5 +++++
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8d3ec74a1c..604baf53c8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -103,7 +103,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
+ ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
+ ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
@@ -1491,6 +1493,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
+ MULTI_EXT_CFG_BOOL("x-zaamo", ext_zaamo, false),
+ MULTI_EXT_CFG_BOOL("x-zalrsc", ext_zalrsc, false),
+
MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fea14c275f..cc4c30244c 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -78,7 +78,9 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_zdinx;
+ bool ext_zaamo;
bool ext_zacas;
+ bool ext_zalrsc;
bool ext_zawrs;
bool ext_zfa;
bool ext_zfbfmin;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions
2024-01-19 11:21 [PATCH v2 0/2] target/riscv: Add support for Zaamo & Zalrsc Rob Bradford
2024-01-19 11:21 ` [PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions Rob Bradford
@ 2024-01-19 11:21 ` Rob Bradford
2024-01-19 12:24 ` Daniel Henrique Barboza
1 sibling, 1 reply; 5+ messages in thread
From: Rob Bradford @ 2024-01-19 11:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, atishp, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, Rob Bradford
Following the pattern for 'M' and Zmmul check if either the 'A'
extension is enabled or the appropriate split extension for the
instruction.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 56 +++++++++++++++----------
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index f0368de3e4..267930e5bc 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -18,6 +18,18 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#define REQUIRE_A_OR_ZAAMO(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zaamo && !has_ext(ctx, RVA)) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_A_OR_ZALRSC(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zalrsc && !has_ext(ctx, RVA)) { \
+ return false; \
+ } \
+} while (0)
+
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1;
@@ -96,143 +108,143 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZALRSC(ctx);
return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
}
static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZALRSC(ctx);
return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
}
static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
{
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZALRSC(ctx);
return gen_lr(ctx, a, MO_ALIGN | MO_TEUQ);
}
static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZALRSC(ctx);
return gen_sc(ctx, a, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEUQ));
}
static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVA);
+ REQUIRE_A_OR_ZAAMO(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEUQ));
}
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions
2024-01-19 11:21 ` [PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions Rob Bradford
@ 2024-01-19 12:24 ` Daniel Henrique Barboza
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-19 12:24 UTC (permalink / raw)
To: Rob Bradford, qemu-devel
Cc: qemu-riscv, atishp, palmer, alistair.francis, bin.meng,
liwei1518, zhiwei_liu
On 1/19/24 08:21, Rob Bradford wrote:
> Following the pattern for 'M' and Zmmul check if either the 'A'
> extension is enabled or the appropriate split extension for the
> instruction.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/insn_trans/trans_rva.c.inc | 56 +++++++++++++++----------
> 1 file changed, 34 insertions(+), 22 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
> index f0368de3e4..267930e5bc 100644
> --- a/target/riscv/insn_trans/trans_rva.c.inc
> +++ b/target/riscv/insn_trans/trans_rva.c.inc
> @@ -18,6 +18,18 @@
> * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +#define REQUIRE_A_OR_ZAAMO(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zaamo && !has_ext(ctx, RVA)) { \
> + return false; \
> + } \
> +} while (0)
> +
> +#define REQUIRE_A_OR_ZALRSC(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zalrsc && !has_ext(ctx, RVA)) { \
> + return false; \
> + } \
> +} while (0)
> +
> static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
> {
> TCGv src1;
> @@ -96,143 +108,143 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
>
> static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZALRSC(ctx);
> return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZALRSC(ctx);
> return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
> {
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
> }
>
> static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZALRSC(ctx);
> return gen_lr(ctx, a, MO_ALIGN | MO_TEUQ);
> }
>
> static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZALRSC(ctx);
> return gen_sc(ctx, a, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_EXT(ctx, RVA);
> + REQUIRE_A_OR_ZAAMO(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEUQ));
> }
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions
2024-01-19 11:21 ` [PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions Rob Bradford
@ 2024-01-22 5:46 ` Alistair Francis
0 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2024-01-22 5:46 UTC (permalink / raw)
To: Rob Bradford
Cc: qemu-devel, qemu-riscv, atishp, palmer, alistair.francis,
bin.meng, liwei1518, dbarboza, zhiwei_liu
On Fri, Jan 19, 2024 at 9:22 PM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> These extensions represent the atomic operations from A (Zaamo) and the
> Load-Reserved/Store-Conditional operations from A (Zalrsc)
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 5 +++++
> target/riscv/cpu_cfg.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8d3ec74a1c..604baf53c8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -103,7 +103,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
> ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
> ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
> + ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
> ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
> + ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
> ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
> ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
> ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
> @@ -1491,6 +1493,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
> MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
>
> + MULTI_EXT_CFG_BOOL("x-zaamo", ext_zaamo, false),
> + MULTI_EXT_CFG_BOOL("x-zalrsc", ext_zalrsc, false),
We should implement the extension before we expose it to userspace.
That helps maintain bisectability of the code
Alistair
> +
> MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
> MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index fea14c275f..cc4c30244c 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -78,7 +78,9 @@ struct RISCVCPUConfig {
> bool ext_svnapot;
> bool ext_svpbmt;
> bool ext_zdinx;
> + bool ext_zaamo;
> bool ext_zacas;
> + bool ext_zalrsc;
> bool ext_zawrs;
> bool ext_zfa;
> bool ext_zfbfmin;
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-01-22 5:47 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-19 11:21 [PATCH v2 0/2] target/riscv: Add support for Zaamo & Zalrsc Rob Bradford
2024-01-19 11:21 ` [PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions Rob Bradford
2024-01-22 5:46 ` Alistair Francis
2024-01-19 11:21 ` [PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions Rob Bradford
2024-01-19 12:24 ` Daniel Henrique Barboza
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