From: Alistair Francis <alistair23@gmail.com>
To: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Date: Mon, 30 Nov 2020 18:09:40 -0800 [thread overview]
Message-ID: <CAKmqyKMD3c5dD8-V9kfYS5aizE1fm3N+ot37kPgyb10km7gmsA@mail.gmail.com> (raw)
In-Reply-To: <20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk>
On Mon, Nov 30, 2020 at 9:07 AM Alex Richardson
<Alexander.Richardson@cl.cam.ac.uk> wrote:
>
> The TW and TSR fields should be bits 21 and 22 and not 30/29.
> This was found while comparing QEMU behaviour against the sail formal
> model (https://github.com/rems-project/sail-riscv/).
>
> Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 24b24c69c5..92147332c6 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -379,8 +379,8 @@
> #define MSTATUS_MXR 0x00080000
> #define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
> #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
> -#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
> -#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
> +#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
> +#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
> #define MSTATUS_GVA 0x4000000000ULL
> #define MSTATUS_MPV 0x8000000000ULL
>
> --
> 2.29.2
>
>
prev parent reply other threads:[~2020-12-01 2:22 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-30 17:01 [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Alex Richardson
2020-12-01 2:09 ` Alistair Francis [this message]
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