* [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
@ 2020-11-30 17:01 Alex Richardson
2020-12-01 2:09 ` Alistair Francis
0 siblings, 1 reply; 2+ messages in thread
From: Alex Richardson @ 2020-11-30 17:01 UTC (permalink / raw)
Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
open list:All patches CC here, Alistair Francis, Alex Richardson,
Palmer Dabbelt
The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
---
target/riscv/cpu_bits.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 24b24c69c5..92147332c6 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -379,8 +379,8 @@
#define MSTATUS_MXR 0x00080000
#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
-#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
-#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
+#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
+#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
--
2.29.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
2020-11-30 17:01 [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Alex Richardson
@ 2020-12-01 2:09 ` Alistair Francis
0 siblings, 0 replies; 2+ messages in thread
From: Alistair Francis @ 2020-12-01 2:09 UTC (permalink / raw)
To: Alex Richardson
Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
open list:All patches CC here, Alistair Francis, Palmer Dabbelt
On Mon, Nov 30, 2020 at 9:07 AM Alex Richardson
<Alexander.Richardson@cl.cam.ac.uk> wrote:
>
> The TW and TSR fields should be bits 21 and 22 and not 30/29.
> This was found while comparing QEMU behaviour against the sail formal
> model (https://github.com/rems-project/sail-riscv/).
>
> Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 24b24c69c5..92147332c6 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -379,8 +379,8 @@
> #define MSTATUS_MXR 0x00080000
> #define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
> #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
> -#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
> -#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
> +#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
> +#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
> #define MSTATUS_GVA 0x4000000000ULL
> #define MSTATUS_MPV 0x8000000000ULL
>
> --
> 2.29.2
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2020-12-01 2:22 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-30 17:01 [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Alex Richardson
2020-12-01 2:09 ` Alistair Francis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).