From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Igor Mammedov" <imammedo@redhat.com>
Subject: Re: [PATCH v2 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
Date: Thu, 21 Oct 2021 09:11:26 +1000 [thread overview]
Message-ID: <CAKmqyKMDJ935US0Sy6=UC5mPuDtebmW9znKtEAUtdA_fK-M9ug@mail.gmail.com> (raw)
In-Reply-To: <20211020014112.7336-4-bmeng.cn@gmail.com>
On Wed, Oct 20, 2021 at 11:46 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> (no changes since v1)
>
> hw/riscv/shakti_c.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index d7d1f91fa5..90e2cf609f 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -45,7 +45,6 @@ static void shakti_c_machine_state_init(MachineState *mstate)
> {
> ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
>
> /* Allow only Shakti C CPU for this platform */
> if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
> @@ -59,11 +58,9 @@ static void shakti_c_machine_state_init(MachineState *mstate)
> qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
>
> /* register RAM */
> - memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
> - mstate->ram_size, &error_fatal);
> memory_region_add_subregion(system_memory,
> shakti_c_memmap[SHAKTI_C_RAM].base,
> - main_mem);
> + mstate->ram);
>
> /* ROM reset vector */
> riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
> @@ -88,6 +85,7 @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
> mc->desc = "RISC-V Board compatible with Shakti SDK";
> mc->init = shakti_c_machine_state_init;
> mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
> + mc->default_ram_id = "riscv.shakti.c.ram";
> }
>
> static const TypeInfo shakti_c_machine_type_info = {
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-10-20 23:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
2021-10-20 1:41 ` [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-20 23:06 ` Alistair Francis
2021-10-21 8:48 ` Igor Mammedov
2021-10-20 1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
2021-10-20 13:01 ` Philippe Mathieu-Daudé
2021-10-20 23:10 ` Alistair Francis
2021-10-21 8:44 ` Igor Mammedov
2021-10-20 1:41 ` [PATCH v2 3/6] hw/riscv: shakti_c: " Bin Meng
2021-10-20 23:11 ` Alistair Francis [this message]
2021-10-20 1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-20 13:02 ` Philippe Mathieu-Daudé
2021-10-20 23:12 ` Alistair Francis
2021-10-21 8:43 ` Igor Mammedov
2021-10-20 1:41 ` [PATCH v2 5/6] hw/riscv: sifive_u: " Bin Meng
2021-10-20 23:12 ` Alistair Francis
2021-10-20 1:41 ` [PATCH v2 6/6] hw/riscv: spike: " Bin Meng
2021-10-20 23:13 ` Alistair Francis
2021-10-21 21:58 ` [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Alistair Francis
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