From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Igor Mammedov <imammedo@redhat.com>
Subject: Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
Date: Wed, 20 Oct 2021 15:01:59 +0200 [thread overview]
Message-ID: <f2922591-0335-b319-a3df-4b0a95b4e5fb@redhat.com> (raw)
In-Reply-To: <20211020014112.7336-3-bmeng.cn@gmail.com>
On 10/20/21 03:41, Bin Meng wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/opentitan.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
next prev parent reply other threads:[~2021-10-20 13:07 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
2021-10-20 1:41 ` [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-20 23:06 ` Alistair Francis
2021-10-21 8:48 ` Igor Mammedov
2021-10-20 1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
2021-10-20 13:01 ` Philippe Mathieu-Daudé [this message]
2021-10-20 23:10 ` Alistair Francis
2021-10-21 8:44 ` Igor Mammedov
2021-10-20 1:41 ` [PATCH v2 3/6] hw/riscv: shakti_c: " Bin Meng
2021-10-20 23:11 ` Alistair Francis
2021-10-20 1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-20 13:02 ` Philippe Mathieu-Daudé
2021-10-20 23:12 ` Alistair Francis
2021-10-21 8:43 ` Igor Mammedov
2021-10-20 1:41 ` [PATCH v2 5/6] hw/riscv: sifive_u: " Bin Meng
2021-10-20 23:12 ` Alistair Francis
2021-10-20 1:41 ` [PATCH v2 6/6] hw/riscv: spike: " Bin Meng
2021-10-20 23:13 ` Alistair Francis
2021-10-21 21:58 ` [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Alistair Francis
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