* [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8
@ 2024-01-09 10:29 Alexey Baturo
2024-01-09 10:29 ` [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
` (6 more replies)
0 siblings, 7 replies; 19+ messages in thread
From: Alexey Baturo @ 2024-01-09 10:29 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Hi,
Patch series updated after the suggested comments:
- removed J-letter extension as it's unused
- renamed and fixed function to detect if address should be sign-extended
- zeroed unused context variables and moved computation logic to another patch
- bumped pointer masking version_id and minimum_version_id by 1
Thanks
[v3]:
There patches are updated after Richard's comments:
- moved new tb flags to the end
- used tcg_gen_(s)extract to get the final address
- properly handle CONFIG_USER_ONLY
Thanks
[v2]:
As per Richard's suggestion I made pmm field part of tb_flags.
It allowed to get rid of global variable to store pmlen.
Also it allowed to simplify all the machinery around it.
Thanks
[v1]:
Hi all,
It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore.
Compared to the original implementation with explicit base and mask CSRs, we now only have
several fixed options for number of masked bits which are set using existing CSRs.
The changes have been tested with handwritten assembly tests and LLVM HWASAN
test suite.
Thanks
Alexey Baturo (6):
target/riscv: Remove obsolete pointer masking extension code.
target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part
of Zjpm v0.8
target/riscv: Add helper functions to calculate current number of
masked bits for pointer masking
target/riscv: Add pointer masking tb flags
target/riscv: Update address modify functions to take into account
pointer masking
target/riscv: Enable updates for pointer masking variables and thus
enable pointer masking extension
target/riscv/cpu.c | 21 +--
target/riscv/cpu.h | 46 +++--
target/riscv/cpu_bits.h | 90 +---------
target/riscv/cpu_cfg.h | 3 +
target/riscv/cpu_helper.c | 96 +++++-----
target/riscv/csr.c | 337 ++---------------------------------
target/riscv/machine.c | 16 +-
target/riscv/pmp.c | 13 +-
target/riscv/pmp.h | 11 +-
target/riscv/tcg/tcg-cpu.c | 5 +-
target/riscv/translate.c | 46 ++---
target/riscv/vector_helper.c | 14 +-
12 files changed, 153 insertions(+), 545 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code.
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
@ 2024-01-09 10:29 ` Alexey Baturo
2024-01-22 6:53 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
` (5 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Alexey Baturo @ 2024-01-09 10:29 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.c | 13 +-
target/riscv/cpu.h | 33 +---
target/riscv/cpu_bits.h | 87 ----------
target/riscv/cpu_helper.c | 52 ------
target/riscv/csr.c | 326 -----------------------------------
target/riscv/machine.c | 14 +-
target/riscv/tcg/tcg-cpu.c | 5 +-
target/riscv/translate.c | 27 +--
target/riscv/vector_helper.c | 2 +-
9 files changed, 14 insertions(+), 545 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 83c7c0cf07..d8de1f1890 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -40,7 +40,7 @@
/* RISC-V CPU definitions */
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
- RVC, RVS, RVU, RVH, RVJ, RVG, 0};
+ RVC, RVS, RVU, RVH, RVG, 0};
/*
* From vector_helper.c
@@ -710,13 +710,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CSR_MSCRATCH,
CSR_SSCRATCH,
CSR_SATP,
- CSR_MMTE,
- CSR_UPMBASE,
- CSR_UPMMASK,
- CSR_SPMBASE,
- CSR_SPMMASK,
- CSR_MPMBASE,
- CSR_MPMMASK,
};
for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
@@ -891,8 +884,6 @@ static void riscv_cpu_reset_hold(Object *obj)
}
i++;
}
- /* mmte is supposed to have pm.current hardwired to 1 */
- env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
/*
* Clear mseccfg and unlock all the PMP entries upon reset.
@@ -906,7 +897,6 @@ static void riscv_cpu_reset_hold(Object *obj)
pmp_unlock_entries(env);
#endif
env->xl = riscv_cpu_mxl(env);
- riscv_cpu_update_mask(env);
cs->exception_index = RISCV_EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
@@ -1251,7 +1241,6 @@ static const MISAExtInfo misa_ext_info_arr[] = {
MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
MISA_EXT_INFO(RVU, "u", "User-level instructions"),
MISA_EXT_INFO(RVH, "h", "Hypervisor"),
- MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
MISA_EXT_INFO(RVV, "v", "Vector operations"),
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d74b361be6..a43c8fba57 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,7 +67,6 @@ typedef struct CPUArchState CPURISCVState;
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
-#define RVJ RV('J')
#define RVG RV('G')
extern const uint32_t misa_bits[];
@@ -374,18 +373,7 @@ struct CPUArchState {
/* True if in debugger mode. */
bool debugger;
- /*
- * CSRs for PointerMasking extension
- */
- target_ulong mmte;
- target_ulong mpmmask;
- target_ulong mpmbase;
- target_ulong spmmask;
- target_ulong spmbase;
- target_ulong upmmask;
- target_ulong upmbase;
-
- /* CSRs for execution environment configuration */
+ /* CSRs for execution enviornment configuration */
uint64_t menvcfg;
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
@@ -393,8 +381,6 @@ struct CPUArchState {
target_ulong senvcfg;
uint64_t henvcfg;
#endif
- target_ulong cur_pmmask;
- target_ulong cur_pmbase;
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
@@ -543,17 +529,14 @@ FIELD(TB_FLAGS, VILL, 14, 1)
FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 16, 2)
-/* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
-FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
-FIELD(TB_FLAGS, VTA, 20, 1)
-FIELD(TB_FLAGS, VMA, 21, 1)
+FIELD(TB_FLAGS, VTA, 18, 1)
+FIELD(TB_FLAGS, VMA, 19, 1)
/* Native debug itrigger */
-FIELD(TB_FLAGS, ITRIGGER, 22, 1)
+FIELD(TB_FLAGS, ITRIGGER, 20, 1)
/* Virtual mode enabled */
-FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
-FIELD(TB_FLAGS, PRIV, 24, 2)
-FIELD(TB_FLAGS, AXL, 26, 2)
+FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
+FIELD(TB_FLAGS, PRIV, 22, 2)
+FIELD(TB_FLAGS, AXL, 24, 2)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
@@ -680,8 +663,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags);
-void riscv_cpu_update_mask(CPURISCVState *env);
-
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ebd7917d49..1c92458a01 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -491,37 +491,6 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
-/*
- * User PointerMasking registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_UMTE 0x4c0
-#define CSR_UPMMASK 0x4c1
-#define CSR_UPMBASE 0x4c2
-
-/*
- * Machine PointerMasking registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_MMTE 0x3c0
-#define CSR_MPMMASK 0x3c1
-#define CSR_MPMBASE 0x3c2
-
-/*
- * Supervisor PointerMaster registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_SMTE 0x1c0
-#define CSR_SPMMASK 0x1c1
-#define CSR_SPMBASE 0x1c2
-
-/*
- * Hypervisor PointerMaster registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_VSMTE 0x2c0
-#define CSR_VSPMMASK 0x2c1
-#define CSR_VSPMBASE 0x2c2
#define CSR_SCOUNTOVF 0xda0
/* Crypto Extension */
@@ -741,11 +710,6 @@ typedef enum RISCVException {
#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
-/* General PointerMasking CSR bits */
-#define PM_ENABLE 0x00000001ULL
-#define PM_CURRENT 0x00000002ULL
-#define PM_INSN 0x00000004ULL
-
/* Execution environment configuration bits */
#define MENVCFG_FIOM BIT(0)
#define MENVCFG_CBIE (3UL << 4)
@@ -778,57 +742,6 @@ typedef enum RISCVException {
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE
-/* Offsets for every pair of control bits per each priv level */
-#define XS_OFFSET 0ULL
-#define U_OFFSET 2ULL
-#define S_OFFSET 5ULL
-#define M_OFFSET 8ULL
-
-#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
-#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
-#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
-#define U_PM_INSN (PM_INSN << U_OFFSET)
-#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
-#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
-#define S_PM_INSN (PM_INSN << S_OFFSET)
-#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
-#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
-#define M_PM_INSN (PM_INSN << M_OFFSET)
-
-/* mmte CSR bits */
-#define MMTE_PM_XS_BITS PM_XS_BITS
-#define MMTE_U_PM_ENABLE U_PM_ENABLE
-#define MMTE_U_PM_CURRENT U_PM_CURRENT
-#define MMTE_U_PM_INSN U_PM_INSN
-#define MMTE_S_PM_ENABLE S_PM_ENABLE
-#define MMTE_S_PM_CURRENT S_PM_CURRENT
-#define MMTE_S_PM_INSN S_PM_INSN
-#define MMTE_M_PM_ENABLE M_PM_ENABLE
-#define MMTE_M_PM_CURRENT M_PM_CURRENT
-#define MMTE_M_PM_INSN M_PM_INSN
-#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
- MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
- MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
- MMTE_PM_XS_BITS)
-
-/* (v)smte CSR bits */
-#define SMTE_PM_XS_BITS PM_XS_BITS
-#define SMTE_U_PM_ENABLE U_PM_ENABLE
-#define SMTE_U_PM_CURRENT U_PM_CURRENT
-#define SMTE_U_PM_INSN U_PM_INSN
-#define SMTE_S_PM_ENABLE S_PM_ENABLE
-#define SMTE_S_PM_CURRENT S_PM_CURRENT
-#define SMTE_S_PM_INSN S_PM_INSN
-#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
- SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
- SMTE_PM_XS_BITS)
-
-/* umte CSR bits */
-#define UMTE_U_PM_ENABLE U_PM_ENABLE
-#define UMTE_U_PM_CURRENT U_PM_CURRENT
-#define UMTE_U_PM_INSN U_PM_INSN
-#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
-
/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
#define ISELECT_IPRIO0 0x30
#define ISELECT_IPRIO15 0x3f
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e7e23b34f4..a3d477d226 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -135,61 +135,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
- if (env->cur_pmmask != 0) {
- flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
- }
- if (env->cur_pmbase != 0) {
- flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
- }
*pflags = flags;
}
-void riscv_cpu_update_mask(CPURISCVState *env)
-{
- target_ulong mask = 0, base = 0;
- RISCVMXL xl = env->xl;
- /*
- * TODO: Current RVJ spec does not specify
- * how the extension interacts with XLEN.
- */
-#ifndef CONFIG_USER_ONLY
- int mode = cpu_address_mode(env);
- xl = cpu_get_xl(env, mode);
- if (riscv_has_ext(env, RVJ)) {
- switch (mode) {
- case PRV_M:
- if (env->mmte & M_PM_ENABLE) {
- mask = env->mpmmask;
- base = env->mpmbase;
- }
- break;
- case PRV_S:
- if (env->mmte & S_PM_ENABLE) {
- mask = env->spmmask;
- base = env->spmbase;
- }
- break;
- case PRV_U:
- if (env->mmte & U_PM_ENABLE) {
- mask = env->upmmask;
- base = env->upmbase;
- }
- break;
- default:
- g_assert_not_reached();
- }
- }
-#endif
- if (xl == MXL_RV32) {
- env->cur_pmmask = mask & UINT32_MAX;
- env->cur_pmbase = base & UINT32_MAX;
- } else {
- env->cur_pmmask = mask;
- env->cur_pmbase = base;
- }
-}
-
#ifndef CONFIG_USER_ONLY
/*
@@ -721,7 +670,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv = newpriv;
env->xl = cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
/*
* Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fde7ce1a53..ea4e1ac6ef 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -483,16 +483,6 @@ static RISCVException hgatp(CPURISCVState *env, int csrno)
return hmode(env, csrno);
}
-/* Checks if PointerMasking registers could be accessed */
-static RISCVException pointer_masking(CPURISCVState *env, int csrno)
-{
- /* Check if j-ext is present */
- if (riscv_has_ext(env, RVJ)) {
- return RISCV_EXCP_NONE;
- }
- return RISCV_EXCP_ILLEGAL_INST;
-}
-
static int aia_hmode(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_cfg(env)->ext_ssaia) {
@@ -1355,7 +1345,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
env->xl = cpu_recompute_xl(env);
}
- riscv_cpu_update_mask(env);
return RISCV_EXCP_NONE;
}
@@ -3900,302 +3889,6 @@ static RISCVException read_tinfo(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-/*
- * Functions to access Pointer Masking feature registers
- * We have to check if current priv lvl could modify
- * csr in given mode
- */
-static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
-{
- int csr_priv = get_field(csrno, 0x300);
- int pm_current;
-
- if (env->debugger) {
- return false;
- }
- /*
- * If priv lvls differ that means we're accessing csr from higher priv lvl,
- * so allow the access
- */
- if (env->priv != csr_priv) {
- return false;
- }
- switch (env->priv) {
- case PRV_M:
- pm_current = get_field(env->mmte, M_PM_CURRENT);
- break;
- case PRV_S:
- pm_current = get_field(env->mmte, S_PM_CURRENT);
- break;
- case PRV_U:
- pm_current = get_field(env->mmte, U_PM_CURRENT);
- break;
- default:
- g_assert_not_reached();
- }
- /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
- return !pm_current;
-}
-
-static RISCVException read_mmte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mmte & MMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mmte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
- target_ulong wpri_val = val & MMTE_MASK;
-
- if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
- val, "vs expected 0x", wpri_val);
- }
- /* for machine mode pm.current is hardwired to 1 */
- wpri_val |= MMTE_M_PM_CURRENT;
-
- /* hardwiring pm.instruction bit to 0, since it's not supported yet */
- wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
- env->mmte = wpri_val | EXT_STATUS_DIRTY;
- riscv_cpu_update_mask(env);
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_smte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mmte & SMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_smte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- target_ulong wpri_val = val & SMTE_MASK;
-
- if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
- val, "vs expected 0x", wpri_val);
- }
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
-
- wpri_val |= (env->mmte & ~SMTE_MASK);
- write_mmte(env, csrno, wpri_val);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_umte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mmte & UMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_umte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- target_ulong wpri_val = val & UMTE_MASK;
-
- if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
- val, "vs expected 0x", wpri_val);
- }
-
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
-
- wpri_val |= (env->mmte & ~UMTE_MASK);
- write_mmte(env, csrno, wpri_val);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mpmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- env->mpmmask = val;
- if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
- env->cur_pmmask = val;
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_spmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->spmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_spmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->spmmask = val;
- if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
- env->cur_pmmask = val;
- if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
- env->cur_pmmask &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_upmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->upmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_upmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->upmmask = val;
- if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
- env->cur_pmmask = val;
- if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
- env->cur_pmmask &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mpmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- env->mpmbase = val;
- if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
- env->cur_pmbase = val;
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_spmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->spmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_spmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->spmbase = val;
- if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
- env->cur_pmbase = val;
- if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
- env->cur_pmbase &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_upmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->upmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_upmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->upmbase = val;
- if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
- env->cur_pmbase = val;
- if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
- env->cur_pmbase &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
#endif
/* Crypto Extension */
@@ -4800,25 +4493,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
[CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
- /* User Pointer Masking */
- [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
- [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
- write_upmmask },
- [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
- write_upmbase },
- /* Machine Pointer Masking */
- [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
- [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
- write_mpmmask },
- [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
- write_mpmbase },
- /* Supervisor Pointer Masking */
- [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
- [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
- write_spmmask },
- [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
- write_spmbase },
-
/* Performance Counters */
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index fdde243e04..71ee8bab19 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -152,10 +152,7 @@ static const VMStateDescription vmstate_vector = {
static bool pointermasking_needed(void *opaque)
{
- RISCVCPU *cpu = opaque;
- CPURISCVState *env = &cpu->env;
-
- return riscv_has_ext(env, RVJ);
+ return false;
}
static const VMStateDescription vmstate_pointermasking = {
@@ -164,14 +161,6 @@ static const VMStateDescription vmstate_pointermasking = {
.minimum_version_id = 1,
.needed = pointermasking_needed,
.fields = (VMStateField[]) {
- VMSTATE_UINTTL(env.mmte, RISCVCPU),
- VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
- VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
- VMSTATE_UINTTL(env.spmmask, RISCVCPU),
- VMSTATE_UINTTL(env.spmbase, RISCVCPU),
- VMSTATE_UINTTL(env.upmmask, RISCVCPU),
- VMSTATE_UINTTL(env.upmbase, RISCVCPU),
-
VMSTATE_END_OF_LIST()
}
};
@@ -267,7 +256,6 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
CPURISCVState *env = &cpu->env;
env->xl = cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
return 0;
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 8a35683a34..5f5ba8bcf2 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -788,7 +788,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
MISA_CFG(RVS, true),
MISA_CFG(RVU, true),
MISA_CFG(RVH, true),
- MISA_CFG(RVJ, false),
MISA_CFG(RVV, false),
MISA_CFG(RVG, false),
};
@@ -964,8 +963,8 @@ static void riscv_init_max_cpu_extensions(Object *obj)
CPURISCVState *env = &cpu->env;
const RISCVCPUMultiExtConfig *prop;
- /* Enable RVG, RVJ and RVV that are disabled by default */
- riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+ /* Enable RVG, RVV that are disabled by default */
+ riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0be79bb16..6b4b9a671c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
-/* globals for PM CSRs */
-static TCGv pm_mask;
-static TCGv pm_base;
/*
* If an operation is being performed on less than TARGET_LONG_BITS,
@@ -106,9 +103,6 @@ typedef struct DisasContext {
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
- /* PointerMasking extension */
- bool pm_mask_enabled;
- bool pm_base_enabled;
/* Use icount trigger for native debug */
bool itrigger;
/* FRM is known to contain a valid value. */
@@ -582,14 +576,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
- if (ctx->pm_mask_enabled) {
- tcg_gen_andc_tl(addr, addr, pm_mask);
- } else if (get_address_xl(ctx) == MXL_RV32) {
+ if (get_address_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
- if (ctx->pm_base_enabled) {
- tcg_gen_or_tl(addr, addr, pm_base);
- }
return addr;
}
@@ -601,14 +590,9 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_add_tl(addr, src1, offs);
- if (ctx->pm_mask_enabled) {
- tcg_gen_andc_tl(addr, addr, pm_mask);
- } else if (get_xl(ctx) == MXL_RV32) {
+ if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
- if (ctx->pm_base_enabled) {
- tcg_gen_or_tl(addr, addr, pm_base);
- }
return addr;
}
@@ -1192,8 +1176,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
- ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
- ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
@@ -1325,9 +1307,4 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
"load_val");
- /* Assign PM CSRs to tcg globals */
- pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask),
- "pmmask");
- pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase),
- "pmbase");
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c1c3a4d1ea..8e7a8e80a0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -94,7 +94,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
- return (addr & ~env->cur_pmmask) | env->cur_pmbase;
+ return addr;
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-09 10:29 ` [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
@ 2024-01-09 10:29 ` Alexey Baturo
2024-01-22 7:04 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
` (4 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Alexey Baturo @ 2024-01-09 10:29 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.h | 8 ++++++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++++++++++
target/riscv/machine.c | 10 +++++++---
target/riscv/pmp.c | 13 ++++++++++---
target/riscv/pmp.h | 11 ++++++-----
7 files changed, 48 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a43c8fba57..c9bed5c9fc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -101,6 +101,14 @@ typedef enum {
EXT_STATUS_DIRTY,
} RISCVExtStatus;
+/* Enum holds PMM field values for Zjpm v0.8 extension */
+typedef enum {
+ PMM_FIELD_DISABLED = 0,
+ PMM_FIELD_RESERVED = 1,
+ PMM_FIELD_PMLEN7 = 2,
+ PMM_FIELD_PMLEN16 = 3,
+} RISCVPmPmm;
+
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1c92458a01..7cf1049bf4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -715,6 +715,7 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_PMM (3ULL << 32)
#define MENVCFG_ADUE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63)
@@ -728,11 +729,13 @@ typedef enum RISCVException {
#define SENVCFG_CBIE MENVCFG_CBIE
#define SENVCFG_CBCFE MENVCFG_CBCFE
#define SENVCFG_CBZE MENVCFG_CBZE
+#define SENVCFG_PMM MENVCFG_PMM
#define HENVCFG_FIOM MENVCFG_FIOM
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_PMM MENVCFG_PMM
#define HENVCFG_ADUE MENVCFG_ADUE
#define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index f4605fb190..201f8af6ae 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -113,6 +113,9 @@ struct RISCVCPUConfig {
bool ext_ssaia;
bool ext_sscofpmf;
bool ext_smepmp;
+ bool ext_ssnpm;
+ bool ext_smnpm;
+ bool ext_smmpm;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ea4e1ac6ef..a67ba30494 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -527,6 +527,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
if (riscv_cpu_cfg(env)->ext_zkr) {
return RISCV_EXCP_NONE;
}
+ if (riscv_cpu_cfg(env)->ext_smmpm) {
+ return RISCV_EXCP_NONE;
+ }
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -2030,6 +2033,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_ADUE : 0);
}
+ /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+ if (((val & MENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+ mask |= MENVCFG_PMM;
+ }
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
@@ -2074,6 +2081,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
+ /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+ if (((val & SENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+ mask |= SENVCFG_PMM;
+ }
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 71ee8bab19..0ad593ed5a 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -152,15 +152,19 @@ static const VMStateDescription vmstate_vector = {
static bool pointermasking_needed(void *opaque)
{
- return false;
+ RISCVCPU *cpu = opaque;
+ return cpu->cfg.ext_ssnpm || cpu->cfg.ext_smnpm || cpu->cfg.ext_smmpm;
}
static const VMStateDescription vmstate_pointermasking = {
.name = "cpu/pointer_masking",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = pointermasking_needed,
.fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.mseccfg, RISCVCPU),
+ VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
+ VMSTATE_UINTTL(env.menvcfg, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 162e88a90a..893ccd58d8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -576,6 +576,12 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
{
int i;
+ uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
+
+ /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+ if (((val & MSECCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+ mask |= MSECCFG_PMM;
+ }
trace_mseccfg_csr_write(env->mhartid, val);
@@ -591,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
if (riscv_cpu_cfg(env)->ext_smepmp) {
/* Sticky bits */
- val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
- if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
+ val |= (env->mseccfg & mask);
+ if ((val ^ env->mseccfg) & mask) {
tlb_flush(env_cpu(env));
}
} else {
- val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
+ mask |= MSECCFG_RLB;
+ val &= ~(mask);
}
env->mseccfg = val;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 9af8614cd4..b3ca51c26d 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -40,11 +40,12 @@ typedef enum {
} pmp_am_t;
typedef enum {
- MSECCFG_MML = 1 << 0,
- MSECCFG_MMWP = 1 << 1,
- MSECCFG_RLB = 1 << 2,
- MSECCFG_USEED = 1 << 8,
- MSECCFG_SSEED = 1 << 9
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2,
+ MSECCFG_USEED = 1 << 8,
+ MSECCFG_SSEED = 1 << 9,
+ MSECCFG_PMM = 3UL << 32,
} mseccfg_field_t;
typedef struct {
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-09 10:29 ` [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2024-01-09 10:29 ` [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
@ 2024-01-09 10:29 ` Alexey Baturo
2024-01-18 17:21 ` Deepak Gupta
2024-01-09 10:29 ` [PATCH v4 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
` (3 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Alexey Baturo @ 2024-01-09 10:29 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.h | 4 +++
target/riscv/cpu_helper.c | 58 +++++++++++++++++++++++++++++++++++++++
2 files changed, 62 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c9bed5c9fc..1c8979c1c8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -671,6 +671,10 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags);
+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
+int riscv_pm_get_pmlen(RISCVPmPmm pmm);
+
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a3d477d226..9640e4c2c5 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -139,6 +139,64 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
*pflags = flags;
}
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
+{
+ int pmm = 0;
+#ifndef CONFIG_USER_ONLY
+ int priv_mode = cpu_address_mode(env);
+ /* Get current PMM field */
+ switch (priv_mode) {
+ case PRV_M:
+ pmm = riscv_cpu_cfg(env)->ext_smmpm ?
+ get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ case PRV_S:
+ pmm = riscv_cpu_cfg(env)->ext_smnpm ?
+ get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ case PRV_U:
+ pmm = riscv_cpu_cfg(env)->ext_ssnpm ?
+ get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+#endif
+ return pmm;
+}
+
+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
+{
+ bool virt_mem_en = false;
+#ifndef CONFIG_USER_ONLY
+ int satp_mode = 0;
+ int priv_mode = cpu_address_mode(env);
+ /* Get current PMM field */
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ satp_mode = get_field(env->satp, SATP32_MODE);
+ } else {
+ satp_mode = get_field(env->satp, SATP64_MODE);
+ }
+ virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));
+#endif
+ return virt_mem_en;
+}
+
+int riscv_pm_get_pmlen(RISCVPmPmm pmm)
+{
+ switch (pmm) {
+ case PMM_FIELD_DISABLED:
+ return 0;
+ case PMM_FIELD_PMLEN7:
+ return 7;
+ case PMM_FIELD_PMLEN16:
+ return 16;
+ default:
+ g_assert_not_reached();
+ }
+ return -1;
+}
+
#ifndef CONFIG_USER_ONLY
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v4 4/6] target/riscv: Add pointer masking tb flags
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
` (2 preceding siblings ...)
2024-01-09 10:29 ` [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
@ 2024-01-09 10:29 ` Alexey Baturo
2024-01-22 7:01 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
` (2 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Alexey Baturo @ 2024-01-09 10:29 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +++++
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1c8979c1c8..0284ea418f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -545,6 +545,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1)
FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
FIELD(TB_FLAGS, PRIV, 22, 2)
FIELD(TB_FLAGS, AXL, 24, 2)
+/* If pointer masking should be applied and address sign extended */
+FIELD(TB_FLAGS, PM_PMM, 26, 2)
+FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9640e4c2c5..67bc51e510 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
RISCVCPU *cpu = env_archcpu(env);
RISCVExtStatus fs, vs;
uint32_t flags = 0;
+ bool pm_signext = riscv_cpu_virt_mem_enabled(env);
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
@@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
*pflags = flags;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6b4b9a671c..2c89d749c0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -103,6 +103,9 @@ typedef struct DisasContext {
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
+ /* actual address width */
+ uint8_t addr_width;
+ bool addr_signed;
/* Use icount trigger for native debug */
bool itrigger;
/* FRM is known to contain a valid value. */
@@ -1176,6 +1179,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
+ ctx->addr_width = 0;
+ ctx->addr_signed = false;
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
` (3 preceding siblings ...)
2024-01-09 10:29 ` [PATCH v4 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
@ 2024-01-09 10:29 ` Alexey Baturo
2024-01-22 7:01 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
2024-01-22 6:52 ` [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alistair Francis
6 siblings, 1 reply; 19+ messages in thread
From: Alexey Baturo @ 2024-01-09 10:29 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 22 ++++++++++++++++------
target/riscv/vector_helper.c | 13 +++++++++++++
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2c89d749c0..457de381c7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -579,8 +579,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
- if (get_address_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32u_tl(addr, addr);
+ if (ctx->addr_signed) {
+ tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
+ } else {
+ tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
}
return addr;
@@ -593,8 +595,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_add_tl(addr, src1, offs);
- if (get_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32u_tl(addr, addr);
+ if (ctx->addr_signed) {
+ tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
+ } else {
+ tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
}
return addr;
}
@@ -1179,8 +1183,14 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
- ctx->addr_width = 0;
- ctx->addr_signed = false;
+ if (get_xl(ctx) == MXL_RV32) {
+ ctx->addr_width = 32;
+ ctx->addr_signed = false;
+ } else {
+ int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
+ ctx->addr_width = 64 - riscv_pm_get_pmlen(pm_pmm);
+ ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
+ }
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8e7a8e80a0..ff1178723c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -94,6 +94,19 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
+ RISCVPmPmm pmm = riscv_pm_get_pmm(env);
+ if (pmm == PMM_FIELD_DISABLED) {
+ return addr;
+ }
+ int pmlen = riscv_pm_get_pmlen(pmm);
+ bool signext = riscv_cpu_virt_mem_enabled(env);
+ addr = addr << pmlen;
+ /* sign/zero extend masked address by N-1 bit */
+ if (signext) {
+ addr = (target_long)addr >> pmlen;
+ } else {
+ addr = addr >> pmlen;
+ }
return addr;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
` (4 preceding siblings ...)
2024-01-09 10:29 ` [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
@ 2024-01-09 10:29 ` Alexey Baturo
2024-01-22 6:54 ` Alistair Francis
2024-01-22 6:52 ` [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alistair Francis
6 siblings, 1 reply; 19+ messages in thread
From: Alexey Baturo @ 2024-01-09 10:29 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d8de1f1890..44ebd80aba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm),
+ ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm),
+ ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
@@ -1336,6 +1339,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
+ /* Zjpm v0.8 extensions */
+ MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
+ MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
+ MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
+
MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-09 10:29 ` [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
@ 2024-01-18 17:21 ` Deepak Gupta
2024-01-18 20:50 ` Richard Henderson
0 siblings, 1 reply; 19+ messages in thread
From: Deepak Gupta @ 2024-01-18 17:21 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Tue, Jan 9, 2024 at 2:31 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
> +
> +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
> +{
> + bool virt_mem_en = false;
> +#ifndef CONFIG_USER_ONLY
> + int satp_mode = 0;
> + int priv_mode = cpu_address_mode(env);
> + /* Get current PMM field */
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> + satp_mode = get_field(env->satp, SATP32_MODE);
> + } else {
> + satp_mode = get_field(env->satp, SATP64_MODE);
> + }
> + virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));
> +#endif
> + return virt_mem_en;
Obsessing a little bit on how to test PM enabled binaries with qemu-user.
If we return false above then we're not allowed to test binaries with
pointer masking enabled with qemu-user.
That use case is not required?
> +}
> +
> +int riscv_pm_get_pmlen(RISCVPmPmm pmm)
> +{
> + switch (pmm) {
> + case PMM_FIELD_DISABLED:
> + return 0;
> + case PMM_FIELD_PMLEN7:
> + return 7;
> + case PMM_FIELD_PMLEN16:
> + return 16;
> + default:
> + g_assert_not_reached();
> + }
> + return -1;
> +}
> +
> #ifndef CONFIG_USER_ONLY
>
> /*
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-18 17:21 ` Deepak Gupta
@ 2024-01-18 20:50 ` Richard Henderson
2024-01-18 22:40 ` Deepak Gupta
0 siblings, 1 reply; 19+ messages in thread
From: Richard Henderson @ 2024-01-18 20:50 UTC (permalink / raw)
To: Deepak Gupta, Alexey Baturo
Cc: zhiwei_liu, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
On 1/19/24 04:21, Deepak Gupta wrote:
> On Tue, Jan 9, 2024 at 2:31 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>>
>> From: Alexey Baturo <baturo.alexey@gmail.com>
>>
>> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>> ---
>
>> +
>> +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
>> +{
>> + bool virt_mem_en = false;
>> +#ifndef CONFIG_USER_ONLY
>> + int satp_mode = 0;
>> + int priv_mode = cpu_address_mode(env);
>> + /* Get current PMM field */
>> + if (riscv_cpu_mxl(env) == MXL_RV32) {
>> + satp_mode = get_field(env->satp, SATP32_MODE);
>> + } else {
>> + satp_mode = get_field(env->satp, SATP64_MODE);
>> + }
>> + virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));
>> +#endif
>> + return virt_mem_en;
>
> Obsessing a little bit on how to test PM enabled binaries with qemu-user.
> If we return false above then we're not allowed to test binaries with
> pointer masking enabled with qemu-user.
> That use case is not required?
In a previous round I suggested that the ifdefs are not necessary.
But for now it will always be off for qemu-user.
At some point pointer masking will be in hardware, and the kernel will gain support for
it, and there will likely be a prctl() added for it. At the point the kernel finalizes
the API, you will be able to enable pointer masking for qemu-user.
r~
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-18 20:50 ` Richard Henderson
@ 2024-01-18 22:40 ` Deepak Gupta
2024-01-20 7:37 ` Richard Henderson
0 siblings, 1 reply; 19+ messages in thread
From: Deepak Gupta @ 2024-01-18 22:40 UTC (permalink / raw)
To: Richard Henderson
Cc: Alexey Baturo, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Thu, Jan 18, 2024 at 12:50 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 1/19/24 04:21, Deepak Gupta wrote:
> > On Tue, Jan 9, 2024 at 2:31 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
> >>
> >> From: Alexey Baturo <baturo.alexey@gmail.com>
> >>
> >> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> >> ---
> >
> >> +
> >> +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
> >> +{
> >> + bool virt_mem_en = false;
> >> +#ifndef CONFIG_USER_ONLY
> >> + int satp_mode = 0;
> >> + int priv_mode = cpu_address_mode(env);
> >> + /* Get current PMM field */
> >> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> >> + satp_mode = get_field(env->satp, SATP32_MODE);
> >> + } else {
> >> + satp_mode = get_field(env->satp, SATP64_MODE);
> >> + }
> >> + virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));
> >> +#endif
> >> + return virt_mem_en;
> >
> > Obsessing a little bit on how to test PM enabled binaries with qemu-user.
> > If we return false above then we're not allowed to test binaries with
> > pointer masking enabled with qemu-user.
> > That use case is not required?
>
> In a previous round I suggested that the ifdefs are not necessary.
> But for now it will always be off for qemu-user.
>
> At some point pointer masking will be in hardware, and the kernel will gain support for
> it, and there will likely be a prctl() added for it. At the point the kernel finalizes
> the API, you will be able to enable pointer masking for qemu-user.
I am sure I am missing some important detail here, BUT...
How is it different from aarch64 "top byte ignore".
I think commit: 16c8497 enables top byte ignore for user pointers and
by default for qemu-user for aarch64 target.
IIRC, user <--> kernel abi is only needed for pointers that are passed
to the kernel.
And in the case of qemu-user, we are talking about the host kernel.
Since arm64 had TBI enabled for qemu-user for a while and I imagine it
works on x86 host kernel
(assuming qemu-user is sanitizing pointers)
Same should work for risc-v qemu-user, right?
>
>
> r~
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-18 22:40 ` Deepak Gupta
@ 2024-01-20 7:37 ` Richard Henderson
2024-01-21 7:13 ` Alexey Baturo
0 siblings, 1 reply; 19+ messages in thread
From: Richard Henderson @ 2024-01-20 7:37 UTC (permalink / raw)
To: Deepak Gupta
Cc: Alexey Baturo, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On 1/19/24 09:40, Deepak Gupta wrote:
> On Thu, Jan 18, 2024 at 12:50 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> At some point pointer masking will be in hardware, and the kernel will gain support for
>> it, and there will likely be a prctl() added for it. At the point the kernel finalizes
>> the API, you will be able to enable pointer masking for qemu-user.
>
> I am sure I am missing some important detail here, BUT...
>
> How is it different from aarch64 "top byte ignore".
It is very similar, yes.
> I think commit: 16c8497 enables top byte ignore for user pointers and
> by default for qemu-user for aarch64 target.
Not quite, no.
commit 0e0c030c681730f3ec55ba3b223b608a8f3e8282
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Fri Feb 12 10:48:51 2021 -0800
linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
is more relevant.
> IIRC, user <--> kernel abi is only needed for pointers that are passed
> to the kernel.
It is also needed to *enable* pointer masking at all.
For aarch64, TBI has been enabled for user-space since the beginning, but that is not true
for riscv. Therefore there will be a need for a syscall to opt in and enable pointer masking.
> And in the case of qemu-user, we are talking about the host kernel.
No, we are not. We are always emulating the guest kernel.
r~
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-20 7:37 ` Richard Henderson
@ 2024-01-21 7:13 ` Alexey Baturo
2024-01-23 17:44 ` Deepak Gupta
0 siblings, 1 reply; 19+ messages in thread
From: Alexey Baturo @ 2024-01-21 7:13 UTC (permalink / raw)
To: Richard Henderson
Cc: Deepak Gupta, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
[-- Attachment #1: Type: text/plain, Size: 2012 bytes --]
Hi,
Having the feature to run binaries with pointer masking on qemu-user is
really nice, but I see this patch series as an initial support.
Obviously there'll be more patches and fixes for pointer masking as soon as
arch tests are ready.
I suggest supporting qemu-user in the next patches, but make sure we do
this before claiming 100% support for pointer masking.
@Deepak Gupta <debug@rivosinc.com> what do you think?
Thanks
сб, 20 янв. 2024 г. в 10:37, Richard Henderson <richard.henderson@linaro.org
>:
> On 1/19/24 09:40, Deepak Gupta wrote:
> > On Thu, Jan 18, 2024 at 12:50 PM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >> At some point pointer masking will be in hardware, and the kernel will
> gain support for
> >> it, and there will likely be a prctl() added for it. At the point the
> kernel finalizes
> >> the API, you will be able to enable pointer masking for qemu-user.
> >
> > I am sure I am missing some important detail here, BUT...
> >
> > How is it different from aarch64 "top byte ignore".
>
> It is very similar, yes.
>
> > I think commit: 16c8497 enables top byte ignore for user pointers and
> > by default for qemu-user for aarch64 target.
>
> Not quite, no.
>
> commit 0e0c030c681730f3ec55ba3b223b608a8f3e8282
> Author: Richard Henderson <richard.henderson@linaro.org>
> Date: Fri Feb 12 10:48:51 2021 -0800
>
> linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
>
> is more relevant.
>
> > IIRC, user <--> kernel abi is only needed for pointers that are passed
> > to the kernel.
>
> It is also needed to *enable* pointer masking at all.
>
> For aarch64, TBI has been enabled for user-space since the beginning, but
> that is not true
> for riscv. Therefore there will be a need for a syscall to opt in and
> enable pointer masking.
>
> > And in the case of qemu-user, we are talking about the host kernel.
>
> No, we are not. We are always emulating the guest kernel.
>
>
> r~
>
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
` (5 preceding siblings ...)
2024-01-09 10:29 ` [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
@ 2024-01-22 6:52 ` Alistair Francis
6 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2024-01-22 6:52 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Tue, Jan 9, 2024 at 8:31 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Hi,
>
Do you mind including a pointer to the exact spec (a Github link with
the SHA or tag is great) that you are targeting? We are having issues
with a different spec, so it will be helpful in future to know exactly
what the developer was targeting in the cover letter
Alistair
> Patch series updated after the suggested comments:
> - removed J-letter extension as it's unused
> - renamed and fixed function to detect if address should be sign-extended
> - zeroed unused context variables and moved computation logic to another patch
> - bumped pointer masking version_id and minimum_version_id by 1
>
> Thanks
>
> [v3]:
> There patches are updated after Richard's comments:
> - moved new tb flags to the end
> - used tcg_gen_(s)extract to get the final address
> - properly handle CONFIG_USER_ONLY
>
> Thanks
>
> [v2]:
> As per Richard's suggestion I made pmm field part of tb_flags.
> It allowed to get rid of global variable to store pmlen.
> Also it allowed to simplify all the machinery around it.
>
> Thanks
>
> [v1]:
> Hi all,
>
> It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore.
> Compared to the original implementation with explicit base and mask CSRs, we now only have
> several fixed options for number of masked bits which are set using existing CSRs.
> The changes have been tested with handwritten assembly tests and LLVM HWASAN
> test suite.
>
> Thanks
>
> Alexey Baturo (6):
> target/riscv: Remove obsolete pointer masking extension code.
> target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part
> of Zjpm v0.8
> target/riscv: Add helper functions to calculate current number of
> masked bits for pointer masking
> target/riscv: Add pointer masking tb flags
> target/riscv: Update address modify functions to take into account
> pointer masking
> target/riscv: Enable updates for pointer masking variables and thus
> enable pointer masking extension
>
> target/riscv/cpu.c | 21 +--
> target/riscv/cpu.h | 46 +++--
> target/riscv/cpu_bits.h | 90 +---------
> target/riscv/cpu_cfg.h | 3 +
> target/riscv/cpu_helper.c | 96 +++++-----
> target/riscv/csr.c | 337 ++---------------------------------
> target/riscv/machine.c | 16 +-
> target/riscv/pmp.c | 13 +-
> target/riscv/pmp.h | 11 +-
> target/riscv/tcg/tcg-cpu.c | 5 +-
> target/riscv/translate.c | 46 ++---
> target/riscv/vector_helper.c | 14 +-
> 12 files changed, 153 insertions(+), 545 deletions(-)
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code.
2024-01-09 10:29 ` [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
@ 2024-01-22 6:53 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2024-01-22 6:53 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Tue, Jan 9, 2024 at 8:30 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
> The newer version doesn't allow to specify custom mask or base for masking.
> Instead it allows only certain options for masking top bits.
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 13 +-
> target/riscv/cpu.h | 33 +---
> target/riscv/cpu_bits.h | 87 ----------
> target/riscv/cpu_helper.c | 52 ------
> target/riscv/csr.c | 326 -----------------------------------
> target/riscv/machine.c | 14 +-
> target/riscv/tcg/tcg-cpu.c | 5 +-
> target/riscv/translate.c | 27 +--
> target/riscv/vector_helper.c | 2 +-
> 9 files changed, 14 insertions(+), 545 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 83c7c0cf07..d8de1f1890 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -40,7 +40,7 @@
> /* RISC-V CPU definitions */
> static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
> const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
> - RVC, RVS, RVU, RVH, RVJ, RVG, 0};
> + RVC, RVS, RVU, RVH, RVG, 0};
>
> /*
> * From vector_helper.c
> @@ -710,13 +710,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> CSR_MSCRATCH,
> CSR_SSCRATCH,
> CSR_SATP,
> - CSR_MMTE,
> - CSR_UPMBASE,
> - CSR_UPMMASK,
> - CSR_SPMBASE,
> - CSR_SPMMASK,
> - CSR_MPMBASE,
> - CSR_MPMMASK,
> };
>
> for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
> @@ -891,8 +884,6 @@ static void riscv_cpu_reset_hold(Object *obj)
> }
> i++;
> }
> - /* mmte is supposed to have pm.current hardwired to 1 */
> - env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
>
> /*
> * Clear mseccfg and unlock all the PMP entries upon reset.
> @@ -906,7 +897,6 @@ static void riscv_cpu_reset_hold(Object *obj)
> pmp_unlock_entries(env);
> #endif
> env->xl = riscv_cpu_mxl(env);
> - riscv_cpu_update_mask(env);
> cs->exception_index = RISCV_EXCP_NONE;
> env->load_res = -1;
> set_default_nan_mode(1, &env->fp_status);
> @@ -1251,7 +1241,6 @@ static const MISAExtInfo misa_ext_info_arr[] = {
> MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
> MISA_EXT_INFO(RVU, "u", "User-level instructions"),
> MISA_EXT_INFO(RVH, "h", "Hypervisor"),
> - MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
> MISA_EXT_INFO(RVV, "v", "Vector operations"),
> MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
> };
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d74b361be6..a43c8fba57 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -67,7 +67,6 @@ typedef struct CPUArchState CPURISCVState;
> #define RVS RV('S')
> #define RVU RV('U')
> #define RVH RV('H')
> -#define RVJ RV('J')
> #define RVG RV('G')
>
> extern const uint32_t misa_bits[];
> @@ -374,18 +373,7 @@ struct CPUArchState {
> /* True if in debugger mode. */
> bool debugger;
>
> - /*
> - * CSRs for PointerMasking extension
> - */
> - target_ulong mmte;
> - target_ulong mpmmask;
> - target_ulong mpmbase;
> - target_ulong spmmask;
> - target_ulong spmbase;
> - target_ulong upmmask;
> - target_ulong upmbase;
> -
> - /* CSRs for execution environment configuration */
> + /* CSRs for execution enviornment configuration */
> uint64_t menvcfg;
> uint64_t mstateen[SMSTATEEN_MAX_COUNT];
> uint64_t hstateen[SMSTATEEN_MAX_COUNT];
> @@ -393,8 +381,6 @@ struct CPUArchState {
> target_ulong senvcfg;
> uint64_t henvcfg;
> #endif
> - target_ulong cur_pmmask;
> - target_ulong cur_pmbase;
>
> /* Fields from here on are preserved across CPU reset. */
> QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> @@ -543,17 +529,14 @@ FIELD(TB_FLAGS, VILL, 14, 1)
> FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
> /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
> FIELD(TB_FLAGS, XL, 16, 2)
> -/* If PointerMasking should be applied */
> -FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
> -FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
> -FIELD(TB_FLAGS, VTA, 20, 1)
> -FIELD(TB_FLAGS, VMA, 21, 1)
> +FIELD(TB_FLAGS, VTA, 18, 1)
> +FIELD(TB_FLAGS, VMA, 19, 1)
> /* Native debug itrigger */
> -FIELD(TB_FLAGS, ITRIGGER, 22, 1)
> +FIELD(TB_FLAGS, ITRIGGER, 20, 1)
> /* Virtual mode enabled */
> -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
> -FIELD(TB_FLAGS, PRIV, 24, 2)
> -FIELD(TB_FLAGS, AXL, 26, 2)
> +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
> +FIELD(TB_FLAGS, PRIV, 22, 2)
> +FIELD(TB_FLAGS, AXL, 24, 2)
>
> #ifdef TARGET_RISCV32
> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> @@ -680,8 +663,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
> void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> uint64_t *cs_base, uint32_t *pflags);
>
> -void riscv_cpu_update_mask(CPURISCVState *env);
> -
> RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask);
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index ebd7917d49..1c92458a01 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -491,37 +491,6 @@
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
>
> -/*
> - * User PointerMasking registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_UMTE 0x4c0
> -#define CSR_UPMMASK 0x4c1
> -#define CSR_UPMBASE 0x4c2
> -
> -/*
> - * Machine PointerMasking registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_MMTE 0x3c0
> -#define CSR_MPMMASK 0x3c1
> -#define CSR_MPMBASE 0x3c2
> -
> -/*
> - * Supervisor PointerMaster registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_SMTE 0x1c0
> -#define CSR_SPMMASK 0x1c1
> -#define CSR_SPMBASE 0x1c2
> -
> -/*
> - * Hypervisor PointerMaster registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_VSMTE 0x2c0
> -#define CSR_VSPMMASK 0x2c1
> -#define CSR_VSPMBASE 0x2c2
> #define CSR_SCOUNTOVF 0xda0
>
> /* Crypto Extension */
> @@ -741,11 +710,6 @@ typedef enum RISCVException {
> #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
> #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
>
> -/* General PointerMasking CSR bits */
> -#define PM_ENABLE 0x00000001ULL
> -#define PM_CURRENT 0x00000002ULL
> -#define PM_INSN 0x00000004ULL
> -
> /* Execution environment configuration bits */
> #define MENVCFG_FIOM BIT(0)
> #define MENVCFG_CBIE (3UL << 4)
> @@ -778,57 +742,6 @@ typedef enum RISCVException {
> #define HENVCFGH_PBMTE MENVCFGH_PBMTE
> #define HENVCFGH_STCE MENVCFGH_STCE
>
> -/* Offsets for every pair of control bits per each priv level */
> -#define XS_OFFSET 0ULL
> -#define U_OFFSET 2ULL
> -#define S_OFFSET 5ULL
> -#define M_OFFSET 8ULL
> -
> -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
> -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
> -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
> -#define U_PM_INSN (PM_INSN << U_OFFSET)
> -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
> -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
> -#define S_PM_INSN (PM_INSN << S_OFFSET)
> -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
> -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
> -#define M_PM_INSN (PM_INSN << M_OFFSET)
> -
> -/* mmte CSR bits */
> -#define MMTE_PM_XS_BITS PM_XS_BITS
> -#define MMTE_U_PM_ENABLE U_PM_ENABLE
> -#define MMTE_U_PM_CURRENT U_PM_CURRENT
> -#define MMTE_U_PM_INSN U_PM_INSN
> -#define MMTE_S_PM_ENABLE S_PM_ENABLE
> -#define MMTE_S_PM_CURRENT S_PM_CURRENT
> -#define MMTE_S_PM_INSN S_PM_INSN
> -#define MMTE_M_PM_ENABLE M_PM_ENABLE
> -#define MMTE_M_PM_CURRENT M_PM_CURRENT
> -#define MMTE_M_PM_INSN M_PM_INSN
> -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
> - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
> - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
> - MMTE_PM_XS_BITS)
> -
> -/* (v)smte CSR bits */
> -#define SMTE_PM_XS_BITS PM_XS_BITS
> -#define SMTE_U_PM_ENABLE U_PM_ENABLE
> -#define SMTE_U_PM_CURRENT U_PM_CURRENT
> -#define SMTE_U_PM_INSN U_PM_INSN
> -#define SMTE_S_PM_ENABLE S_PM_ENABLE
> -#define SMTE_S_PM_CURRENT S_PM_CURRENT
> -#define SMTE_S_PM_INSN S_PM_INSN
> -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
> - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
> - SMTE_PM_XS_BITS)
> -
> -/* umte CSR bits */
> -#define UMTE_U_PM_ENABLE U_PM_ENABLE
> -#define UMTE_U_PM_CURRENT U_PM_CURRENT
> -#define UMTE_U_PM_INSN U_PM_INSN
> -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
> -
> /* MISELECT, SISELECT, and VSISELECT bits (AIA) */
> #define ISELECT_IPRIO0 0x30
> #define ISELECT_IPRIO15 0x3f
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e7e23b34f4..a3d477d226 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -135,61 +135,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
> flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
> flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
> - if (env->cur_pmmask != 0) {
> - flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
> - }
> - if (env->cur_pmbase != 0) {
> - flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
> - }
>
> *pflags = flags;
> }
>
> -void riscv_cpu_update_mask(CPURISCVState *env)
> -{
> - target_ulong mask = 0, base = 0;
> - RISCVMXL xl = env->xl;
> - /*
> - * TODO: Current RVJ spec does not specify
> - * how the extension interacts with XLEN.
> - */
> -#ifndef CONFIG_USER_ONLY
> - int mode = cpu_address_mode(env);
> - xl = cpu_get_xl(env, mode);
> - if (riscv_has_ext(env, RVJ)) {
> - switch (mode) {
> - case PRV_M:
> - if (env->mmte & M_PM_ENABLE) {
> - mask = env->mpmmask;
> - base = env->mpmbase;
> - }
> - break;
> - case PRV_S:
> - if (env->mmte & S_PM_ENABLE) {
> - mask = env->spmmask;
> - base = env->spmbase;
> - }
> - break;
> - case PRV_U:
> - if (env->mmte & U_PM_ENABLE) {
> - mask = env->upmmask;
> - base = env->upmbase;
> - }
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - }
> -#endif
> - if (xl == MXL_RV32) {
> - env->cur_pmmask = mask & UINT32_MAX;
> - env->cur_pmbase = base & UINT32_MAX;
> - } else {
> - env->cur_pmmask = mask;
> - env->cur_pmbase = base;
> - }
> -}
> -
> #ifndef CONFIG_USER_ONLY
>
> /*
> @@ -721,7 +670,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> env->priv = newpriv;
> env->xl = cpu_recompute_xl(env);
> - riscv_cpu_update_mask(env);
>
> /*
> * Clear the load reservation - otherwise a reservation placed in one
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fde7ce1a53..ea4e1ac6ef 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -483,16 +483,6 @@ static RISCVException hgatp(CPURISCVState *env, int csrno)
> return hmode(env, csrno);
> }
>
> -/* Checks if PointerMasking registers could be accessed */
> -static RISCVException pointer_masking(CPURISCVState *env, int csrno)
> -{
> - /* Check if j-ext is present */
> - if (riscv_has_ext(env, RVJ)) {
> - return RISCV_EXCP_NONE;
> - }
> - return RISCV_EXCP_ILLEGAL_INST;
> -}
> -
> static int aia_hmode(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_ssaia) {
> @@ -1355,7 +1345,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> env->xl = cpu_recompute_xl(env);
> }
>
> - riscv_cpu_update_mask(env);
> return RISCV_EXCP_NONE;
> }
>
> @@ -3900,302 +3889,6 @@ static RISCVException read_tinfo(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -/*
> - * Functions to access Pointer Masking feature registers
> - * We have to check if current priv lvl could modify
> - * csr in given mode
> - */
> -static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
> -{
> - int csr_priv = get_field(csrno, 0x300);
> - int pm_current;
> -
> - if (env->debugger) {
> - return false;
> - }
> - /*
> - * If priv lvls differ that means we're accessing csr from higher priv lvl,
> - * so allow the access
> - */
> - if (env->priv != csr_priv) {
> - return false;
> - }
> - switch (env->priv) {
> - case PRV_M:
> - pm_current = get_field(env->mmte, M_PM_CURRENT);
> - break;
> - case PRV_S:
> - pm_current = get_field(env->mmte, S_PM_CURRENT);
> - break;
> - case PRV_U:
> - pm_current = get_field(env->mmte, U_PM_CURRENT);
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
> - return !pm_current;
> -}
> -
> -static RISCVException read_mmte(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mmte & MMTE_MASK;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_mmte(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> - target_ulong wpri_val = val & MMTE_MASK;
> -
> - if (val != wpri_val) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> - TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
> - val, "vs expected 0x", wpri_val);
> - }
> - /* for machine mode pm.current is hardwired to 1 */
> - wpri_val |= MMTE_M_PM_CURRENT;
> -
> - /* hardwiring pm.instruction bit to 0, since it's not supported yet */
> - wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
> - env->mmte = wpri_val | EXT_STATUS_DIRTY;
> - riscv_cpu_update_mask(env);
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_smte(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mmte & SMTE_MASK;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_smte(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - target_ulong wpri_val = val & SMTE_MASK;
> -
> - if (val != wpri_val) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> - TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
> - val, "vs expected 0x", wpri_val);
> - }
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - wpri_val |= (env->mmte & ~SMTE_MASK);
> - write_mmte(env, csrno, wpri_val);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_umte(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mmte & UMTE_MASK;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_umte(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - target_ulong wpri_val = val & UMTE_MASK;
> -
> - if (val != wpri_val) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> - TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
> - val, "vs expected 0x", wpri_val);
> - }
> -
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - wpri_val |= (env->mmte & ~UMTE_MASK);
> - write_mmte(env, csrno, wpri_val);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mpmmask;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - env->mpmmask = val;
> - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> - env->cur_pmmask = val;
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_spmmask(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->spmmask;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_spmmask(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->spmmask = val;
> - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> - env->cur_pmmask = val;
> - if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> - env->cur_pmmask &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_upmmask(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->upmmask;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_upmmask(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->upmmask = val;
> - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> - env->cur_pmmask = val;
> - if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> - env->cur_pmmask &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mpmbase;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - env->mpmbase = val;
> - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> - env->cur_pmbase = val;
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_spmbase(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->spmbase;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_spmbase(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->spmbase = val;
> - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> - env->cur_pmbase = val;
> - if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> - env->cur_pmbase &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_upmbase(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->upmbase;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_upmbase(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->upmbase = val;
> - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> - env->cur_pmbase = val;
> - if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> - env->cur_pmbase &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> #endif
>
> /* Crypto Extension */
> @@ -4800,25 +4493,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
> [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
>
> - /* User Pointer Masking */
> - [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
> - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
> - write_upmmask },
> - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
> - write_upmbase },
> - /* Machine Pointer Masking */
> - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
> - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
> - write_mpmmask },
> - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
> - write_mpmbase },
> - /* Supervisor Pointer Masking */
> - [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
> - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
> - write_spmmask },
> - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
> - write_spmbase },
> -
> /* Performance Counters */
> [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
> [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index fdde243e04..71ee8bab19 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -152,10 +152,7 @@ static const VMStateDescription vmstate_vector = {
>
> static bool pointermasking_needed(void *opaque)
> {
> - RISCVCPU *cpu = opaque;
> - CPURISCVState *env = &cpu->env;
> -
> - return riscv_has_ext(env, RVJ);
> + return false;
> }
>
> static const VMStateDescription vmstate_pointermasking = {
> @@ -164,14 +161,6 @@ static const VMStateDescription vmstate_pointermasking = {
> .minimum_version_id = 1,
> .needed = pointermasking_needed,
> .fields = (VMStateField[]) {
> - VMSTATE_UINTTL(env.mmte, RISCVCPU),
> - VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
> - VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
> - VMSTATE_UINTTL(env.spmmask, RISCVCPU),
> - VMSTATE_UINTTL(env.spmbase, RISCVCPU),
> - VMSTATE_UINTTL(env.upmmask, RISCVCPU),
> - VMSTATE_UINTTL(env.upmbase, RISCVCPU),
> -
> VMSTATE_END_OF_LIST()
> }
> };
> @@ -267,7 +256,6 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
> CPURISCVState *env = &cpu->env;
>
> env->xl = cpu_recompute_xl(env);
> - riscv_cpu_update_mask(env);
> return 0;
> }
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 8a35683a34..5f5ba8bcf2 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -788,7 +788,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> MISA_CFG(RVS, true),
> MISA_CFG(RVU, true),
> MISA_CFG(RVH, true),
> - MISA_CFG(RVJ, false),
> MISA_CFG(RVV, false),
> MISA_CFG(RVG, false),
> };
> @@ -964,8 +963,8 @@ static void riscv_init_max_cpu_extensions(Object *obj)
> CPURISCVState *env = &cpu->env;
> const RISCVCPUMultiExtConfig *prop;
>
> - /* Enable RVG, RVJ and RVV that are disabled by default */
> - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
> + /* Enable RVG, RVV that are disabled by default */
> + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVV);
>
> for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
> isa_ext_update_enabled(cpu, prop->offset, true);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f0be79bb16..6b4b9a671c 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
> static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> static TCGv load_res;
> static TCGv load_val;
> -/* globals for PM CSRs */
> -static TCGv pm_mask;
> -static TCGv pm_base;
>
> /*
> * If an operation is being performed on less than TARGET_LONG_BITS,
> @@ -106,9 +103,6 @@ typedef struct DisasContext {
> bool vl_eq_vlmax;
> CPUState *cs;
> TCGv zero;
> - /* PointerMasking extension */
> - bool pm_mask_enabled;
> - bool pm_base_enabled;
> /* Use icount trigger for native debug */
> bool itrigger;
> /* FRM is known to contain a valid value. */
> @@ -582,14 +576,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_addi_tl(addr, src1, imm);
> - if (ctx->pm_mask_enabled) {
> - tcg_gen_andc_tl(addr, addr, pm_mask);
> - } else if (get_address_xl(ctx) == MXL_RV32) {
> + if (get_address_xl(ctx) == MXL_RV32) {
> tcg_gen_ext32u_tl(addr, addr);
> }
> - if (ctx->pm_base_enabled) {
> - tcg_gen_or_tl(addr, addr, pm_base);
> - }
>
> return addr;
> }
> @@ -601,14 +590,9 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_add_tl(addr, src1, offs);
> - if (ctx->pm_mask_enabled) {
> - tcg_gen_andc_tl(addr, addr, pm_mask);
> - } else if (get_xl(ctx) == MXL_RV32) {
> + if (get_xl(ctx) == MXL_RV32) {
> tcg_gen_ext32u_tl(addr, addr);
> }
> - if (ctx->pm_base_enabled) {
> - tcg_gen_or_tl(addr, addr, pm_base);
> - }
> return addr;
> }
>
> @@ -1192,8 +1176,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
> ctx->cs = cs;
> - ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
> - ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
> ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> ctx->zero = tcg_constant_tl(0);
> ctx->virt_inst_excp = false;
> @@ -1325,9 +1307,4 @@ void riscv_translate_init(void)
> "load_res");
> load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
> "load_val");
> - /* Assign PM CSRs to tcg globals */
> - pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask),
> - "pmmask");
> - pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase),
> - "pmbase");
> }
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index c1c3a4d1ea..8e7a8e80a0 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -94,7 +94,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
>
> static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
> {
> - return (addr & ~env->cur_pmmask) | env->cur_pmbase;
> + return addr;
> }
>
> /*
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension
2024-01-09 10:29 ` [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
@ 2024-01-22 6:54 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2024-01-22 6:54 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Tue, Jan 9, 2024 at 8:31 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
> target/riscv/cpu.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d8de1f1890..44ebd80aba 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm),
> + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm),
> + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> @@ -1336,6 +1339,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>
> MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
>
> + /* Zjpm v0.8 extensions */
> + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
> + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
> + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
As this isn't ratified yet can you add a "x-" in front the of the
names to indicate experimental
Alistair
> +
> MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
> MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
> MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking
2024-01-09 10:29 ` [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
@ 2024-01-22 7:01 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2024-01-22 7:01 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Tue, Jan 9, 2024 at 9:33 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 22 ++++++++++++++++------
> target/riscv/vector_helper.c | 13 +++++++++++++
> 2 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2c89d749c0..457de381c7 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -579,8 +579,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_addi_tl(addr, src1, imm);
> - if (get_address_xl(ctx) == MXL_RV32) {
> - tcg_gen_ext32u_tl(addr, addr);
> + if (ctx->addr_signed) {
> + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
> + } else {
> + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
> }
>
> return addr;
> @@ -593,8 +595,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_add_tl(addr, src1, offs);
> - if (get_xl(ctx) == MXL_RV32) {
> - tcg_gen_ext32u_tl(addr, addr);
> + if (ctx->addr_signed) {
> + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
> + } else {
> + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
> }
> return addr;
> }
> @@ -1179,8 +1183,14 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
> ctx->cs = cs;
> - ctx->addr_width = 0;
> - ctx->addr_signed = false;
> + if (get_xl(ctx) == MXL_RV32) {
> + ctx->addr_width = 32;
> + ctx->addr_signed = false;
> + } else {
> + int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
> + ctx->addr_width = 64 - riscv_pm_get_pmlen(pm_pmm);
> + ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
> + }
> ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> ctx->zero = tcg_constant_tl(0);
> ctx->virt_inst_excp = false;
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 8e7a8e80a0..ff1178723c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -94,6 +94,19 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
>
> static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
> {
> + RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> + if (pmm == PMM_FIELD_DISABLED) {
> + return addr;
> + }
> + int pmlen = riscv_pm_get_pmlen(pmm);
> + bool signext = riscv_cpu_virt_mem_enabled(env);
> + addr = addr << pmlen;
> + /* sign/zero extend masked address by N-1 bit */
> + if (signext) {
> + addr = (target_long)addr >> pmlen;
> + } else {
> + addr = addr >> pmlen;
> + }
> return addr;
> }
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 4/6] target/riscv: Add pointer masking tb flags
2024-01-09 10:29 ` [PATCH v4 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
@ 2024-01-22 7:01 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2024-01-22 7:01 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Tue, Jan 9, 2024 at 8:31 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 3 +++
> target/riscv/cpu_helper.c | 3 +++
> target/riscv/translate.c | 5 +++++
> 3 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1c8979c1c8..0284ea418f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -545,6 +545,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1)
> FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
> FIELD(TB_FLAGS, PRIV, 22, 2)
> FIELD(TB_FLAGS, AXL, 24, 2)
> +/* If pointer masking should be applied and address sign extended */
> +FIELD(TB_FLAGS, PM_PMM, 26, 2)
> +FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1)
>
> #ifdef TARGET_RISCV32
> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 9640e4c2c5..67bc51e510 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> RISCVCPU *cpu = env_archcpu(env);
> RISCVExtStatus fs, vs;
> uint32_t flags = 0;
> + bool pm_signext = riscv_cpu_virt_mem_enabled(env);
>
> *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
> *cs_base = 0;
> @@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
> flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
> flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
> + flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
> + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
>
> *pflags = flags;
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 6b4b9a671c..2c89d749c0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -103,6 +103,9 @@ typedef struct DisasContext {
> bool vl_eq_vlmax;
> CPUState *cs;
> TCGv zero;
> + /* actual address width */
> + uint8_t addr_width;
> + bool addr_signed;
> /* Use icount trigger for native debug */
> bool itrigger;
> /* FRM is known to contain a valid value. */
> @@ -1176,6 +1179,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
> ctx->cs = cs;
> + ctx->addr_width = 0;
> + ctx->addr_signed = false;
> ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> ctx->zero = tcg_constant_tl(0);
> ctx->virt_inst_excp = false;
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
2024-01-09 10:29 ` [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
@ 2024-01-22 7:04 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2024-01-22 7:04 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Tue, Jan 9, 2024 at 8:32 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 8 ++++++++
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_cfg.h | 3 +++
> target/riscv/csr.c | 11 +++++++++++
> target/riscv/machine.c | 10 +++++++---
> target/riscv/pmp.c | 13 ++++++++++---
> target/riscv/pmp.h | 11 ++++++-----
> 7 files changed, 48 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a43c8fba57..c9bed5c9fc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -101,6 +101,14 @@ typedef enum {
> EXT_STATUS_DIRTY,
> } RISCVExtStatus;
>
> +/* Enum holds PMM field values for Zjpm v0.8 extension */
> +typedef enum {
> + PMM_FIELD_DISABLED = 0,
> + PMM_FIELD_RESERVED = 1,
> + PMM_FIELD_PMLEN7 = 2,
> + PMM_FIELD_PMLEN16 = 3,
> +} RISCVPmPmm;
> +
> #define MMU_USER_IDX 3
>
> #define MAX_RISCV_PMPS (16)
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 1c92458a01..7cf1049bf4 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -715,6 +715,7 @@ typedef enum RISCVException {
> #define MENVCFG_CBIE (3UL << 4)
> #define MENVCFG_CBCFE BIT(6)
> #define MENVCFG_CBZE BIT(7)
> +#define MENVCFG_PMM (3ULL << 32)
> #define MENVCFG_ADUE (1ULL << 61)
> #define MENVCFG_PBMTE (1ULL << 62)
> #define MENVCFG_STCE (1ULL << 63)
> @@ -728,11 +729,13 @@ typedef enum RISCVException {
> #define SENVCFG_CBIE MENVCFG_CBIE
> #define SENVCFG_CBCFE MENVCFG_CBCFE
> #define SENVCFG_CBZE MENVCFG_CBZE
> +#define SENVCFG_PMM MENVCFG_PMM
>
> #define HENVCFG_FIOM MENVCFG_FIOM
> #define HENVCFG_CBIE MENVCFG_CBIE
> #define HENVCFG_CBCFE MENVCFG_CBCFE
> #define HENVCFG_CBZE MENVCFG_CBZE
> +#define HENVCFG_PMM MENVCFG_PMM
> #define HENVCFG_ADUE MENVCFG_ADUE
> #define HENVCFG_PBMTE MENVCFG_PBMTE
> #define HENVCFG_STCE MENVCFG_STCE
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index f4605fb190..201f8af6ae 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -113,6 +113,9 @@ struct RISCVCPUConfig {
> bool ext_ssaia;
> bool ext_sscofpmf;
> bool ext_smepmp;
> + bool ext_ssnpm;
> + bool ext_smnpm;
> + bool ext_smmpm;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ea4e1ac6ef..a67ba30494 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -527,6 +527,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
> if (riscv_cpu_cfg(env)->ext_zkr) {
> return RISCV_EXCP_NONE;
> }
> + if (riscv_cpu_cfg(env)->ext_smmpm) {
> + return RISCV_EXCP_NONE;
> + }
>
> return RISCV_EXCP_ILLEGAL_INST;
> }
> @@ -2030,6 +2033,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> (cfg->ext_sstc ? MENVCFG_STCE : 0) |
> (cfg->ext_svadu ? MENVCFG_ADUE : 0);
> }
> + /* Update PMM field only if the value is valid according to Zjpm v0.8 */
> + if (((val & MENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
> + mask |= MENVCFG_PMM;
> + }
> env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
>
> return RISCV_EXCP_NONE;
> @@ -2074,6 +2081,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
> + /* Update PMM field only if the value is valid according to Zjpm v0.8 */
> + if (((val & SENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
> + mask |= SENVCFG_PMM;
> + }
> RISCVException ret;
>
> ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 71ee8bab19..0ad593ed5a 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -152,15 +152,19 @@ static const VMStateDescription vmstate_vector = {
>
> static bool pointermasking_needed(void *opaque)
> {
> - return false;
> + RISCVCPU *cpu = opaque;
> + return cpu->cfg.ext_ssnpm || cpu->cfg.ext_smnpm || cpu->cfg.ext_smmpm;
> }
>
> static const VMStateDescription vmstate_pointermasking = {
> .name = "cpu/pointer_masking",
> - .version_id = 1,
> - .minimum_version_id = 1,
> + .version_id = 2,
> + .minimum_version_id = 2,
> .needed = pointermasking_needed,
> .fields = (VMStateField[]) {
> + VMSTATE_UINTTL(env.mseccfg, RISCVCPU),
> + VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
> + VMSTATE_UINTTL(env.menvcfg, RISCVCPU),
> VMSTATE_END_OF_LIST()
> }
> };
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 162e88a90a..893ccd58d8 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -576,6 +576,12 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
> void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> {
> int i;
> + uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
> +
> + /* Update PMM field only if the value is valid according to Zjpm v0.8 */
> + if (((val & MSECCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
> + mask |= MSECCFG_PMM;
> + }
>
> trace_mseccfg_csr_write(env->mhartid, val);
>
> @@ -591,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
>
> if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* Sticky bits */
> - val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
> + val |= (env->mseccfg & mask);
> + if ((val ^ env->mseccfg) & mask) {
> tlb_flush(env_cpu(env));
> }
> } else {
> - val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
> + mask |= MSECCFG_RLB;
> + val &= ~(mask);
> }
>
> env->mseccfg = val;
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index 9af8614cd4..b3ca51c26d 100644
> --- a/target/riscv/pmp.h
> +++ b/target/riscv/pmp.h
> @@ -40,11 +40,12 @@ typedef enum {
> } pmp_am_t;
>
> typedef enum {
> - MSECCFG_MML = 1 << 0,
> - MSECCFG_MMWP = 1 << 1,
> - MSECCFG_RLB = 1 << 2,
> - MSECCFG_USEED = 1 << 8,
> - MSECCFG_SSEED = 1 << 9
> + MSECCFG_MML = 1 << 0,
> + MSECCFG_MMWP = 1 << 1,
> + MSECCFG_RLB = 1 << 2,
> + MSECCFG_USEED = 1 << 8,
> + MSECCFG_SSEED = 1 << 9,
> + MSECCFG_PMM = 3UL << 32,
> } mseccfg_field_t;
>
> typedef struct {
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-21 7:13 ` Alexey Baturo
@ 2024-01-23 17:44 ` Deepak Gupta
0 siblings, 0 replies; 19+ messages in thread
From: Deepak Gupta @ 2024-01-23 17:44 UTC (permalink / raw)
To: Alexey Baturo
Cc: Richard Henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Sat, Jan 20, 2024 at 11:14 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Hi,
>
> Having the feature to run binaries with pointer masking on qemu-user is really nice, but I see this patch series as an initial support.
> Obviously there'll be more patches and fixes for pointer masking as soon as arch tests are ready.
> I suggest supporting qemu-user in the next patches, but make sure we do this before claiming 100% support for pointer masking.
> @Deepak Gupta what do you think?
I think that makes sense. Thanks.
>
> Thanks
>
> сб, 20 янв. 2024 г. в 10:37, Richard Henderson <richard.henderson@linaro.org>:
>>
>> On 1/19/24 09:40, Deepak Gupta wrote:
>> > On Thu, Jan 18, 2024 at 12:50 PM Richard Henderson
>> > <richard.henderson@linaro.org> wrote:
>> >> At some point pointer masking will be in hardware, and the kernel will gain support for
>> >> it, and there will likely be a prctl() added for it. At the point the kernel finalizes
>> >> the API, you will be able to enable pointer masking for qemu-user.
>> >
>> > I am sure I am missing some important detail here, BUT...
>> >
>> > How is it different from aarch64 "top byte ignore".
>>
>> It is very similar, yes.
>>
>> > I think commit: 16c8497 enables top byte ignore for user pointers and
>> > by default for qemu-user for aarch64 target.
>>
>> Not quite, no.
>>
>> commit 0e0c030c681730f3ec55ba3b223b608a8f3e8282
>> Author: Richard Henderson <richard.henderson@linaro.org>
>> Date: Fri Feb 12 10:48:51 2021 -0800
>>
>> linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
>>
>> is more relevant.
>>
>> > IIRC, user <--> kernel abi is only needed for pointers that are passed
>> > to the kernel.
>>
>> It is also needed to *enable* pointer masking at all.
>>
>> For aarch64, TBI has been enabled for user-space since the beginning, but that is not true
>> for riscv. Therefore there will be a need for a syscall to opt in and enable pointer masking.
>>
>> > And in the case of qemu-user, we are talking about the host kernel.
>>
>> No, we are not. We are always emulating the guest kernel.
>>
>>
>> r~
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2024-01-23 17:45 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-09 10:29 ` [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2024-01-22 6:53 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
2024-01-22 7:04 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
2024-01-18 17:21 ` Deepak Gupta
2024-01-18 20:50 ` Richard Henderson
2024-01-18 22:40 ` Deepak Gupta
2024-01-20 7:37 ` Richard Henderson
2024-01-21 7:13 ` Alexey Baturo
2024-01-23 17:44 ` Deepak Gupta
2024-01-09 10:29 ` [PATCH v4 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
2024-01-22 7:01 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2024-01-22 7:01 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
2024-01-22 6:54 ` Alistair Francis
2024-01-22 6:52 ` [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alistair Francis
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