From: Alistair Francis <alistair23@gmail.com>
To: Jim Wilson <jimw@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wxy194768@alibaba-inc.com,
Chih-Min Chao <chihmin.chao@sifive.com>,
wenmeng_zhang@c-sky.com, Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v5 0/4] target-riscv: support vector extension part 1
Date: Wed, 26 Feb 2020 14:28:30 -0800 [thread overview]
Message-ID: <CAKmqyKOedrW3HZFfep4ErJ8H86V=KXeBL8LN2Cy_+669a6c9gQ@mail.gmail.com> (raw)
In-Reply-To: <ac290e38-bb39-6551-0758-95d087fa568c@sifive.com>
On Wed, Feb 26, 2020 at 12:09 PM Jim Wilson <jimw@sifive.com> wrote:
>
> On 2/21/20 1:45 AM, LIU Zhiwei wrote:
> > This is the first part of v5 patchset. The changelog of v5 is only coverd
> > the part1.
> >
> > Features:
> > * support specification riscv-v-spec-0.7.1.
>
> I'm still concerned about versioning issues. This implements an
> unofficial draft of the proposed RISC-V vector extension. This draft is
> not compatible with the current draft, and will be even less compatible
> with the final official version of the vector spec.
I wouldn't say this is an unofficial draft. v0.7.1 is an official and
tagged draft spec.
It is a draft spec and there is a new version (v0.8.0) and eventually
there will be a full (not draft release).
>
> The patch adds a version which is good, but there is only one check when
> qemu starts. Probably something like 25% of these patches will be wrong
> for the official vector extension. How are we going to handle this when
> someone submits patches for the official support? It would be better if
The current plan (for all draft extensions) is to support just the
latest draft in QEMU. That is QEMU will have experimental support for
draft extension x at v0.1. When draft extension x is updated to v0.2
we will update the QEMU implementation (when we can) and only support
the v0.2.
We will continue updating and supporting the latest until the final
spec release, in which case we will then maintain the feature
following QEMU's deprecation policy.
While the spec is in a draft state the feature will be considered
experimental (hence the subject to change).
This way we can support and enable users to test on draft extensions,
but not spend all our time supporting draft extensions.
> everything in these patches were conditional on the version number. It
> might also be better if we stopped calling this the 'v' extension and
> maybe used another name like Xrvv071 to make it clear that it is an
> unofficial draft of the proposed vector spec. Or maybe be we can use
> v0p7 but that isn't an officially supported extension name.
>
> If this rvv 0.7.1 implementation is considered a temporary solution,
> maybe we can just remove all of this work when the official rvv spec if
> available? But presumably it is better if we can have both this
That is generally the plan. When the final spec comes out this will be
updated and we will only support that.
> implementation and the official one, which means everything needs to be
> conditional or tied to an Xsomething extension name instead of the V
> extension name.
I agree that would be nice, but that is a lot of extra maintenance to
support a draft spec.
Considering most other projects won't accept draft specs I don't see
the huge appeal to maintain draft specs.
Alistair
>
> Jim
next prev parent reply other threads:[~2020-02-26 22:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-21 9:45 [PATCH v5 0/4] target-riscv: support vector extension part 1 LIU Zhiwei
2020-02-21 9:45 ` [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-02-26 18:03 ` Alistair Francis
2020-02-27 20:32 ` Richard Henderson
2020-02-21 9:45 ` [PATCH v5 2/4] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-02-26 18:05 ` Alistair Francis
2020-02-27 20:33 ` Richard Henderson
2020-02-21 9:45 ` [PATCH v5 3/4] target/riscv: support vector extension csr LIU Zhiwei
2020-02-26 18:42 ` Alistair Francis
2020-02-27 0:41 ` LIU Zhiwei
2020-02-26 20:16 ` Jim Wilson
2020-02-21 9:45 ` [PATCH v5 4/4] target/riscv: add vector configure instruction LIU Zhiwei
2020-02-26 19:20 ` Alistair Francis
2020-02-27 1:41 ` LIU Zhiwei
2020-02-27 21:48 ` Alistair Francis
2020-02-26 20:20 ` Jim Wilson
2020-02-26 20:09 ` [PATCH v5 0/4] target-riscv: support vector extension part 1 Jim Wilson
2020-02-26 22:28 ` Alistair Francis [this message]
2020-02-26 23:39 ` Jim Wilson
2020-02-26 23:46 ` Alistair Francis
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