From: Jim Wilson <jimw@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
richard.henderson@linaro.org, alistair23@gmail.com,
chihmin.chao@sifive.com, palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [PATCH v5 4/4] target/riscv: add vector configure instruction
Date: Wed, 26 Feb 2020 12:20:28 -0800 [thread overview]
Message-ID: <f2ce2ebc-0e79-d65a-86b3-5f705b541fc2@sifive.com> (raw)
In-Reply-To: <20200221094531.61894-5-zhiwei_liu@c-sky.com>
On 2/21/20 1:45 AM, LIU Zhiwei wrote:
> + /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> + if (a->rs1 == 0) {
> + /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> + s1 = tcg_const_tl(RV_VLEN_MAX);
This is wrong for the current draft of the vector spec. x0 now means
don't change VL. So this needs to be version specific.
Jim
next prev parent reply other threads:[~2020-02-26 20:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-21 9:45 [PATCH v5 0/4] target-riscv: support vector extension part 1 LIU Zhiwei
2020-02-21 9:45 ` [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-02-26 18:03 ` Alistair Francis
2020-02-27 20:32 ` Richard Henderson
2020-02-21 9:45 ` [PATCH v5 2/4] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-02-26 18:05 ` Alistair Francis
2020-02-27 20:33 ` Richard Henderson
2020-02-21 9:45 ` [PATCH v5 3/4] target/riscv: support vector extension csr LIU Zhiwei
2020-02-26 18:42 ` Alistair Francis
2020-02-27 0:41 ` LIU Zhiwei
2020-02-26 20:16 ` Jim Wilson
2020-02-21 9:45 ` [PATCH v5 4/4] target/riscv: add vector configure instruction LIU Zhiwei
2020-02-26 19:20 ` Alistair Francis
2020-02-27 1:41 ` LIU Zhiwei
2020-02-27 21:48 ` Alistair Francis
2020-02-26 20:20 ` Jim Wilson [this message]
2020-02-26 20:09 ` [PATCH v5 0/4] target-riscv: support vector extension part 1 Jim Wilson
2020-02-26 22:28 ` Alistair Francis
2020-02-26 23:39 ` Jim Wilson
2020-02-26 23:46 ` Alistair Francis
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