* [PATCH v2 0/2] riscv: add rv32i,rv32e and rv64e CPUs
@ 2024-01-08 16:19 Daniel Henrique Barboza
2024-01-08 16:19 ` [PATCH v2 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init() Daniel Henrique Barboza
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-08 16:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza
Hi,
This is the second version of a buried patch series:
"[PATCH for-9.0 0/6] riscv: rv32i,rv32e,rv64i and rv64e CPUs"
This version shrank to 2 patches since most of the prep work was already
done by the RVA22 profile implementation, which is now queued in
riscv-to-apply.next.
The motivation is the same as in v1 - give users a cleaner way of using
a customized CPU, from scratch, without the need to disable default
extensions.
Patches based on Alistair's riscv-to-apply.next.
Changes from v1:
- patches 1 to 4 from v1: dropped
- patches 5 and 6 from v1: merged into patch 2
- patch 1 (new):
- add a new common cpu_init() for all bare CPUs
- v1 link: https://lore.kernel.org/qemu-riscv/20231113213904.185320-1-dbarboza@ventanamicro.com/
Daniel Henrique Barboza (2):
target/riscv/cpu.c: add riscv_bare_cpu_init()
target/riscv: add rv32i, rv32e and rv64e CPUs
target/riscv/cpu-qom.h | 3 ++
target/riscv/cpu.c | 64 ++++++++++++++++++++++++++++++++----------
2 files changed, 52 insertions(+), 15 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init()
2024-01-08 16:19 [PATCH v2 0/2] riscv: add rv32i,rv32e and rv64e CPUs Daniel Henrique Barboza
@ 2024-01-08 16:19 ` Daniel Henrique Barboza
2024-01-22 3:31 ` Alistair Francis
2024-01-08 16:19 ` [PATCH v2 2/2] target/riscv: add rv32i, rv32e and rv64e CPUs Daniel Henrique Barboza
2024-01-22 3:38 ` [PATCH v2 0/2] riscv: add rv32i,rv32e " Alistair Francis
2 siblings, 1 reply; 6+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-08 16:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza
Next patch will add more bare CPUs. Their cpu_init() functions would be
glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a
riscv_cpu_set_misa() call.
Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this
code repetition. While we're at it, add a better explanation on why
we're disabling the timing extensions for bare CPUs.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++----------------
1 file changed, 29 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b32681f7f3..1202ec3e57 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -575,22 +575,6 @@ static void rv64i_bare_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa(env, MXL_RV64, RVI);
-
- /* Remove the defaults from the parent class */
- RISCV_CPU(obj)->cfg.ext_zicntr = false;
- RISCV_CPU(obj)->cfg.ext_zihpm = false;
-
- /* Set to QEMU's first supported priv version */
- env->priv_ver = PRIV_VERSION_1_10_0;
-
- /*
- * Support all available satp_mode settings. The default
- * value will be set to MBARE if the user doesn't set
- * satp_mode manually (see set_satp_mode_default()).
- */
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
-#endif
}
#else
static void rv32_base_cpu_init(Object *obj)
@@ -1266,6 +1250,34 @@ static void riscv_cpu_init(Object *obj)
RISCV_CPU(obj)->cfg.ext_zihpm = true;
}
+static void riscv_bare_cpu_init(Object *obj)
+{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ /*
+ * Bare CPUs do not inherit the timer and performance
+ * counters from the parent class (see riscv_cpu_init()
+ * for info on why the parent enables them).
+ *
+ * Users have to explicitly enable these counters for
+ * bare CPUs.
+ */
+ cpu->cfg.ext_zicntr = false;
+ cpu->cfg.ext_zihpm = false;
+
+ /* Set to QEMU's first supported priv version */
+ cpu->env.priv_ver = PRIV_VERSION_1_10_0;
+
+ /*
+ * Support all available satp_mode settings. The default
+ * value will be set to MBARE if the user doesn't set
+ * satp_mode manually (see set_satp_mode_default()).
+ */
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV64);
+#endif
+}
+
typedef struct misa_ext_info {
const char *name;
const char *description;
@@ -1925,6 +1937,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_BARE_CPU,
.parent = TYPE_RISCV_CPU,
+ .instance_init = riscv_bare_cpu_init,
.abstract = true,
},
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] target/riscv: add rv32i, rv32e and rv64e CPUs
2024-01-08 16:19 [PATCH v2 0/2] riscv: add rv32i,rv32e and rv64e CPUs Daniel Henrique Barboza
2024-01-08 16:19 ` [PATCH v2 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init() Daniel Henrique Barboza
@ 2024-01-08 16:19 ` Daniel Henrique Barboza
2024-01-22 3:32 ` Alistair Francis
2024-01-22 3:38 ` [PATCH v2 0/2] riscv: add rv32i,rv32e " Alistair Francis
2 siblings, 1 reply; 6+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-08 16:19 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza
A bare bones 32 bit RVI CPU, rv32i, will make users lives easier when a
full customized 32 bit CPU is desired, and users won't need to disable
defaults by hand as they would with the rv32 CPU. [1] has an example of
a situation that would be avoided with rv32i.
In fact, add bare bones CPUs for RVE as well. Trying to use RVE in QEMU
requires one to disable every single default extension, including RVI,
and then add the desirable extension set. Adding rv32e/rv64e makes it
more pleasant to use embedded CPUs in QEMU.
[1] https://lore.kernel.org/qemu-riscv/258be47f-97be-4308-bed5-dc34ef7ff954@Spark/
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu-qom.h | 3 +++
target/riscv/cpu.c | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 9219c2fcc3..3670cfe6d9 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -34,7 +34,10 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
+#define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i")
+#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e")
#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
+#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e")
#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1202ec3e57..b9f10b773b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -576,6 +576,12 @@ static void rv64i_bare_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa(env, MXL_RV64, RVI);
}
+
+static void rv64e_bare_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ riscv_cpu_set_misa(env, MXL_RV64, RVE);
+}
#else
static void rv32_base_cpu_init(Object *obj)
{
@@ -657,6 +663,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
cpu->cfg.ext_zicsr = true;
cpu->cfg.pmp = true;
}
+
+static void rv32i_bare_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ riscv_cpu_set_misa(env, MXL_RV32, RVI);
+}
+
+static void rv32e_bare_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ riscv_cpu_set_misa(env, MXL_RV32, RVE);
+}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -1948,6 +1966,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
+ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, rv32i_bare_cpu_init),
+ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, rv32e_bare_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
@@ -1957,6 +1977,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
+ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, rv64e_bare_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init()
2024-01-08 16:19 ` [PATCH v2 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init() Daniel Henrique Barboza
@ 2024-01-22 3:31 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2024-01-22 3:31 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer
On Tue, Jan 9, 2024 at 3:32 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Next patch will add more bare CPUs. Their cpu_init() functions would be
> glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a
> riscv_cpu_set_misa() call.
>
> Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this
> code repetition. While we're at it, add a better explanation on why
> we're disabling the timing extensions for bare CPUs.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++----------------
> 1 file changed, 29 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b32681f7f3..1202ec3e57 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -575,22 +575,6 @@ static void rv64i_bare_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> riscv_cpu_set_misa(env, MXL_RV64, RVI);
> -
> - /* Remove the defaults from the parent class */
> - RISCV_CPU(obj)->cfg.ext_zicntr = false;
> - RISCV_CPU(obj)->cfg.ext_zihpm = false;
> -
> - /* Set to QEMU's first supported priv version */
> - env->priv_ver = PRIV_VERSION_1_10_0;
> -
> - /*
> - * Support all available satp_mode settings. The default
> - * value will be set to MBARE if the user doesn't set
> - * satp_mode manually (see set_satp_mode_default()).
> - */
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
> -#endif
> }
> #else
> static void rv32_base_cpu_init(Object *obj)
> @@ -1266,6 +1250,34 @@ static void riscv_cpu_init(Object *obj)
> RISCV_CPU(obj)->cfg.ext_zihpm = true;
> }
>
> +static void riscv_bare_cpu_init(Object *obj)
> +{
> + RISCVCPU *cpu = RISCV_CPU(obj);
> +
> + /*
> + * Bare CPUs do not inherit the timer and performance
> + * counters from the parent class (see riscv_cpu_init()
> + * for info on why the parent enables them).
> + *
> + * Users have to explicitly enable these counters for
> + * bare CPUs.
> + */
> + cpu->cfg.ext_zicntr = false;
> + cpu->cfg.ext_zihpm = false;
> +
> + /* Set to QEMU's first supported priv version */
> + cpu->env.priv_ver = PRIV_VERSION_1_10_0;
> +
> + /*
> + * Support all available satp_mode settings. The default
> + * value will be set to MBARE if the user doesn't set
> + * satp_mode manually (see set_satp_mode_default()).
> + */
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_SV64);
> +#endif
> +}
> +
> typedef struct misa_ext_info {
> const char *name;
> const char *description;
> @@ -1925,6 +1937,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> {
> .name = TYPE_RISCV_BARE_CPU,
> .parent = TYPE_RISCV_CPU,
> + .instance_init = riscv_bare_cpu_init,
> .abstract = true,
> },
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: add rv32i, rv32e and rv64e CPUs
2024-01-08 16:19 ` [PATCH v2 2/2] target/riscv: add rv32i, rv32e and rv64e CPUs Daniel Henrique Barboza
@ 2024-01-22 3:32 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2024-01-22 3:32 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer
On Tue, Jan 9, 2024 at 2:19 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> A bare bones 32 bit RVI CPU, rv32i, will make users lives easier when a
> full customized 32 bit CPU is desired, and users won't need to disable
> defaults by hand as they would with the rv32 CPU. [1] has an example of
> a situation that would be avoided with rv32i.
>
> In fact, add bare bones CPUs for RVE as well. Trying to use RVE in QEMU
> requires one to disable every single default extension, including RVI,
> and then add the desirable extension set. Adding rv32e/rv64e makes it
> more pleasant to use embedded CPUs in QEMU.
>
> [1] https://lore.kernel.org/qemu-riscv/258be47f-97be-4308-bed5-dc34ef7ff954@Spark/
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 3 +++
> target/riscv/cpu.c | 21 +++++++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 9219c2fcc3..3670cfe6d9 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -34,7 +34,10 @@
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> +#define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i")
> +#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e")
> #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
> +#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e")
> #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
> #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1202ec3e57..b9f10b773b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -576,6 +576,12 @@ static void rv64i_bare_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> riscv_cpu_set_misa(env, MXL_RV64, RVI);
> }
> +
> +static void rv64e_bare_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + riscv_cpu_set_misa(env, MXL_RV64, RVE);
> +}
> #else
> static void rv32_base_cpu_init(Object *obj)
> {
> @@ -657,6 +663,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> }
> +
> +static void rv32i_bare_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + riscv_cpu_set_misa(env, MXL_RV32, RVI);
> +}
> +
> +static void rv32e_bare_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + riscv_cpu_set_misa(env, MXL_RV32, RVE);
> +}
> #endif
>
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> @@ -1948,6 +1966,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
> + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, rv32i_bare_cpu_init),
> + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, rv32e_bare_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> @@ -1957,6 +1977,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
> + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, rv64e_bare_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
> #endif
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/2] riscv: add rv32i,rv32e and rv64e CPUs
2024-01-08 16:19 [PATCH v2 0/2] riscv: add rv32i,rv32e and rv64e CPUs Daniel Henrique Barboza
2024-01-08 16:19 ` [PATCH v2 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init() Daniel Henrique Barboza
2024-01-08 16:19 ` [PATCH v2 2/2] target/riscv: add rv32i, rv32e and rv64e CPUs Daniel Henrique Barboza
@ 2024-01-22 3:38 ` Alistair Francis
2 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2024-01-22 3:38 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer
On Tue, Jan 9, 2024 at 3:40 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This is the second version of a buried patch series:
>
> "[PATCH for-9.0 0/6] riscv: rv32i,rv32e,rv64i and rv64e CPUs"
>
> This version shrank to 2 patches since most of the prep work was already
> done by the RVA22 profile implementation, which is now queued in
> riscv-to-apply.next.
>
> The motivation is the same as in v1 - give users a cleaner way of using
> a customized CPU, from scratch, without the need to disable default
> extensions.
>
> Patches based on Alistair's riscv-to-apply.next.
>
> Changes from v1:
> - patches 1 to 4 from v1: dropped
> - patches 5 and 6 from v1: merged into patch 2
> - patch 1 (new):
> - add a new common cpu_init() for all bare CPUs
> - v1 link: https://lore.kernel.org/qemu-riscv/20231113213904.185320-1-dbarboza@ventanamicro.com/
>
>
> Daniel Henrique Barboza (2):
> target/riscv/cpu.c: add riscv_bare_cpu_init()
> target/riscv: add rv32i, rv32e and rv64e CPUs
Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next ?
Alistai
>
> target/riscv/cpu-qom.h | 3 ++
> target/riscv/cpu.c | 64 ++++++++++++++++++++++++++++++++----------
> 2 files changed, 52 insertions(+), 15 deletions(-)
>
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-01-22 3:40 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-08 16:19 [PATCH v2 0/2] riscv: add rv32i,rv32e and rv64e CPUs Daniel Henrique Barboza
2024-01-08 16:19 ` [PATCH v2 1/2] target/riscv/cpu.c: add riscv_bare_cpu_init() Daniel Henrique Barboza
2024-01-22 3:31 ` Alistair Francis
2024-01-08 16:19 ` [PATCH v2 2/2] target/riscv: add rv32i, rv32e and rv64e CPUs Daniel Henrique Barboza
2024-01-22 3:32 ` Alistair Francis
2024-01-22 3:38 ` [PATCH v2 0/2] riscv: add rv32i,rv32e " Alistair Francis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).