* [PATCH] target/riscv: Use background registers also for MSTATUS_MPV
@ 2021-03-11 10:30 Georg Kotheimer
2021-03-16 20:22 ` Alistair Francis
0 siblings, 1 reply; 2+ messages in thread
From: Georg Kotheimer @ 2021-03-11 10:30 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, Georg Kotheimer
The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2f43939fb6..d5d84d0d1c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -321,7 +321,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
use_background = true;
}
--
2.30.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/riscv: Use background registers also for MSTATUS_MPV
2021-03-11 10:30 [PATCH] target/riscv: Use background registers also for MSTATUS_MPV Georg Kotheimer
@ 2021-03-16 20:22 ` Alistair Francis
0 siblings, 0 replies; 2+ messages in thread
From: Alistair Francis @ 2021-03-16 20:22 UTC (permalink / raw)
To: Georg Kotheimer
Cc: Alistair Francis, open list:RISC-V, qemu-devel@nongnu.org Developers
On Thu, Mar 11, 2021 at 5:32 AM Georg Kotheimer
<georg.kotheimer@kernkonzept.com> wrote:
>
> The current condition for the use of background registers only
> considers the hypervisor load and store instructions,
> but not accesses from M mode via MSTATUS_MPRV+MPV.
>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 2f43939fb6..d5d84d0d1c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -321,7 +321,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> * was called. Background registers will be used if the guest has
> * forced a two stage translation to be on (in HS or M mode).
> */
> - if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
> + if (!riscv_cpu_virt_enabled(env) && two_stage) {
> use_background = true;
> }
>
> --
> 2.30.1
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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