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* [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
@ 2019-07-01 15:46 jonathan
  2019-07-01 20:54 ` Alistair Francis
  0 siblings, 1 reply; 8+ messages in thread
From: jonathan @ 2019-07-01 15:46 UTC (permalink / raw)
  To: qemu-riscv
  Cc: Sagar Karandikar, Jonathan Behrens, Palmer Dabbelt,
	open list:All patches CC here, Alistair Francis,
	Bastian Koppelmann

From: Jonathan Behrens <jonathan@fintelia.io>

QEMU currently always triggers an illegal instruction exception when
code attempts to read the time CSR. This is valid behavor, but only if
the TM bit in mcounteren is hardwired to zero. This change also
corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit
and 64-bit targets.

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
---
 target/riscv/cpu.h      | 4 ++--
 target/riscv/cpu_bits.h | 5 +++++
 target/riscv/csr.c      | 2 +-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0adb307f32..2d0cbe9c78 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -151,8 +151,8 @@ struct CPURISCVState {
     target_ulong mcause;
     target_ulong mtval;  /* since: priv-1.10.0 */
 
-    target_ulong scounteren;
-    target_ulong mcounteren;
+    uint32_t scounteren;
+    uint32_t mcounteren;
 
     target_ulong sscratch;
     target_ulong mscratch;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 11f971ad5d..0ea1e1caf5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -532,4 +532,9 @@
 #define SIP_STIP                           MIP_STIP
 #define SIP_SEIP                           MIP_SEIP
 
+/* mcounteren CSR bits */
+#define MCOUNTEREN_CY                      0x1
+#define MCOUNTEREN_TM                      0x2
+#define MCOUNTEREN_IR                      0x4
+
 #endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0d4586760..8425a6d2bd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -473,7 +473,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
     if (env->priv_ver < PRIV_VERSION_1_10_0) {
         return -1;
     }
-    env->mcounteren = val;
+    env->mcounteren = val & ~MCOUNTEREN_TM;
     return 0;
 }
 
-- 
2.22.0


^ permalink raw reply related	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-01-21 22:29 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-01 15:46 [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren jonathan
2019-07-01 20:54 ` Alistair Francis
2019-07-02  1:26   ` Bin Meng
2019-07-03 18:02     ` Jonathan Behrens
2019-08-15  3:19       ` Jonathan Behrens
2019-08-21 17:37         ` Palmer Dabbelt
2020-01-21 13:05           ` Jonathan Behrens
2020-01-21 22:26             ` Alistair Francis

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