From: Sylvain Pelissier <sylvain.pelissier@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] gdb: riscv: Add target description
Date: Wed, 30 Dec 2020 08:42:46 +0100 [thread overview]
Message-ID: <CAOkUe-DyJLEiHK4hmxEtfVwTV_3rb-RXAgRS2Ojtk5krctVBGA@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmWcNqNMzipVvYMgVsJH7dTwZv8qMYFdpzvCSNRGVH0NsA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1775 bytes --]
Target description is not currently implemented in RISC-V architecture.
Thus GDB won't set it properly when attached. The patch implements the
target description response.
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 254cd83f8b..ed4971978b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static gchar *riscv_gdb_arch_name(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (riscv_cpu_is_32bit(env)) {
+ return g_strdup("riscv:rv32");
+ } else {
+ return g_strdup("riscv:rv64");
+ }
+}
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
+ cc->gdb_arch_name = riscv_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
--
2.25.1
On Wed, 30 Dec 2020 at 01:26, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Sylvain,
>
> On Wed, Dec 30, 2020 at 12:37 AM Sylvain Pelissier
> <sylvain.pelissier@gmail.com> wrote:
> >
> > Thank you for your remark here is the new patch:
>
> This should not be put into the commit message.
>
> Previous commit message is missing.
>
> >
> > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
> > ---
> > target/riscv/cpu.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
>
> Regards,
> Bin
>
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next prev parent reply other threads:[~2020-12-30 7:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-23 16:28 [PATCH] gdb: riscv: Add target description Sylvain Pelissier
2020-12-29 4:10 ` Bin Meng
2020-12-29 16:36 ` Sylvain Pelissier
2020-12-30 0:26 ` Bin Meng
2020-12-30 7:42 ` Sylvain Pelissier [this message]
2020-12-30 7:57 ` Bin Meng
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