From: Sylvain Pelissier <sylvain.pelissier@gmail.com>
To: qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
qemu-riscv@nongnu.org,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [PATCH] gdb: riscv: Add target description
Date: Wed, 23 Dec 2020 17:28:13 +0100 [thread overview]
Message-ID: <CAOkUe-DTG1yU-z4SF-+nBeEJUWdx5gctLMSNp8f1+_7FpWG4aA@mail.gmail.com> (raw)
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Target description is not currently implemented in RISC-V architecture.
Thus GDB won't set it properly when attached. The patch implements the
target description response.
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
---
target/riscv/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 254cd83f8b..489d66038c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,6 +556,15 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static gchar *riscv_gdb_arch_name(CPUState *cs)
+{
+ #ifdef TARGET_RISCV64
+ return g_strdup("riscv:rv64");
+ #else
+ return g_strdup("riscv:rv32");
+ #endif
+}
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -591,6 +600,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
+ cc->gdb_arch_name = riscv_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
--
2.25.1
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next reply other threads:[~2020-12-23 17:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-23 16:28 Sylvain Pelissier [this message]
2020-12-29 4:10 ` [PATCH] gdb: riscv: Add target description Bin Meng
2020-12-29 16:36 ` Sylvain Pelissier
2020-12-30 0:26 ` Bin Meng
2020-12-30 7:42 ` Sylvain Pelissier
2020-12-30 7:57 ` Bin Meng
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