* [PATCH v5 1/1] accel/tcg: Fix computing of is_write for MIPS
@ 2020-10-02 8:14 Kele Huang
2020-10-05 17:27 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Kele Huang @ 2020-10-02 8:14 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Xu Zou, Riku Voipio, Richard Henderson,
Kele Huang, Jiaxun Yang, Aleksandar Markovic, Paolo Bonzini
Detect all MIPS store instructions in cpu_signal_handler for all available
MIPS versions, and set is_write if encountering such store instructions.
This fixed the error while dealing with self-modified code for MIPS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Signed-off-by: Xu Zou <iwatchnima@gmail.com>
---
accel/tcg/user-exec.c | 39 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 5c96819ded..88eccf7900 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -702,6 +702,10 @@ int cpu_signal_handler(int host_signum, void *pinfo,
#elif defined(__mips__)
+#if defined(__misp16) || defined(__mips_micromips)
+#error "Unsupported encoding"
+#endif
+
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)
{
@@ -709,9 +713,42 @@ int cpu_signal_handler(int host_signum, void *pinfo,
ucontext_t *uc = puc;
greg_t pc = uc->uc_mcontext.pc;
int is_write;
+ uint32_t insn;
- /* XXX: compute is_write */
+ /* Detect all store instructions at program counter. */
is_write = 0;
+ insn = *(uint32_t *)pc;
+ switch((insn >> 26) & 077) {
+ case 050: /* SB */
+ case 051: /* SH */
+ case 052: /* SWL */
+ case 053: /* SW */
+ case 054: /* SDL */
+ case 055: /* SDR */
+ case 056: /* SWR */
+ case 070: /* SC */
+ case 071: /* SWC1 */
+ case 074: /* SCD */
+ case 075: /* SDC1 */
+ case 077: /* SD */
+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
+ case 072: /* SWC2 */
+ case 076: /* SDC2 */
+#endif
+ is_write = 1;
+ break;
+ case 023: /* COP1X */
+ /* Required in all versions of MIPS64 since
+ MIPS64r1 and subsequent versions of MIPS32r2. */
+ switch (insn & 077) {
+ case 010: /* SWXC1 */
+ case 011: /* SDXC1 */
+ case 015: /* SUXC1 */
+ is_write = 1;
+ }
+ break;
+ }
+
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v5 1/1] accel/tcg: Fix computing of is_write for MIPS
2020-10-02 8:14 [PATCH v5 1/1] accel/tcg: Fix computing of is_write for MIPS Kele Huang
@ 2020-10-05 17:27 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2020-10-05 17:27 UTC (permalink / raw)
To: Kele Huang, qemu-devel
Cc: Aleksandar Rikalo, Xu Zou, Riku Voipio, Jiaxun Yang,
Aleksandar Markovic, Paolo Bonzini
On 10/2/20 3:14 AM, Kele Huang wrote:
> Detect all MIPS store instructions in cpu_signal_handler for all available
> MIPS versions, and set is_write if encountering such store instructions.
>
> This fixed the error while dealing with self-modified code for MIPS.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Kele Huang <kele.hwang@gmail.com>
> Signed-off-by: Xu Zou <iwatchnima@gmail.com>
> ---
> accel/tcg/user-exec.c | 39 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 38 insertions(+), 1 deletion(-)
Queued to tcg-next.
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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