From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
Date: Tue, 28 Mar 2023 10:20:37 +0800 [thread overview]
Message-ID: <c0abfb39-56a7-a184-f134-bcb075908f57@linux.alibaba.com> (raw)
In-Reply-To: <20230327100027.61160-2-liweiwei@iscas.ac.cn>
On 2023/3/27 18:00, Weiwei Li wrote:
> Since pointer mask works on effective address, and the xl works on the
> generation of effective address, so xl related calculation should be done
> before pointer mask.
Incorrect. It has been done.
When updating the pm_mask, we have already considered the env->xl.
You can see it in riscv_cpu_update_mask
if (env->xl == MXL_RV32) {
env->cur_pmmask = mask & UINT32_MAX;
env->cur_pmbase = base & UINT32_MAX;
} else {
env->cur_pmmask = mask;
env->cur_pmbase = base;
}
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/translate.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 0ee8ee147d..bf0e2d318e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -568,11 +568,15 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_addi_tl(addr, src1, imm);
> +
> + if (get_xl(ctx) == MXL_RV32) {
> + tcg_gen_ext32u_tl(addr, addr);
> + }
> +
> if (ctx->pm_mask_enabled) {
> tcg_gen_andc_tl(addr, addr, pm_mask);
> - } else if (get_xl(ctx) == MXL_RV32) {
> - tcg_gen_ext32u_tl(addr, addr);
> }
The else is processing when only xl works, and the pm_mask doesn't work.
Zhiwei
> +
> if (ctx->pm_base_enabled) {
> tcg_gen_or_tl(addr, addr, pm_base);
> }
> @@ -586,11 +590,15 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_add_tl(addr, src1, offs);
> +
> + if (get_xl(ctx) == MXL_RV32) {
> + tcg_gen_ext32u_tl(addr, addr);
> + }
> +
> if (ctx->pm_mask_enabled) {
> tcg_gen_andc_tl(addr, addr, pm_mask);
> - } else if (get_xl(ctx) == MXL_RV32) {
> - tcg_gen_ext32u_tl(addr, addr);
> }
> +
> if (ctx->pm_base_enabled) {
> tcg_gen_or_tl(addr, addr, pm_base);
> }
next prev parent reply other threads:[~2023-03-28 2:21 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 10:00 [PATCH 0/5] target/riscv: Fix pointer mask related support Weiwei Li
2023-03-27 10:00 ` [PATCH 1/5] target/riscv: Fix effective address for pointer mask Weiwei Li
2023-03-27 13:19 ` Daniel Henrique Barboza
2023-03-28 2:20 ` LIU Zhiwei [this message]
2023-03-28 2:48 ` liweiwei
2023-03-28 3:18 ` Richard Henderson
2023-03-28 3:24 ` LIU Zhiwei
2023-03-28 3:33 ` liweiwei
2023-03-28 7:25 ` LIU Zhiwei
2023-03-28 10:26 ` liweiwei
2023-03-27 10:00 ` [PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32 Weiwei Li
2023-03-27 13:20 ` Daniel Henrique Barboza
2023-03-28 2:14 ` LIU Zhiwei
2023-03-28 3:07 ` liweiwei
2023-03-27 10:00 ` [PATCH 3/5] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-03-27 13:20 ` Daniel Henrique Barboza
2023-03-28 2:21 ` LIU Zhiwei
2023-03-27 10:00 ` [PATCH 4/5] target/riscv: take xl into consideration " Weiwei Li
2023-03-27 13:21 ` Daniel Henrique Barboza
2023-03-28 2:21 ` LIU Zhiwei
2023-03-27 10:00 ` [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch Weiwei Li
2023-03-27 13:28 ` Daniel Henrique Barboza
2023-03-27 15:13 ` Daniel Henrique Barboza
2023-03-27 18:04 ` Richard Henderson
2023-03-28 1:55 ` liweiwei
2023-03-28 2:31 ` LIU Zhiwei
2023-03-28 3:14 ` liweiwei
2023-03-28 3:31 ` Richard Henderson
2023-03-28 4:09 ` liweiwei
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