* [PATCH] hw/adc/stm32f2xx_adc: Correct memory region size and access size
@ 2020-05-25 11:08 Philippe Mathieu-Daudé
2020-05-25 11:09 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 2+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-25 11:08 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-trivial, Peter Maydell, qemu-arm,
Philippe Mathieu-Daudé,
Alistair Francis
The ADC region size is 256B, split as:
- [0x00 - 0x4f] defined
- [0x50 - 0xff] reserved
All registers are 32-bit (thus when the datasheet mentions the
last defined register is 0x4c, it means its address range is
0x4c .. 0x4f.
This model implementation is also 32-bit. Set MemoryRegionOps
'impl' fields.
See:
'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/adc/stm32f2xx_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
index 4f9d485ecf..5d834a98f6 100644
--- a/hw/adc/stm32f2xx_adc.c
+++ b/hw/adc/stm32f2xx_adc.c
@@ -278,7 +278,7 @@ static void stm32f2xx_adc_init(Object *obj)
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
- TYPE_STM32F2XX_ADC, 0xFF);
+ TYPE_STM32F2XX_ADC, 0x100);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}
--
2.21.3
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] hw/adc/stm32f2xx_adc: Correct memory region size and access size
2020-05-25 11:08 [PATCH] hw/adc/stm32f2xx_adc: Correct memory region size and access size Philippe Mathieu-Daudé
@ 2020-05-25 11:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 2+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-25 11:09 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-trivial, Peter Maydell, qemu-arm, Alistair Francis
On 5/25/20 1:08 PM, Philippe Mathieu-Daudé wrote:
> The ADC region size is 256B, split as:
> - [0x00 - 0x4f] defined
> - [0x50 - 0xff] reserved
>
> All registers are 32-bit (thus when the datasheet mentions the
> last defined register is 0x4c, it means its address range is
> 0x4c .. 0x4f.
>
> This model implementation is also 32-bit. Set MemoryRegionOps
> 'impl' fields.
>
> See:
> 'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/adc/stm32f2xx_adc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
> index 4f9d485ecf..5d834a98f6 100644
> --- a/hw/adc/stm32f2xx_adc.c
> +++ b/hw/adc/stm32f2xx_adc.c
> @@ -278,7 +278,7 @@ static void stm32f2xx_adc_init(Object *obj)
> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
>
> memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
> - TYPE_STM32F2XX_ADC, 0xFF);
> + TYPE_STM32F2XX_ADC, 0x100);
> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
> }
>
Please ignore this patch, it is incomplete.
^ permalink raw reply [flat|nested] 2+ messages in thread
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