[PATCH 0/5] MIPS Bootloader helper

[PATCH 0/5] MIPS Bootloader helper

[Jiaxun Yang]

Hi all,

I'm back! Now I'm also helping CIP United, the present owner of MIPS
in China, take care of their open-souce infrastructures.

Btw: I'd like to add kernel boot tests for boston and incoming loongson-virt.
Where should I place kernel binaries?

Thanks.

Jiaxun Yang (5):
  hw/mips: Add a bootloader helper
  hw/mips/malta: Make use of bootloader helper
  hw/mips/fuloong2e: Make use of bootloader helper
  hw/mips/addr: Add translation helpers for KSEG1
  hw/mips/boston: Make use of bootloader helper

 hw/mips/addr.c            |  11 +++
 hw/mips/bootloader.c      | 150 ++++++++++++++++++++++++++++++++++++++
 hw/mips/boston.c          |  60 ++++-----------
 hw/mips/fuloong2e.c       |  35 ++-------
 hw/mips/malta.c           | 108 +++++++--------------------
 hw/mips/meson.build       |   2 +-
 include/hw/mips/cpudevs.h |  10 +++
 7 files changed, 216 insertions(+), 160 deletions(-)
 create mode 100644 hw/mips/bootloader.c

-- 
2.29.2

[PATCH 1/5] hw/mips: Add a bootloader helper

[Jiaxun Yang]

Add a bootloader helper to generate simple bootloaders for kernel.
It can help us reduce inline hex hack and also keep MIPS release 6
compatibility easier.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/mips/bootloader.c      | 150 ++++++++++++++++++++++++++++++++++++++
 hw/mips/meson.build       |   2 +-
 include/hw/mips/cpudevs.h |   8 ++
 3 files changed, 159 insertions(+), 1 deletion(-)
 create mode 100644 hw/mips/bootloader.c

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
new file mode 100644
index 0000000000..3210c26bb7
--- /dev/null
+++ b/hw/mips/bootloader.c
@@ -0,0 +1,150 @@
+/*
+ * Utility for QEMU MIPS to generate it's simple bootloader
+ *
+ * Instructions used here are carefully selected to keep compatibility with
+ * MIPS Release 6.
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "cpu.h"
+#include "hw/mips/cpudevs.h"
+
+/* Base types */
+static void bl_gen_nop(uint32_t **p)
+{
+    stl_p(*p, 0);
+    *p = *p + 1;
+}
+
+static void bl_gen_r_type(uint32_t **p, uint8_t opcode, uint8_t rs, uint8_t rt,
+                            uint8_t rd, uint8_t shift, uint8_t funct)
+{
+    uint32_t insn = 0;
+
+    insn = deposit32(insn, 26, 6, opcode);
+    insn = deposit32(insn, 21, 5, rs);
+    insn = deposit32(insn, 16, 5, rt);
+    insn = deposit32(insn, 11, 5, rd);
+    insn = deposit32(insn, 6, 5, shift);
+    insn = deposit32(insn, 0, 6, funct);
+
+    stl_p(*p, insn);
+    *p = *p + 1;
+}
+
+static void bl_gen_i_type(uint32_t **p, uint8_t opcode, uint8_t rs, uint8_t rt,
+                            uint16_t imm)
+{
+    uint32_t insn = 0;
+
+    insn = deposit32(insn, 26, 6, opcode);
+    insn = deposit32(insn, 21, 5, rs);
+    insn = deposit32(insn, 16, 5, rt);
+    insn = deposit32(insn, 0, 16, imm);
+
+    stl_p(*p, insn);
+    *p = *p + 1;
+}
+
+/* Single instructions */
+static void bl_gen_dsll(uint32_t **p, uint8_t rd, uint8_t rt, uint8_t sa)
+{
+    /* R6: OK, 32: NO */
+    bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
+}
+
+static void bl_gen_daddiu(uint32_t **p, uint8_t rt, uint8_t rs, uint16_t imm)
+{
+    /* R6: OK, 32: NO */
+    bl_gen_i_type(p, 0x19, rs, rt, imm);
+}
+
+static void bl_gen_jalr(uint32_t **p, uint8_t rs)
+{
+    /* R6: OK, 32: OK */
+    bl_gen_r_type(p, 0, rs, 0, 31, 0, 0x9);
+}
+
+static void bl_gen_lui(uint32_t **p, uint8_t rt, uint16_t imm)
+{
+    /* R6: It's a alias of AUI with RS = 0, 32: OK */
+    bl_gen_i_type(p, 0xf, 0, rt, imm);
+}
+
+static void bl_gen_ori(uint32_t **p, uint8_t rt, uint8_t rs, uint16_t imm)
+{
+    /* R6: OK, 32: OK */
+    bl_gen_i_type(p, 0xd, rs, rt, imm);
+}
+
+static void bl_gen_sw(uint32_t **p, uint8_t rt, uint8_t base, uint16_t offset)
+{
+    /* R6: OK, 32: NO */
+    bl_gen_i_type(p, 0x2b, base, rt, offset);
+}
+
+static void bl_gen_sd(uint32_t **p, uint8_t rt, uint8_t base, uint16_t offset)
+{
+    /* R6: OK, 32: NO */
+    bl_gen_i_type(p, 0x3f, base, rt, offset);
+}
+
+/* Pseudo instructions */
+static void bl_gen_li(uint32_t **p, uint8_t rt, uint32_t imm)
+{
+    /* R6: OK, 32 OK */
+    bl_gen_lui(p, rt, extract32(imm, 16, 16));
+    bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+}
+
+static void bl_gen_dli(uint32_t **p, uint8_t rt, uint64_t imm)
+{
+    /* R6: OK, 32 NO */
+    bl_gen_li(p, rt, extract64(imm, 32, 32));
+    bl_gen_dsll(p, rt, rt, 16);
+    bl_gen_daddiu(p, rt, rt, extract64(imm, 16, 16));
+    bl_gen_dsll(p, rt, rt, 16);
+    bl_gen_daddiu(p, rt, rt, extract64(imm, 0, 16));
+}
+
+/* Helpers */
+void bl_gen_jump_to(uint32_t **p, uint32_t jump_addr)
+{
+    /* Use ra to jump */
+    bl_gen_li(p, 31, jump_addr);
+    bl_gen_jalr(p, 31);
+    bl_gen_nop(p); /* delay slot, useless for R6 */
+}
+
+void bl_gen_jump_kernel(uint32_t **p, uint32_t sp, uint32_t a0,
+                        uint32_t a1, uint32_t a2, uint32_t a3,
+                        uint32_t kernel_addr)
+{
+    bl_gen_li(p, 29, sp);
+    bl_gen_li(p, 4, a0);
+    bl_gen_li(p, 5, a1);
+    bl_gen_li(p, 6, a2);
+    bl_gen_li(p, 7, a3);
+
+    bl_gen_jump_to(p, kernel_addr);
+}
+
+void bl_gen_writel(uint32_t **p, uint32_t val, uint32_t addr)
+{
+    bl_gen_li(p, 26, val);
+    bl_gen_li(p, 27, addr);
+    bl_gen_sw(p, 26, 27, 0x0);
+}
+
+void bl_gen_writeq(uint32_t **p, uint64_t val, uint32_t addr)
+{
+    /* 64 Only */
+    bl_gen_dli(p, 26, val);
+    bl_gen_li(p, 27, addr);
+    bl_gen_sd(p, 26, 27, 0x0);
+}
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index bcdf96be69..053459377f 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,5 +1,5 @@
 mips_ss = ss.source_set()
-mips_ss.add(files('addr.c', 'mips_int.c'))
+mips_ss.add(files('addr.c', 'bootloader.c', 'mips_int.c'))
 mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
 mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
 mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
index 291f59281a..0b3e060c95 100644
--- a/include/hw/mips/cpudevs.h
+++ b/include/hw/mips/cpudevs.h
@@ -12,6 +12,14 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
 bool mips_um_ksegs_enabled(void);
 void mips_um_ksegs_enable(void);
 
+/* bootloader.c */
+void bl_gen_jump_to(uint32_t **p, uint32_t jump_addr);
+void bl_gen_jump_kernel(uint32_t **p, uint32_t sp, uint32_t a0,
+                        uint32_t a1, uint32_t a2, uint32_t a3,
+                        uint32_t kernel_addr);
+void bl_gen_writel(uint32_t **p, uint32_t val, uint32_t addr);
+void bl_gen_writeq(uint32_t **p, uint64_t val, uint32_t addr);
+
 /* mips_int.c */
 void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
 
-- 
2.29.2

[PATCH 2/5] hw/mips/malta: Make use of bootloader helper

[Jiaxun Yang]

Use bootloader helper to generate BAR setting code
and kernel jump.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/mips/malta.c | 108 ++++++++++++------------------------------------
 1 file changed, 26 insertions(+), 82 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9d1a3b50b7..e9767e8744 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -841,14 +841,12 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
 static void write_bootloader(uint8_t *base, int64_t run_addr,
                              int64_t kernel_entry)
 {
-    uint32_t *p;
+    uint32_t *p, a0;
 
     /* Small bootloader */
     p = (uint32_t *)base;
 
-    stl_p(p++, 0x08000000 |                  /* j 0x1fc00580 */
-                 ((run_addr + 0x580) & 0x0fffffff) >> 2);
-    stl_p(p++, 0x00000000);                  /* nop */
+    bl_gen_jump_to(&p, run_addr + 0x580);
 
     /* YAMON service vector */
     stl_p(base + 0x500, run_addr + 0x0580);  /* start: */
@@ -869,88 +867,34 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
     /* Second part of the bootloader */
     p = (uint32_t *) (base + 0x580);
 
-    if (semihosting_get_argc()) {
-        /* Preserve a0 content as arguments have been passed */
-        stl_p(p++, 0x00000000);              /* nop */
-    } else {
-        stl_p(p++, 0x24040002);              /* addiu a0, zero, 2 */
-    }
-
-    /* lui sp, high(ENVP_ADDR) */
-    stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
-    /* ori sp, sp, low(ENVP_ADDR) */
-    stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
-    /* lui a1, high(ENVP_ADDR) */
-    stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
-    /* ori a1, a1, low(ENVP_ADDR) */
-    stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
-    /* lui a2, high(ENVP_ADDR + 8) */
-    stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
-    /* ori a2, a2, low(ENVP_ADDR + 8) */
-    stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
-    /* lui a3, high(ram_low_size) */
-    stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
-    /* ori a3, a3, low(ram_low_size) */
-    stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
-
-    /* Load BAR registers as done by YAMON */
-    stl_p(p++, 0x3c09b400);                  /* lui t1, 0xb400 */
-
-#ifdef TARGET_WORDS_BIGENDIAN
-    stl_p(p++, 0x3c08df00);                  /* lui t0, 0xdf00 */
-#else
-    stl_p(p++, 0x340800df);                  /* ori t0, r0, 0x00df */
-#endif
-    stl_p(p++, 0xad280068);                  /* sw t0, 0x0068(t1) */
-
-    stl_p(p++, 0x3c09bbe0);                  /* lui t1, 0xbbe0 */
-
-#ifdef TARGET_WORDS_BIGENDIAN
-    stl_p(p++, 0x3c08c000);                  /* lui t0, 0xc000 */
-#else
-    stl_p(p++, 0x340800c0);                  /* ori t0, r0, 0x00c0 */
-#endif
-    stl_p(p++, 0xad280048);                  /* sw t0, 0x0048(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
-    stl_p(p++, 0x3c084000);                  /* lui t0, 0x4000 */
-#else
-    stl_p(p++, 0x34080040);                  /* ori t0, r0, 0x0040 */
-#endif
-    stl_p(p++, 0xad280050);                  /* sw t0, 0x0050(t1) */
-
-#ifdef TARGET_WORDS_BIGENDIAN
-    stl_p(p++, 0x3c088000);                  /* lui t0, 0x8000 */
-#else
-    stl_p(p++, 0x34080080);                  /* ori t0, r0, 0x0080 */
-#endif
-    stl_p(p++, 0xad280058);                  /* sw t0, 0x0058(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
-    stl_p(p++, 0x3c083f00);                  /* lui t0, 0x3f00 */
-#else
-    stl_p(p++, 0x3408003f);                  /* ori t0, r0, 0x003f */
-#endif
-    stl_p(p++, 0xad280060);                  /* sw t0, 0x0060(t1) */
-
+    /* GT64xxxx is always big endian */
 #ifdef TARGET_WORDS_BIGENDIAN
-    stl_p(p++, 0x3c08c100);                  /* lui t0, 0xc100 */
+#define cpu_to_gt32(x) cpu_to_le32(x)
 #else
-    stl_p(p++, 0x340800c1);                  /* ori t0, r0, 0x00c1 */
+#define cpu_to_gt32(x) cpu_to_be32(x)
 #endif
-    stl_p(p++, 0xad280080);                  /* sw t0, 0x0080(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
-    stl_p(p++, 0x3c085e00);                  /* lui t0, 0x5e00 */
-#else
-    stl_p(p++, 0x3408005e);                  /* ori t0, r0, 0x005e */
-#endif
-    stl_p(p++, 0xad280088);                  /* sw t0, 0x0088(t1) */
+    /* Load BAR registers as done by YAMON */
+    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+    bl_gen_writel(&p, cpu_to_gt32(0xdf000000), 0xb4000068);
+
+    /* setup MEM-to-PCI0 mapping */
+    /* setup PCI0 io window to 0x18000000-0x181fffff */
+    bl_gen_writel(&p, cpu_to_gt32(0xc0000000), 0xbbe00048);
+    bl_gen_writel(&p, cpu_to_gt32(0x40000000), 0xbbe00050);
+    /* setup PCI0 mem windows */
+    bl_gen_writel(&p, cpu_to_gt32(0x80000000), 0xbbe00058);
+    bl_gen_writel(&p, cpu_to_gt32(0x3f000000), 0xbbe00060);
+    bl_gen_writel(&p, cpu_to_gt32(0xc1000000), 0xbbe00080);
+    bl_gen_writel(&p, cpu_to_gt32(0x5e000000), 0xbbe00088);
+#undef cpu_to_gt32
 
-    /* Jump to kernel code */
-    stl_p(p++, 0x3c1f0000 |
-          ((kernel_entry >> 16) & 0xffff));  /* lui ra, high(kernel_entry) */
-    stl_p(p++, 0x37ff0000 |
-          (kernel_entry & 0xffff));          /* ori ra, ra, low(kernel_entry) */
-    stl_p(p++, 0x03e00009);                  /* jalr ra */
-    stl_p(p++, 0x00000000);                  /* nop */
+    if (semihosting_get_argc()) {
+        a0 = 0;
+    } else {
+        a0 = 2;
+    }
+    bl_gen_jump_kernel(&p, ENVP_ADDR - 64, a0, ENVP_ADDR, (ENVP_ADDR + 8),
+                        loaderparams.ram_low_size, kernel_entry);
 
     /* YAMON subroutines */
     p = (uint32_t *) (base + 0x800);
-- 
2.29.2

[PATCH 3/5] hw/mips/fuloong2e: Make use of bootloader helper

[Jiaxun Yang]

Use bootloader helper to generate kernel jump.
Also move kernel jump to 0x580 to avoid collisions with exception
vectors.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/mips/fuloong2e.c | 35 +++++------------------------------
 1 file changed, 5 insertions(+), 30 deletions(-)

diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index a9e0c2f8d3..0a4809c816 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -186,38 +186,13 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
     /* Small bootloader */
     p = (uint32_t *)base;
 
-    /* j 0x1fc00040 */
-    stl_p(p++, 0x0bf00010);
-    /* nop */
-    stl_p(p++, 0x00000000);
+    bl_gen_jump_to(&p, 0xbfc00580);
 
     /* Second part of the bootloader */
-    p = (uint32_t *)(base + 0x040);
-
-    /* lui a0, 0 */
-    stl_p(p++, 0x3c040000);
-    /* ori a0, a0, 2 */
-    stl_p(p++, 0x34840002);
-    /* lui a1, high(ENVP_ADDR) */
-    stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
-    /* ori a1, a0, low(ENVP_ADDR) */
-    stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
-    /* lui a2, high(ENVP_ADDR + 8) */
-    stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
-    /* ori a2, a2, low(ENVP_ADDR + 8) */
-    stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
-    /* lui a3, high(env->ram_size) */
-    stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16));
-    /* ori a3, a3, low(env->ram_size) */
-    stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));
-    /* lui ra, high(kernel_addr) */
-    stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));
-    /* ori ra, ra, low(kernel_addr) */
-    stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff));
-    /* jr ra */
-    stl_p(p++, 0x03e00008);
-    /* nop */
-    stl_p(p++, 0x00000000);
+    p = (uint32_t *)(base + 0x580);
+
+    bl_gen_jump_kernel(&p, ENVP_ADDR - 64, 2, ENVP_ADDR, ENVP_ADDR + 8,
+                        loaderparams.ram_size, kernel_addr);
 }
 
 static void main_cpu_reset(void *opaque)
-- 
2.29.2

[PATCH 4/5] hw/mips/addr: Add translation helpers for KSEG1

[Jiaxun Yang]

It's useful for bootloader to do IO opreations.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/mips/addr.c            | 11 +++++++++++
 include/hw/mips/cpudevs.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/hw/mips/addr.c b/hw/mips/addr.c
index 2f138fe1ea..9d21cc2eb0 100644
--- a/hw/mips/addr.c
+++ b/hw/mips/addr.c
@@ -35,6 +35,17 @@ uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr)
     return addr | ~0x7fffffffll;
 }
 
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr)
+{
+    return addr & 0x1fffffffll;
+}
+
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr)
+{
+    return (addr & 0x1fffffffll) | 0xffffffffa0000000ll;
+}
+
+
 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
 {
     return addr | 0x40000000ll;
diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
index 0b3e060c95..048767db67 100644
--- a/include/hw/mips/cpudevs.h
+++ b/include/hw/mips/cpudevs.h
@@ -8,6 +8,8 @@
 /* addr.c */
 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
 bool mips_um_ksegs_enabled(void);
 void mips_um_ksegs_enable(void);
-- 
2.29.2

[PATCH 5/5] hw/mips/boston: Make use of bootloader helper

[Jiaxun Yang]

Use bootloader helper to generate CM Base setting code
and kernel jump.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/mips/boston.c | 60 +++++++++++-------------------------------------
 1 file changed, 13 insertions(+), 47 deletions(-)

diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 3d40867dc4..c784f8ee62 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -281,40 +281,20 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
     const uint32_t gic_base = 0x16120000;
     const uint32_t cpc_base = 0x16200000;
 
-    /* Move CM GCRs */
     if (is_64b) {
-        stl_p(p++, 0x40287803);                 /* dmfc0 $8, CMGCRBase */
-        stl_p(p++, 0x00084138);                 /* dsll $8, $8, 4 */
+        bl_gen_writeq(&p, cm_base,
+                    cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS));
+        bl_gen_writeq(&p, gic_base | GCR_GIC_BASE_GICEN_MSK,
+                    cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS));
+        bl_gen_writeq(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK,
+                    cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS));
     } else {
-        stl_p(p++, 0x40087803);                 /* mfc0 $8, CMGCRBase */
-        stl_p(p++, 0x00084100);                 /* sll  $8, $8, 4 */
-    }
-    stl_p(p++, 0x3c09a000);                     /* lui  $9, 0xa000 */
-    stl_p(p++, 0x01094025);                     /* or   $8, $9 */
-    stl_p(p++, 0x3c0a0000 | (cm_base >> 16));   /* lui  $10, cm_base >> 16 */
-    if (is_64b) {
-        stl_p(p++, 0xfd0a0008);                 /* sd   $10, 0x8($8) */
-    } else {
-        stl_p(p++, 0xad0a0008);                 /* sw   $10, 0x8($8) */
-    }
-    stl_p(p++, 0x012a4025);                     /* or   $8, $10 */
-
-    /* Move & enable GIC GCRs */
-    stl_p(p++, 0x3c090000 | (gic_base >> 16));  /* lui  $9, gic_base >> 16 */
-    stl_p(p++, 0x35290001);                     /* ori  $9, 0x1 */
-    if (is_64b) {
-        stl_p(p++, 0xfd090080);                 /* sd   $9, 0x80($8) */
-    } else {
-        stl_p(p++, 0xad090080);                 /* sw   $9, 0x80($8) */
-    }
-
-    /* Move & enable CPC GCRs */
-    stl_p(p++, 0x3c090000 | (cpc_base >> 16));  /* lui  $9, cpc_base >> 16 */
-    stl_p(p++, 0x35290001);                     /* ori  $9, 0x1 */
-    if (is_64b) {
-        stl_p(p++, 0xfd090088);                 /* sd   $9, 0x88($8) */
-    } else {
-        stl_p(p++, 0xad090088);                 /* sw   $9, 0x88($8) */
+        bl_gen_writel(&p, cm_base,
+                    cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS));
+        bl_gen_writel(&p, gic_base | GCR_GIC_BASE_GICEN_MSK,
+                    cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS));
+        bl_gen_writel(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK,
+                    cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS));
     }
 
     /*
@@ -325,21 +305,7 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
      * a2/$6 = 0
      * a3/$7 = 0
      */
-    stl_p(p++, 0x2404fffe);                     /* li   $4, -2 */
-                                                /* lui  $5, hi(fdt_addr) */
-    stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff));
-    if (fdt_addr & 0xffff) {                    /* ori  $5, lo(fdt_addr) */
-        stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff));
-    }
-    stl_p(p++, 0x34060000);                     /* li   $6, 0 */
-    stl_p(p++, 0x34070000);                     /* li   $7, 0 */
-
-    /* Load kernel entry address & jump to it */
-                                                /* lui  $25, hi(kernel_entry) */
-    stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff));
-                                                /* ori  $25, lo(kernel_entry) */
-    stl_p(p++, 0x37390000 | (kernel_entry & 0xffff));
-    stl_p(p++, 0x03200009);                     /* jr   $25 */
+    bl_gen_jump_kernel(&p, 0, -2, fdt_addr, 0, 0, kernel_entry);
 }
 
 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
-- 
2.29.2

Re: [PATCH 0/5] MIPS Bootloader helper

[Philippe Mathieu-Daudé]

On 12/7/20 6:02 AM, Jiaxun Yang wrote:
> Hi all,
> 
> I'm back! Now I'm also helping CIP United, the present owner of MIPS
> in China, take care of their open-souce infrastructures.
> 
> Btw: I'd like to add kernel boot tests for boston and incoming loongson-virt.
> Where should I place kernel binaries?

The easiest way is a tag in git repository.

See commits 89368673493 ("BootLinuxConsoleTest: Run kerneltests
BusyBox on Malta") and 4fe986dd448 ("tests/acceptance: console
boot tests for quanta-gsj").

> 
> Thanks.
> 
> Jiaxun Yang (5):
>   hw/mips: Add a bootloader helper
>   hw/mips/malta: Make use of bootloader helper
>   hw/mips/fuloong2e: Make use of bootloader helper
>   hw/mips/addr: Add translation helpers for KSEG1
>   hw/mips/boston: Make use of bootloader helper
> 
>  hw/mips/addr.c            |  11 +++
>  hw/mips/bootloader.c      | 150 ++++++++++++++++++++++++++++++++++++++
>  hw/mips/boston.c          |  60 ++++-----------
>  hw/mips/fuloong2e.c       |  35 ++-------
>  hw/mips/malta.c           | 108 +++++++--------------------
>  hw/mips/meson.build       |   2 +-
>  include/hw/mips/cpudevs.h |  10 +++
>  7 files changed, 216 insertions(+), 160 deletions(-)
>  create mode 100644 hw/mips/bootloader.c
> 

Re: [PATCH 1/5] hw/mips: Add a bootloader helper

[Philippe Mathieu-Daudé]

Hi Jiaxun,

On 12/7/20 6:02 AM, Jiaxun Yang wrote:
> Add a bootloader helper to generate simple bootloaders for kernel.
> It can help us reduce inline hex hack and also keep MIPS release 6
> compatibility easier.

Great idea :)

> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  hw/mips/bootloader.c      | 150 ++++++++++++++++++++++++++++++++++++++
>  hw/mips/meson.build       |   2 +-
>  include/hw/mips/cpudevs.h |   8 ++
>  3 files changed, 159 insertions(+), 1 deletion(-)
>  create mode 100644 hw/mips/bootloader.c
> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> new file mode 100644
> index 0000000000..3210c26bb7
> --- /dev/null
> +++ b/hw/mips/bootloader.c
> @@ -0,0 +1,150 @@
> +/*
> + * Utility for QEMU MIPS to generate it's simple bootloader
> + *
> + * Instructions used here are carefully selected to keep compatibility with
> + * MIPS Release 6.
> + *
> + * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "cpu.h"
> +#include "hw/mips/cpudevs.h"

Please keep the include local, and name it accordingly (bootloader.h).

Also, can you use an enum for the register values to make the code
easier to review?

enum {
    R_a0 = 4,
    R_a1 = 5,
    ...
    R_t0 = 26,
    R_t1 = 27,
    ...
    R_pc = 31,
};

> +
> +/* Base types */
> +static void bl_gen_nop(uint32_t **p)
> +{
> +    stl_p(*p, 0);
> +    *p = *p + 1;
> +}
> +
> +static void bl_gen_r_type(uint32_t **p, uint8_t opcode, uint8_t rs, uint8_t rt,
> +                            uint8_t rd, uint8_t shift, uint8_t funct)
> +{
> +    uint32_t insn = 0;
> +
> +    insn = deposit32(insn, 26, 6, opcode);
> +    insn = deposit32(insn, 21, 5, rs);
> +    insn = deposit32(insn, 16, 5, rt);
> +    insn = deposit32(insn, 11, 5, rd);
> +    insn = deposit32(insn, 6, 5, shift);
> +    insn = deposit32(insn, 0, 6, funct);
> +
> +    stl_p(*p, insn);
> +    *p = *p + 1;
> +}
> +
> +static void bl_gen_i_type(uint32_t **p, uint8_t opcode, uint8_t rs, uint8_t rt,
> +                            uint16_t imm)
> +{
> +    uint32_t insn = 0;
> +
> +    insn = deposit32(insn, 26, 6, opcode);
> +    insn = deposit32(insn, 21, 5, rs);
> +    insn = deposit32(insn, 16, 5, rt);
> +    insn = deposit32(insn, 0, 16, imm);
> +
> +    stl_p(*p, insn);
> +    *p = *p + 1;
> +}
> +
> +/* Single instructions */
> +static void bl_gen_dsll(uint32_t **p, uint8_t rd, uint8_t rt, uint8_t sa)
> +{
> +    /* R6: OK, 32: NO */
> +    bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
> +}

We should convert cpu_supports_isa() as:
bool cpu_supports_isa(MIPSCPU *cpu, uint64_t isa);
so passing a MIPSCPU (or CPUMIPSState) argument, you can do:

static void bl_gen_dsll(MIPSCPU *cpu, uint32_t **p,
                        uint8_t rd, uint8_t rt, uint8_t sa)
{
    if (cpu_supports_isa(cpu, ISA_MIPS32R6 | ISA_MIPS64R6)) {
        bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
    } else {
        g_assert_not_reached(); /* unsupported */
    }
}

> +
> +static void bl_gen_daddiu(uint32_t **p, uint8_t rt, uint8_t rs, uint16_t imm)
> +{
> +    /* R6: OK, 32: NO */

Ditto, etc...

> +    bl_gen_i_type(p, 0x19, rs, rt, imm);
> +}
> +
> +static void bl_gen_jalr(uint32_t **p, uint8_t rs)
> +{
> +    /* R6: OK, 32: OK */
> +    bl_gen_r_type(p, 0, rs, 0, 31, 0, 0x9);
> +}
> +
> +static void bl_gen_lui(uint32_t **p, uint8_t rt, uint16_t imm)
> +{
> +    /* R6: It's a alias of AUI with RS = 0, 32: OK */
> +    bl_gen_i_type(p, 0xf, 0, rt, imm);
> +}
> +
> +static void bl_gen_ori(uint32_t **p, uint8_t rt, uint8_t rs, uint16_t imm)
> +{
> +    /* R6: OK, 32: OK */
> +    bl_gen_i_type(p, 0xd, rs, rt, imm);
> +}
> +
> +static void bl_gen_sw(uint32_t **p, uint8_t rt, uint8_t base, uint16_t offset)
> +{
> +    /* R6: OK, 32: NO */
> +    bl_gen_i_type(p, 0x2b, base, rt, offset);
> +}
> +
> +static void bl_gen_sd(uint32_t **p, uint8_t rt, uint8_t base, uint16_t offset)
> +{
> +    /* R6: OK, 32: NO */
> +    bl_gen_i_type(p, 0x3f, base, rt, offset);
> +}
> +
> +/* Pseudo instructions */
> +static void bl_gen_li(uint32_t **p, uint8_t rt, uint32_t imm)
> +{
> +    /* R6: OK, 32 OK */
> +    bl_gen_lui(p, rt, extract32(imm, 16, 16));
> +    bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
> +}
> +
> +static void bl_gen_dli(uint32_t **p, uint8_t rt, uint64_t imm)
> +{
> +    /* R6: OK, 32 NO */
> +    bl_gen_li(p, rt, extract64(imm, 32, 32));
> +    bl_gen_dsll(p, rt, rt, 16);
> +    bl_gen_daddiu(p, rt, rt, extract64(imm, 16, 16));
> +    bl_gen_dsll(p, rt, rt, 16);
> +    bl_gen_daddiu(p, rt, rt, extract64(imm, 0, 16));
> +}
> +
> +/* Helpers */
> +void bl_gen_jump_to(uint32_t **p, uint32_t jump_addr)

bl_gen_jump_to_u32?

> +{
> +    /* Use ra to jump */
> +    bl_gen_li(p, 31, jump_addr);
> +    bl_gen_jalr(p, 31);
> +    bl_gen_nop(p); /* delay slot, useless for R6 */
> +}
> +
> +void bl_gen_jump_kernel(uint32_t **p, uint32_t sp, uint32_t a0,
> +                        uint32_t a1, uint32_t a2, uint32_t a3,
> +                        uint32_t kernel_addr)

bl_gen_jump_kernel_u32?

> +{
> +    bl_gen_li(p, 29, sp);
> +    bl_gen_li(p, 4, a0);
> +    bl_gen_li(p, 5, a1);
> +    bl_gen_li(p, 6, a2);
> +    bl_gen_li(p, 7, a3);
> +
> +    bl_gen_jump_to(p, kernel_addr);
> +}
> +
> +void bl_gen_writel(uint32_t **p, uint32_t val, uint32_t addr)

bl_gen_write_u32?

> +{
> +    bl_gen_li(p, 26, val);
> +    bl_gen_li(p, 27, addr);
> +    bl_gen_sw(p, 26, 27, 0x0);
> +}
> +
> +void bl_gen_writeq(uint32_t **p, uint64_t val, uint32_t addr)

Well, addr has to be uint64_t... else you wrap KSEG1 on 64-bit.

bl_gen_write_u64?

> +{
> +    /* 64 Only */

       if (!cpu_supports_isa(cpu, ISA_MIPS64)) {
           g_assert_not_reached(); /* unsupported */
       }

> +    bl_gen_dli(p, 26, val);
> +    bl_gen_li(p, 27, addr);
> +    bl_gen_sd(p, 26, 27, 0x0);
> +}
> diff --git a/hw/mips/meson.build b/hw/mips/meson.build
> index bcdf96be69..053459377f 100644
> --- a/hw/mips/meson.build
> +++ b/hw/mips/meson.build
> @@ -1,5 +1,5 @@
>  mips_ss = ss.source_set()
> -mips_ss.add(files('addr.c', 'mips_int.c'))
> +mips_ss.add(files('addr.c', 'bootloader.c', 'mips_int.c'))
>  mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
>  mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
>  mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
> diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
> index 291f59281a..0b3e060c95 100644
> --- a/include/hw/mips/cpudevs.h
> +++ b/include/hw/mips/cpudevs.h
> @@ -12,6 +12,14 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
>  bool mips_um_ksegs_enabled(void);
>  void mips_um_ksegs_enable(void);
>  
> +/* bootloader.c */

Not related to CPU internal devices, add to hw/mips/bootloader.h.

> +void bl_gen_jump_to(uint32_t **p, uint32_t jump_addr);
> +void bl_gen_jump_kernel(uint32_t **p, uint32_t sp, uint32_t a0,
> +                        uint32_t a1, uint32_t a2, uint32_t a3,
> +                        uint32_t kernel_addr);
> +void bl_gen_writel(uint32_t **p, uint32_t val, uint32_t addr);
> +void bl_gen_writeq(uint32_t **p, uint64_t val, uint32_t addr);
> +
>  /* mips_int.c */
>  void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
>  
> 

Re: [PATCH 2/5] hw/mips/malta: Make use of bootloader helper

[Philippe Mathieu-Daudé]

On 12/7/20 6:02 AM, Jiaxun Yang wrote:
> Use bootloader helper to generate BAR setting code
> and kernel jump.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  hw/mips/malta.c | 108 ++++++++++++------------------------------------
>  1 file changed, 26 insertions(+), 82 deletions(-)
> 
...
> +    /* GT64xxxx is always big endian */
>  #ifdef TARGET_WORDS_BIGENDIAN
> -    stl_p(p++, 0x3c08c100);                  /* lui t0, 0xc100 */
> +#define cpu_to_gt32(x) cpu_to_le32(x)
>  #else
> -    stl_p(p++, 0x340800c1);                  /* ori t0, r0, 0x00c1 */
> +#define cpu_to_gt32(x) cpu_to_be32(x)
>  #endif
> -    stl_p(p++, 0xad280080);                  /* sw t0, 0x0080(t1) */
> -#ifdef TARGET_WORDS_BIGENDIAN
> -    stl_p(p++, 0x3c085e00);                  /* lui t0, 0x5e00 */
> -#else
> -    stl_p(p++, 0x3408005e);                  /* ori t0, r0, 0x005e */
> -#endif
> -    stl_p(p++, 0xad280088);                  /* sw t0, 0x0088(t1) */
> +    /* Load BAR registers as done by YAMON */
> +    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
> +    bl_gen_writel(&p, cpu_to_gt32(0xdf000000), 0xb4000068);

Ideally we'd write as:

    bl_gen_writel(&p, cpu_to_be32(0x1be00000 << 3),
                  cpu_mips_phys_to_kseg1(NULL, 0x14000068));

But I guess this is enough:

    bl_gen_writel(&p, cpu_to_be32(0x1be00000 << 3), 0xb4000068);

No need for cpu_to_gt32().

From a review point of view, it would be easier to split your
patches in 2: first use bl_gen_write_u32/u64, second convert
bl_gen_jump_to_u32 and bl_gen_jump_kernel_u32.

> +
> +    /* setup MEM-to-PCI0 mapping */
> +    /* setup PCI0 io window to 0x18000000-0x181fffff */
> +    bl_gen_writel(&p, cpu_to_gt32(0xc0000000), 0xbbe00048);
> +    bl_gen_writel(&p, cpu_to_gt32(0x40000000), 0xbbe00050);
> +    /* setup PCI0 mem windows */
> +    bl_gen_writel(&p, cpu_to_gt32(0x80000000), 0xbbe00058);
> +    bl_gen_writel(&p, cpu_to_gt32(0x3f000000), 0xbbe00060);
> +    bl_gen_writel(&p, cpu_to_gt32(0xc1000000), 0xbbe00080);
> +    bl_gen_writel(&p, cpu_to_gt32(0x5e000000), 0xbbe00088);
> +#undef cpu_to_gt32
>  
> -    /* Jump to kernel code */
> -    stl_p(p++, 0x3c1f0000 |
> -          ((kernel_entry >> 16) & 0xffff));  /* lui ra, high(kernel_entry) */
> -    stl_p(p++, 0x37ff0000 |
> -          (kernel_entry & 0xffff));          /* ori ra, ra, low(kernel_entry) */
> -    stl_p(p++, 0x03e00009);                  /* jalr ra */
> -    stl_p(p++, 0x00000000);                  /* nop */
> +    if (semihosting_get_argc()) {
> +        a0 = 0;
> +    } else {
> +        a0 = 2;
> +    }
> +    bl_gen_jump_kernel(&p, ENVP_ADDR - 64, a0, ENVP_ADDR, (ENVP_ADDR + 8),
> +                        loaderparams.ram_low_size, kernel_entry);
>  
>      /* YAMON subroutines */
>      p = (uint32_t *) (base + 0x800);
> 

Re: [PATCH 1/5] hw/mips: Add a bootloader helper

[Philippe Mathieu-Daudé]

On 12/7/20 7:14 PM, Philippe Mathieu-Daudé wrote:
> Hi Jiaxun,
> 
> On 12/7/20 6:02 AM, Jiaxun Yang wrote:
>> Add a bootloader helper to generate simple bootloaders for kernel.
>> It can help us reduce inline hex hack and also keep MIPS release 6
>> compatibility easier.
> 
> Great idea :)
> 
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>>  hw/mips/bootloader.c      | 150 ++++++++++++++++++++++++++++++++++++++
>>  hw/mips/meson.build       |   2 +-
>>  include/hw/mips/cpudevs.h |   8 ++
>>  3 files changed, 159 insertions(+), 1 deletion(-)
>>  create mode 100644 hw/mips/bootloader.c
...
>> +void bl_gen_writeq(uint32_t **p, uint64_t val, uint32_t addr)
> 
> Well, addr has to be uint64_t... else you wrap KSEG1 on 64-bit.

Oops I misread addr/val.

> 
> bl_gen_write_u64?
> 
>> +{
>> +    /* 64 Only */
> 
>        if (!cpu_supports_isa(cpu, ISA_MIPS64)) {
>            g_assert_not_reached(); /* unsupported */
>        }
> 
>> +    bl_gen_dli(p, 26, val);
>> +    bl_gen_li(p, 27, addr);
>> +    bl_gen_sd(p, 26, 27, 0x0);
>> +}