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* [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V
@ 2023-07-31 12:10 Nathan Egge
  0 siblings, 0 replies; 6+ messages in thread
From: Nathan Egge @ 2023-07-31 12:10 UTC (permalink / raw)
  To: qemu-devel

[-- Attachment #1: Type: text/plain, Size: 101 bytes --]

One line patch that fixes the issue reported in:

https://gitlab.com/qemu-project/qemu/-/issues/1793

[-- Attachment #2: 0001-linux-user-elfload-Set-V-in-ELF_HWCAP-for-RISC-V.patch --]
[-- Type: text/x-patch, Size: 988 bytes --]

From 7122a450d745325ce250785e58c543481054bec6 Mon Sep 17 00:00:00 2001
From: "Nathan E. Egge" <negge@xiph.org>
Date: Mon, 31 Jul 2023 03:45:13 -0400
Subject: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V

Set V bit for hwcap if misa is set.

Signed-off-by: Nathan E. Egge <negge@xiph.org>
---
 linux-user/elfload.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 861ec07abc..a299ba7300 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void)
 #define MISA_BIT(EXT) (1 << (EXT - 'A'))
     RISCVCPU *cpu = RISCV_CPU(thread_cpu);
     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
-                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
+                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
+                    | MISA_BIT('V');
 
     return cpu->env.misa_ext & mask;
 #undef MISA_BIT
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V
  2023-08-08  6:36 ` Michael Tokarev
@ 2023-08-10 17:09   ` Alistair Francis
  0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2023-08-10 17:09 UTC (permalink / raw)
  To: Michael Tokarev
  Cc: Nathan Egge, Palmer Dabbelt, Alistair Francis, Bin Meng,
	Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv,
	qemu-devel

On Tue, Aug 8, 2023 at 2:37 AM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 03.08.2023 16:14, Nathan Egge wrote:
> > From: "Nathan Egge" <negge@xiph.org>
> >
> > Set V bit for hwcap if misa is set.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
> > Signed-off-by: Nathan Egge <negge@xiph.org>
> > ---
> >   linux-user/elfload.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> > index 861ec07abc..a299ba7300 100644
> > --- a/linux-user/elfload.c
> > +++ b/linux-user/elfload.c
> > @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void)
> >   #define MISA_BIT(EXT) (1 << (EXT - 'A'))
> >       RISCVCPU *cpu = RISCV_CPU(thread_cpu);
> >       uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> > -                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
> > +                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
> > +                    | MISA_BIT('V');
>
> Is smells like a -stable material (incl. 7.2), is it not?

I think so as well

Alistair

>
> Thanks,
>
> /mjt
>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V
  2023-08-03 13:14 Nathan Egge
  2023-08-03 14:42 ` Daniel Henrique Barboza
@ 2023-08-08  6:36 ` Michael Tokarev
  2023-08-10 17:09   ` Alistair Francis
  1 sibling, 1 reply; 6+ messages in thread
From: Michael Tokarev @ 2023-08-08  6:36 UTC (permalink / raw)
  To: Nathan Egge, Palmer Dabbelt, Alistair Francis, Bin Meng
  Cc: Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv, qemu-devel

03.08.2023 16:14, Nathan Egge wrote:
> From: "Nathan Egge" <negge@xiph.org>
> 
> Set V bit for hwcap if misa is set.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
> Signed-off-by: Nathan Egge <negge@xiph.org>
> ---
>   linux-user/elfload.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 861ec07abc..a299ba7300 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void)
>   #define MISA_BIT(EXT) (1 << (EXT - 'A'))
>       RISCVCPU *cpu = RISCV_CPU(thread_cpu);
>       uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> -                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
> +                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
> +                    | MISA_BIT('V');

Is smells like a -stable material (incl. 7.2), is it not?

Thanks,

/mjt


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V
  2023-08-03 14:42 ` Daniel Henrique Barboza
@ 2023-08-04 16:17   ` Richard Henderson
  0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2023-08-04 16:17 UTC (permalink / raw)
  To: Daniel Henrique Barboza, Nathan Egge, Palmer Dabbelt,
	Alistair Francis, Bin Meng
  Cc: Weiwei Li, Liu Zhiwei, qemu-riscv, qemu-devel

On 8/3/23 07:42, Daniel Henrique Barboza wrote:
> 
> 
> On 8/3/23 10:14, Nathan Egge wrote:
>> From: "Nathan Egge" <negge@xiph.org>
>>
>> Set V bit for hwcap if misa is set.
>>
>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
>> Signed-off-by: Nathan Egge <negge@xiph.org>
>> ---
> 
> Tested with the example program described in the bug:
> 
> ===========
> #include <sys/auxv.h>
> #include <stdio.h>
> 
> #define ISA_V_HWCAP (1 << ('v' - 'a'))
> 
> void main() {
>    unsigned long hw_cap = getauxval(AT_HWCAP);
>    printf("RVV %s\n", hw_cap & ISA_V_HWCAP ? "detected" : "not found");
> }
> ===========
> 
> $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,v=true,vlen=128 -B 0x100000 ./a.out
> RVV detected
> $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,vlen=128 -B 0x100000 ./a.out
> RVV not found
> 
> 
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> 
> 
> Looks like 8.1 material to me. Thanks,

Queued to tcg-next.


r~


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V
  2023-08-03 13:14 Nathan Egge
@ 2023-08-03 14:42 ` Daniel Henrique Barboza
  2023-08-04 16:17   ` Richard Henderson
  2023-08-08  6:36 ` Michael Tokarev
  1 sibling, 1 reply; 6+ messages in thread
From: Daniel Henrique Barboza @ 2023-08-03 14:42 UTC (permalink / raw)
  To: Nathan Egge, Palmer Dabbelt, Alistair Francis, Bin Meng
  Cc: Weiwei Li, Liu Zhiwei, qemu-riscv, qemu-devel



On 8/3/23 10:14, Nathan Egge wrote:
> From: "Nathan Egge" <negge@xiph.org>
> 
> Set V bit for hwcap if misa is set.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
> Signed-off-by: Nathan Egge <negge@xiph.org>
> ---

Tested with the example program described in the bug:

===========
#include <sys/auxv.h>
#include <stdio.h>

#define ISA_V_HWCAP (1 << ('v' - 'a'))

void main() {
   unsigned long hw_cap = getauxval(AT_HWCAP);
   printf("RVV %s\n", hw_cap & ISA_V_HWCAP ? "detected" : "not found");
}
===========

$ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,v=true,vlen=128 -B 0x100000 ./a.out
RVV detected
$ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,vlen=128 -B 0x100000 ./a.out
RVV not found


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>


Looks like 8.1 material to me. Thanks,


Daniel

>   linux-user/elfload.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 861ec07abc..a299ba7300 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void)
>   #define MISA_BIT(EXT) (1 << (EXT - 'A'))
>       RISCVCPU *cpu = RISCV_CPU(thread_cpu);
>       uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> -                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
> +                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
> +                    | MISA_BIT('V');
>   
>       return cpu->env.misa_ext & mask;
>   #undef MISA_BIT


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V
@ 2023-08-03 13:14 Nathan Egge
  2023-08-03 14:42 ` Daniel Henrique Barboza
  2023-08-08  6:36 ` Michael Tokarev
  0 siblings, 2 replies; 6+ messages in thread
From: Nathan Egge @ 2023-08-03 13:14 UTC (permalink / raw)
  To: Palmer Dabbelt, Alistair Francis, Bin Meng
  Cc: Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv,
	qemu-devel, Nathan Egge

From: "Nathan Egge" <negge@xiph.org>

Set V bit for hwcap if misa is set.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
Signed-off-by: Nathan Egge <negge@xiph.org>
---
 linux-user/elfload.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 861ec07abc..a299ba7300 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void)
 #define MISA_BIT(EXT) (1 << (EXT - 'A'))
     RISCVCPU *cpu = RISCV_CPU(thread_cpu);
     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
-                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
+                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
+                    | MISA_BIT('V');
 
     return cpu->env.misa_ext & mask;
 #undef MISA_BIT
-- 
2.35.1



^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-08-10 17:10 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-07-31 12:10 [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V Nathan Egge
2023-08-03 13:14 Nathan Egge
2023-08-03 14:42 ` Daniel Henrique Barboza
2023-08-04 16:17   ` Richard Henderson
2023-08-08  6:36 ` Michael Tokarev
2023-08-10 17:09   ` Alistair Francis

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