* [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree
@ 2021-10-27 18:06 Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
` (32 more replies)
0 siblings, 33 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Since v1:
- Addressed Richard comments (thanks, I learned a lot doing so!
Although I consider this series 'boring' I enjoyed working on
your review comments).
- Included Jiaxun R-b tags, but they are conditional on Richard
ones.
v1 unchanged cover:
Hi,
This series converts 2000+ lines of switch() code to decodetree
description, so this hard-to-review/modify switch is auto generated
by the decodetree script. This is a big win for maintenance (and
indeed the convertion revealed 2 bugs).
Massive convertions are - beside being often boring - bug-prone.
In this series we re-start running the MSA tests (the tests are
run automagically in the 'build-user-static' job on gitlab CI).
Although boring, the conversion is very clean, so I hope it will
be easy enough to review. The TRANS*() macros are heavily used.
When possible, constant fields are hold with tcg_constant().
Note, various opcodes can be optimized using TCG host vectors.
We won't address that in this series, as it makes the resulting
review harder. We will post that in a following series. Here we
simply dummy-convert.
The resulting msa.decode file is quite pleasant to look at, and
the diff-stat is encouraging: number of LoC halved.
Regards,
Phil.
git: https://gitlab.com/philmd/qemu.git tree/mips-msa-decodetree
Based-on: <20211023164329.328137-1-f4bug@amsat.org>
Philippe Mathieu-Daudé (32):
target/mips: Fix MSA MADDV.B opcode
target/mips: Fix MSA MSUBV.B opcode
tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
target/mips: Use dup_const() to simplify
target/mips: Have check_msa_access() return a boolean
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
target/mips: Convert MSA LDI opcode to decodetree
target/mips: Convert MSA I5 instruction format to decodetree
target/mips: Convert MSA BIT instruction format to decodetree
target/mips: Convert MSA SHF opcode to decodetree
target/mips: Convert MSA I8 instruction format to decodetree
target/mips: Convert MSA load/store instruction format to decodetree
target/mips: Convert MSA 2RF instruction format to decodetree
target/mips: Convert MSA FILL opcode to decodetree
target/mips: Convert MSA 2R instruction format to decodetree
target/mips: Convert MSA VEC instruction format to decodetree
target/mips: Convert MSA 3RF instruction format to decodetree
(DF_HALF)
target/mips: Convert MSA 3RF instruction format to decodetree
(DF_WORD)
target/mips: Convert MSA 3R instruction format to decodetree (part
1/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
2/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
3/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
4/4)
target/mips: Convert MSA ELM instruction format to decodetree
target/mips: Convert MSA COPY_U opcode to decodetree
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
target/mips: Convert MSA MOVE.V opcode to decodetree
target/mips: Convert CFCMSA opcode to decodetree
target/mips: Convert CTCMSA opcode to decodetree
target/mips: Remove generic MSA opcode
target/mips: Remove one MSA unnecessary decodetree overlap group
target/mips: Adjust style in msa_translate_init()
tests/tcg/mips/ase-msa.mak | 30 +
target/mips/tcg/msa.decode | 241 ++-
target/mips/tcg/msa_helper.c | 64 +-
target/mips/tcg/msa_translate.c | 2746 +++++++---------------------
MAINTAINERS | 1 +
tests/tcg/mips/Makefile.target | 5 +
tests/tcg/mips64/Makefile.target | 9 +
tests/tcg/mips64el/Makefile.target | 12 +
tests/tcg/mipsel/Makefile.target | 9 +
9 files changed, 969 insertions(+), 2148 deletions(-)
create mode 100644 tests/tcg/mips/ase-msa.mak
create mode 100644 tests/tcg/mips64/Makefile.target
create mode 100644 tests/tcg/mips64el/Makefile.target
create mode 100644 tests/tcg/mipsel/Makefile.target
--
2.31.1
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
@ 2021-10-27 18:06 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
` (31 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:06 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
The result of the 'Vector Multiply and Add' opcode is incorrect
with Byte vectors. Probably due to a copy/paste error, commit
7a7a162adde mistakenly used the $wt (target register) instead
of $wd (destination register) as first operand. Fix that.
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index e40c1b70575..d978909527f 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
- pwd->b[0] = msa_maddv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
- pwd->b[1] = msa_maddv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
- pwd->b[2] = msa_maddv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
- pwd->b[3] = msa_maddv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
- pwd->b[4] = msa_maddv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
- pwd->b[5] = msa_maddv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
- pwd->b[6] = msa_maddv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
- pwd->b[7] = msa_maddv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
- pwd->b[8] = msa_maddv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
- pwd->b[9] = msa_maddv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
- pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
- pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
- pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
- pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
- pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
- pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+ pwd->b[0] = msa_maddv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_maddv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_maddv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_maddv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_maddv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_maddv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_maddv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_maddv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_maddv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_maddv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
}
void helper_msa_maddv_h(CPUMIPSState *env,
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
` (30 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
The result of the 'Vector Multiply and Subtract' opcode is
incorrect with Byte vectors. Probably due to a copy/paste error,
commit 5f148a02327 mistakenly used the $wt (target register)
instead of $wd (destination register) as first operand. Fix that.
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index d978909527f..5667b1f0a15 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3303,22 +3303,22 @@ void helper_msa_msubv_b(CPUMIPSState *env,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
- pwd->b[0] = msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
- pwd->b[1] = msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
- pwd->b[2] = msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
- pwd->b[3] = msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
- pwd->b[4] = msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
- pwd->b[5] = msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
- pwd->b[6] = msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
- pwd->b[7] = msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
- pwd->b[8] = msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
- pwd->b[9] = msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
- pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
- pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
- pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
- pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
- pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
- pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+ pwd->b[0] = msa_msubv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_msubv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_msubv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_msubv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_msubv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_msubv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_msubv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_msubv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_msubv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_msubv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_msubv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_msubv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_msubv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_msubv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_msubv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_msubv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
}
void helper_msa_msubv_h(CPUMIPSState *env,
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
` (29 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Alex Bennée, Philippe Mathieu-Daudé,
Aurelien Jarno
The following commits added various user-mode tests
for various MSA instructions:
- 0fdd986a6c8 ("Add tests for MSA integer add instructions")
- 1be82d89011 ("Add tests for MSA integer average instructions")
- 1d336c87a3c ("Add tests for MSA bit set instructions")
- 1e6bea794c8 ("Add tests for MSA integer max/min instructions")
- 2a367db039f ("Add tests for MSA pack instructions")
- 3d9569b8550 ("Add tests for MSA move instructions")
- 4b302ce90db ("Add tests for MSA integer multiply instructions")
- 520e210c0aa ("Add tests for MSA integer compare instructions")
- 53e116fed6d ("Add tests for MSA integer subtract instructions")
- 666952ea7c1 ("Add tests for MSA bit move instructions")
- 72f463bc080 ("Add tests for MSA integer divide instructions")
- 8598f5fac1c ("Add tests for MSA FP max/min instructions")
- 99d423e576a ("Add tests for MSA shift instructions")
- a8f91dd9fd0 ("Add tests for MSA integer dot product instructions")
- b62592ab655 ("Add tests for MSA bit counting instructions")
- ba632924450 ("Add tests for MSA logic instructions")
- fc76f486677 ("Add tests for MSA interleave instructions")
Cover them in the buildsys machinery so they are run automatically
when calling 'make check-tcg'.
Start running them on the mips64el target.
Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Notes:
- I am using $wilcard because because the test files are in multiple
directories ($MSA_TEST_CLASS).
- mips32 tests are disabled because the Debian toolchain produces:
/usr/mips-linux-gnu/include/gnu/stubs.h:17:11: fatal error:
gnu/stubs-o32_hard_2008.h: No such file or directory
# include <gnu/stubs-o32_hard_2008.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~
---
tests/tcg/mips/ase-msa.mak | 30 ++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
tests/tcg/mips/Makefile.target | 5 +++++
tests/tcg/mips64/Makefile.target | 9 +++++++++
tests/tcg/mips64el/Makefile.target | 12 ++++++++++++
tests/tcg/mipsel/Makefile.target | 9 +++++++++
6 files changed, 66 insertions(+)
create mode 100644 tests/tcg/mips/ase-msa.mak
create mode 100644 tests/tcg/mips64/Makefile.target
create mode 100644 tests/tcg/mips64el/Makefile.target
create mode 100644 tests/tcg/mipsel/Makefile.target
diff --git a/tests/tcg/mips/ase-msa.mak b/tests/tcg/mips/ase-msa.mak
new file mode 100644
index 00000000000..be1ba967a5b
--- /dev/null
+++ b/tests/tcg/mips/ase-msa.mak
@@ -0,0 +1,30 @@
+# -*- Mode: makefile -*-
+#
+# MIPS MSA specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+MSA_DIR = $(SRC_PATH)/tests/tcg/mips/user/ase/msa
+
+MSA_TEST_CLASS = bit-count bit-move bit-set fixed-multiply \
+ float-max-min int-add int-average int-compare int-divide \
+ int-dot-product interleave int-max-min int-modulo \
+ int-multiply int-subtract logic move pack shift
+
+MSA_TEST_SRCS = $(foreach class,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(class)/*.c))
+
+MSA_TESTS = $(patsubst %.c,%,$(notdir $(MSA_TEST_SRCS)))
+
+$(MSA_TESTS): CFLAGS+=-mmsa $(MSA_CFLAGS)
+$(MSA_TESTS): %: $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/%.c))
+ $(CC) -static $(CFLAGS) -o $@ \
+ $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/$@.c))
+
+$(foreach test,$(MSA_TESTS),run-$(test)): QEMU_OPTS += -cpu $(MSA_CPU)
+
+# FIXME: These tests fail when using plugins
+ifneq ($(CONFIG_PLUGIN),y)
+TESTS += $(MSA_TESTS)
+endif
diff --git a/MAINTAINERS b/MAINTAINERS
index 894dc431052..0a1475a6e83 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3112,6 +3112,7 @@ R: Jiaxun Yang <jiaxun.yang@flygoat.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Odd Fixes
F: tcg/mips/
+F: tests/tcg/mips*
PPC TCG target
M: Richard Henderson <richard.henderson@linaro.org>
diff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target
index 1a994d5525e..fc54f144f37 100644
--- a/tests/tcg/mips/Makefile.target
+++ b/tests/tcg/mips/Makefile.target
@@ -17,3 +17,8 @@ TESTS += $(MIPS_TESTS)
hello-mips: CFLAGS+=-mno-abicalls -fno-PIC -mabi=32
hello-mips: LDFLAGS+=-nostdlib
endif
+
+# FIXME enable MSA tests
+#MSA_CFLAGS=-march=mips32r5 -mnan=2008
+#MSA_CPU=P5600
+#include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
diff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target
new file mode 100644
index 00000000000..d876b92f219
--- /dev/null
+++ b/tests/tcg/mips64/Makefile.target
@@ -0,0 +1,9 @@
+# -*- Mode: makefile -*-
+#
+# mips64el specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# 64-bit MSA is tested on little-endian target
diff --git a/tests/tcg/mips64el/Makefile.target b/tests/tcg/mips64el/Makefile.target
new file mode 100644
index 00000000000..87c0d6dce18
--- /dev/null
+++ b/tests/tcg/mips64el/Makefile.target
@@ -0,0 +1,12 @@
+# -*- Mode: makefile -*-
+#
+# mips64el specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MSA
+MSA_CFLAGS=-march=mips64r5 -mnan=legacy
+MSA_CPU=Loongson-3A4000
+include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
diff --git a/tests/tcg/mipsel/Makefile.target b/tests/tcg/mipsel/Makefile.target
new file mode 100644
index 00000000000..c8acacb4497
--- /dev/null
+++ b/tests/tcg/mipsel/Makefile.target
@@ -0,0 +1,9 @@
+# -*- Mode: makefile -*-
+#
+# mipsel specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# 32-bit MSA is tested on big-endian target
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 04/32] target/mips: Use dup_const() to simplify
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 19:06 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
` (28 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
The dup_const() helper makes the code easier to follow, use it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 23 +++--------------------
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..bc57e06d923 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -313,28 +313,11 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
{
/* generates tcg ops to check if any element is 0 */
/* Note this function only works with MSA_WRLEN = 128 */
- uint64_t eval_zero_or_big = 0;
- uint64_t eval_big = 0;
+ uint64_t eval_zero_or_big = dup_const(df, 0x01);
+ uint64_t eval_big = dup_const(df, 0x80);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
- switch (df) {
- case DF_BYTE:
- eval_zero_or_big = 0x0101010101010101ULL;
- eval_big = 0x8080808080808080ULL;
- break;
- case DF_HALF:
- eval_zero_or_big = 0x0001000100010001ULL;
- eval_big = 0x8000800080008000ULL;
- break;
- case DF_WORD:
- eval_zero_or_big = 0x0000000100000001ULL;
- eval_big = 0x8000000080000000ULL;
- break;
- case DF_DOUBLE:
- eval_zero_or_big = 0x0000000000000001ULL;
- eval_big = 0x8000000000000000ULL;
- break;
- }
+
tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big);
tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]);
tcg_gen_andi_i64(t0, t0, eval_big);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 19:07 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
` (27 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled (the instruction got
decoded properly, but we raised an exception).
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: return true (opcode decoded) because the opcode is decoded, reword
---
target/mips/tcg/msa_translate.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index bc57e06d923..5acb27f1d71 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -293,19 +293,24 @@ void msa_translate_init(void)
}
}
-static inline int check_msa_access(DisasContext *ctx)
+/*
+ * Check if MSA is enabled.
+ * This function is always called with MSA available.
+ * If MSA is disabled, raise an exception.
+ */
+static inline bool check_msa_enabled(DisasContext *ctx)
{
if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
!(ctx->hflags & MIPS_HFLAG_F64))) {
gen_reserved_instruction(ctx);
- return 0;
+ return false;
}
if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
generate_exception_end(ctx, EXCP_MSADIS);
- return 0;
+ return false;
}
- return 1;
+ return true;
}
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
@@ -337,7 +342,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
{
TCGv_i64 t0;
- check_msa_access(ctx);
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
if (ctx->hflags & MIPS_HFLAG_BMASK) {
gen_reserved_instruction(ctx);
@@ -369,7 +376,9 @@ static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
{
- check_msa_access(ctx);
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
if (ctx->hflags & MIPS_HFLAG_BMASK) {
gen_reserved_instruction(ctx);
@@ -2141,7 +2150,9 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
{
uint32_t opcode = ctx->opcode;
- check_msa_access(ctx);
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
switch (MASK_MSA_MINOR(opcode)) {
case OPC_MSA_I8_00:
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
` (26 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5acb27f1d71..41ade61879e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1789,10 +1789,10 @@ static void gen_msa_3rf(DisasContext *ctx)
case OPC_MULR_Q_df:
case OPC_MADDR_Q_df:
case OPC_MSUBR_Q_df:
- tdf = tcg_constant_i32(df + 1);
+ tdf = tcg_constant_i32(DF_HALF + df);
break;
default:
- tdf = tcg_constant_i32(df + 2);
+ tdf = tcg_constant_i32(DF_WORD + df);
break;
}
@@ -2021,7 +2021,7 @@ static void gen_msa_2rf(DisasContext *ctx)
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
/* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_constant_i32(df + 2);
+ TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
switch (MASK_MSA_2RF(ctx->opcode)) {
case OPC_FCLASS_df:
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
` (25 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.
Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).
Since we modify &msa_bz, re-align its arguments, so the other
structures added in the following commits stay visually aligned.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 15 +++++++--------
target/mips/tcg/msa_translate.c | 20 ++++++++++----------
2 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 74d99f6862c..56419a24eb9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,19 +13,18 @@
&r rs rt rd sa
-&msa_bz df wt s16
+&msa_bz df wt sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
-@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
-@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
+@bz ...... ... df:2 wt:5 sa:16 &msa_bz
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
-BZ_V 010001 01011 ..... ................ @bz
-BNZ_V 010001 01111 ..... ................ @bz
-
-BZ_x 010001 110 .. ..... ................ @bz_df
-BNZ_x 010001 111 .. ..... ................ @bz_df
+BZ_V 010001 01011 ..... ................ @bz_v
+BNZ_V 010001 01111 ..... ................ @bz_v
+BZ 010001 110 .. ..... ................ @bz
+BNZ 010001 111 .. ..... ................ @bz
MSA 011110 --------------------------
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 41ade61879e..0aaf441f359 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -338,7 +338,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
tcg_temp_free_i64(t1);
}
-static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
{
TCGv_i64 t0;
@@ -356,7 +356,7 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
tcg_gen_trunc_i64_tl(bcond, t0);
tcg_temp_free_i64(t0);
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
@@ -366,15 +366,15 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+ return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ);
}
static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+ return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE);
}
-static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not)
{
if (!check_msa_enabled(ctx)) {
return true;
@@ -387,21 +387,21 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
return true;
}
-static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false);
}
-static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
}
static void gen_msa_i8(DisasContext *ctx)
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 19:10 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
` (24 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert the LDI opcode (Immediate Load) to decodetree. Since it
overlaps with the generic MSA handler, use a decodetree overlap
group.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- add &msa_ldi format
- !check_msa_enabled -> return true
- TCG timm is constant
---
target/mips/tcg/msa.decode | 8 +++++++-
target/mips/tcg/msa_translate.c | 22 ++++++++++++++--------
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 56419a24eb9..bdfe5a24cb3 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -14,10 +14,12 @@
&r rs rt rd sa
&msa_bz df wt sa
+&msa_ldi df wd sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
@@ -27,4 +29,8 @@ BNZ_V 010001 01111 ..... ................ @bz_v
BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
-MSA 011110 --------------------------
+{
+ LDI 011110 110 .. .......... ..... 000111 @ldi
+
+ MSA 011110 --------------------------
+}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 0aaf441f359..46f5ba092e1 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -70,7 +70,6 @@ enum {
OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
- OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07,
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
@@ -513,13 +512,6 @@ static void gen_msa_i5(DisasContext *ctx)
case OPC_CLEI_U_df:
gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
break;
- case OPC_LDI_df:
- {
- int32_t s10 = sextract32(ctx->opcode, 11, 10);
- tcg_gen_movi_i32(timm, s10);
- gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -532,6 +524,20 @@ static void gen_msa_i5(DisasContext *ctx)
tcg_temp_free_i32(timm);
}
+static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a)
+{
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_helper_msa_ldi_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->sa));
+
+ return true;
+}
+
static void gen_msa_bit(DisasContext *ctx)
{
#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 19:17 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
` (23 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert instructions with a 5-bit immediate value to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- add &msa_i5 format
- TRANS_MSA() calls check_msa_enabled()
- TCG timm is constant
---
target/mips/tcg/msa.decode | 16 +++++
target/mips/tcg/msa_translate.c | 114 ++++++++++----------------------
2 files changed, 52 insertions(+), 78 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index bdfe5a24cb3..115e90b4fce 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -15,10 +15,13 @@
&msa_bz df wt sa
&msa_ldi df wd sa
+&msa_i5 df wd ws sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
+@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
@@ -30,6 +33,19 @@ BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
{
+ ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
+ SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
+ MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
+ MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
+ MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
+ MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
+
+ CEQI 011110 000 .. ..... ..... ..... 000111 @s5
+ CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
+ CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
+ CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
+ CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
+
LDI 011110 110 .. .......... ..... 000111 @ldi
MSA 011110 --------------------------
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 46f5ba092e1..ca70c38c866 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
OPC_MSA_I8_00 = 0x00 | OPC_MSA,
OPC_MSA_I8_01 = 0x01 | OPC_MSA,
OPC_MSA_I8_02 = 0x02 | OPC_MSA,
- OPC_MSA_I5_06 = 0x06 | OPC_MSA,
- OPC_MSA_I5_07 = 0x07 | OPC_MSA,
OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
OPC_MSA_3R_0D = 0x0D | OPC_MSA,
@@ -58,19 +56,6 @@ enum {
};
enum {
- /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
- OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
- OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
- OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
- OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
- OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
- OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
- OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
-
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
@@ -312,6 +297,22 @@ static inline bool check_msa_enabled(DisasContext *ctx)
return true;
}
+typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
+
+/*
+ * Helpers for implementing sets of trans_* functions.
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
+ * All helpers check whether MSA is enabled.
+ */
+#define TRANS_MSA(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { \
+ if (!check_msa_enabled(ctx)) { \
+ return true; \
+ } \
+ return FUNC(ctx, a, __VA_ARGS__); \
+ }
+
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@@ -461,69 +462,30 @@ static void gen_msa_i8(DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
-static void gen_msa_i5(DisasContext *ctx)
+static bool trans_msa_i5(DisasContext *ctx, arg_msa_i5 *a,
+ gen_helper_piiii *gen_msa_i5)
{
-#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
- uint8_t u5 = extract32(ctx->opcode, 16, 5);
+ gen_msa_i5(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->sa));
- TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
- TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
- TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
- TCGv_i32 timm = tcg_temp_new_i32();
- tcg_gen_movi_i32(timm, u5);
-
- switch (MASK_MSA_I5(ctx->opcode)) {
- case OPC_ADDVI_df:
- gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_SUBVI_df:
- gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_U_df:
- gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_U_df:
- gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CEQI_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_U_df:
- gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_U_df:
- gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(tdf);
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(timm);
+ return true;
}
+TRANS_MSA(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df);
+TRANS_MSA(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df);
+TRANS_MSA(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df);
+TRANS_MSA(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df);
+TRANS_MSA(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df);
+TRANS_MSA(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df);
+TRANS_MSA(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df);
+TRANS_MSA(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df);
+TRANS_MSA(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df);
+TRANS_MSA(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df);
+TRANS_MSA(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df);
+
static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a)
{
if (!check_msa_enabled(ctx)) {
@@ -2166,10 +2128,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_I8_02:
gen_msa_i8(ctx);
break;
- case OPC_MSA_I5_06:
- case OPC_MSA_I5_07:
- gen_msa_i5(ctx);
- break;
case OPC_MSA_BIT_09:
case OPC_MSA_BIT_0A:
gen_msa_bit(ctx);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 10/32] target/mips: Convert MSA BIT instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:20 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
` (22 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert instructions with an immediate bit index and
data format df/m to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- dfm field in decodetree format
- index array by CPUMIPSMSADataFormat to avoid dup
- TCG tm is constant
---
target/mips/tcg/msa.decode | 19 ++++
target/mips/tcg/msa_translate.c | 177 ++++++++++++++------------------
2 files changed, 98 insertions(+), 98 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 115e90b4fce..c4699b9d4b7 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -16,6 +16,10 @@
&msa_bz df wt sa
&msa_ldi df wd sa
&msa_i5 df wd ws sa
+&msa_bit df wd ws m
+
+%dfm_df 16:7 !function=msa_bit_df
+%dfm_m 16:7 !function=msa_bit_m
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@@ -23,6 +27,7 @@
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
+@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%dfm_df m=%dfm_m
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
@@ -48,5 +53,19 @@ BNZ 010001 111 .. ..... ................ @bz
LDI 011110 110 .. .......... ..... 000111 @ldi
+ SLLI 011110 000 ....... ..... ..... 001001 @bit
+ SRAI 011110 001 ....... ..... ..... 001001 @bit
+ SRLI 011110 010 ....... ..... ..... 001001 @bit
+ BCLRI 011110 011 ....... ..... ..... 001001 @bit
+ BSETI 011110 100 ....... ..... ..... 001001 @bit
+ BNEGI 011110 101 ....... ..... ..... 001001 @bit
+ BINSLI 011110 110 ....... ..... ..... 001001 @bit
+ BINSRI 011110 111 ....... ..... ..... 001001 @bit
+
+ SAT_S 011110 000 ....... ..... ..... 001010 @bit
+ SAT_U 011110 001 ....... ..... ..... 001010 @bit
+ SRARI 011110 010 ....... ..... ..... 001010 @bit
+ SRLRI 011110 011 ....... ..... ..... 001010 @bit
+
MSA 011110 --------------------------
}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ca70c38c866..175254c1e47 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -17,6 +17,9 @@
#include "fpu_helper.h"
#include "internal.h"
+static int msa_bit_m(DisasContext *ctx, int x);
+static int msa_bit_df(DisasContext *ctx, int x);
+
/* Include the auto-generated decoder. */
#include "decode-msa.c.inc"
@@ -27,8 +30,6 @@ enum {
OPC_MSA_I8_00 = 0x00 | OPC_MSA,
OPC_MSA_I8_01 = 0x01 | OPC_MSA,
OPC_MSA_I8_02 = 0x02 | OPC_MSA,
- OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
- OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
OPC_MSA_3R_0D = 0x0D | OPC_MSA,
OPC_MSA_3R_0E = 0x0E | OPC_MSA,
OPC_MSA_3R_0F = 0x0F | OPC_MSA,
@@ -222,20 +223,6 @@ enum {
OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
-
- /* BIT instruction df(bits 22..16) = _B _H _W _D */
- OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
- OPC_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A,
- OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
- OPC_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A,
- OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
- OPC_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A,
- OPC_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09,
- OPC_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A,
- OPC_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09,
- OPC_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09,
- OPC_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
- OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
};
static const char msaregnames[][6] = {
@@ -257,6 +244,59 @@ static const char msaregnames[][6] = {
"w30.d0", "w30.d1", "w31.d0", "w31.d1",
};
+/* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */
+struct dfe {
+ int start;
+ int length;
+ uint32_t mask;
+};
+
+/*
+ * Extract immediate from df/{m,n} format (used by ELM & BIT instructions).
+ * Returns the immediate value, or -1 if the format does not match.
+ */
+static int msa_df_extract_val(DisasContext *ctx, int x, const struct dfe *s)
+{
+ for (unsigned i = 0; i < 4; i++) {
+ if (extract32(x, s->start, s->length) == s->mask) {
+ return extract32(x, 0, s->start);
+ }
+ }
+ return -1;
+}
+
+/*
+ * Extract DataField from df/{m,n} format (used by ELM & BIT instructions).
+ * Returns the DataField, or -1 if the format does not match.
+ */
+static int msa_df_extract_df(DisasContext *ctx, int x, const struct dfe *s)
+{
+ for (unsigned i = 0; i < 4; i++) {
+ if (extract32(x, s->start, s->length) == s->mask) {
+ return i;
+ }
+ }
+ return -1;
+}
+
+static const struct dfe df_bit[] = {
+ /* Table 3.28 BIT Instruction Format */
+ [DF_BYTE] = {3, 4, 0b1110},
+ [DF_HALF] = {4, 3, 0b110},
+ [DF_WORD] = {5, 2, 0b10},
+ [DF_DOUBLE] = {6, 1, 0b0}
+};
+
+static int msa_bit_m(DisasContext *ctx, int x)
+{
+ return msa_df_extract_val(ctx, x, df_bit);
+}
+
+static int msa_bit_df(DisasContext *ctx, int x)
+{
+ return msa_df_extract_df(ctx, x, df_bit);
+}
+
static TCGv_i64 msa_wr_d[64];
void msa_translate_init(void)
@@ -500,90 +540,35 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a)
return true;
}
-static void gen_msa_bit(DisasContext *ctx)
+static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a,
+ gen_helper_piiii *gen_msa_bit)
{
-#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
- uint32_t df = 0, m = 0;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 tdf;
- TCGv_i32 tm;
- TCGv_i32 twd;
- TCGv_i32 tws;
-
- if ((dfm & 0x40) == 0x00) {
- m = dfm & 0x3f;
- df = DF_DOUBLE;
- } else if ((dfm & 0x60) == 0x40) {
- m = dfm & 0x1f;
- df = DF_WORD;
- } else if ((dfm & 0x70) == 0x60) {
- m = dfm & 0x0f;
- df = DF_HALF;
- } else if ((dfm & 0x78) == 0x70) {
- m = dfm & 0x7;
- df = DF_BYTE;
- } else {
- gen_reserved_instruction(ctx);
- return;
+ if (a->df < 0) {
+ return false;
}
- tdf = tcg_const_i32(df);
- tm = tcg_const_i32(m);
- twd = tcg_const_i32(wd);
- tws = tcg_const_i32(ws);
+ gen_msa_bit(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->m));
- switch (MASK_MSA_BIT(ctx->opcode)) {
- case OPC_SLLI_df:
- gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRAI_df:
- gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRLI_df:
- gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BCLRI_df:
- gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BSETI_df:
- gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BNEGI_df:
- gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BINSLI_df:
- gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BINSRI_df:
- gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SAT_S_df:
- gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SAT_U_df:
- gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRARI_df:
- gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRLRI_df:
- gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(tdf);
- tcg_temp_free_i32(tm);
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
+ return true;
}
+TRANS_MSA(SLLI, trans_msa_bit, gen_helper_msa_slli_df);
+TRANS_MSA(SRAI, trans_msa_bit, gen_helper_msa_srai_df);
+TRANS_MSA(SRLI, trans_msa_bit, gen_helper_msa_srli_df);
+TRANS_MSA(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df);
+TRANS_MSA(BSETI, trans_msa_bit, gen_helper_msa_bseti_df);
+TRANS_MSA(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df);
+TRANS_MSA(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df);
+TRANS_MSA(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df);
+TRANS_MSA(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df);
+TRANS_MSA(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df);
+TRANS_MSA(SRARI, trans_msa_bit, gen_helper_msa_srari_df);
+TRANS_MSA(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df);
+
static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -2128,10 +2113,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_I8_02:
gen_msa_i8(ctx);
break;
- case OPC_MSA_BIT_09:
- case OPC_MSA_BIT_0A:
- gen_msa_bit(ctx);
- break;
case OPC_MSA_3R_0D:
case OPC_MSA_3R_0E:
case OPC_MSA_3R_0F:
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 11/32] target/mips: Convert MSA SHF opcode to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:21 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
` (21 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- add &msa_i8 format
- !check_msa_enabled -> return true
- TCG timm is constant
---
target/mips/tcg/msa.decode | 4 ++++
target/mips/tcg/msa_translate.c | 37 ++++++++++++++++++---------------
2 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index c4699b9d4b7..7a4d7549258 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -16,6 +16,7 @@
&msa_bz df wt sa
&msa_ldi df wd sa
&msa_i5 df wd ws sa
+&msa_i8 df wd ws sa
&msa_bit df wd ws m
%dfm_df 16:7 !function=msa_bit_df
@@ -26,6 +27,7 @@
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
+@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%dfm_df m=%dfm_m
@@ -38,6 +40,8 @@ BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
{
+ SHF 011110 .. ........ ..... ..... 000010 @i8_df
+
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 175254c1e47..76c40dc7126 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -60,13 +60,10 @@ enum {
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
- OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
- OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
- OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
/* VEC/2R/2RF instruction */
@@ -477,20 +474,6 @@ static void gen_msa_i8(DisasContext *ctx)
case OPC_BSELI_B:
gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
break;
- case OPC_SHF_B:
- case OPC_SHF_H:
- case OPC_SHF_W:
- {
- uint8_t df = (ctx->opcode >> 24) & 0x3;
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- } else {
- TCGv_i32 tdf = tcg_const_i32(df);
- gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
- tcg_temp_free_i32(tdf);
- }
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -502,6 +485,26 @@ static void gen_msa_i8(DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
+static bool trans_SHF(DisasContext *ctx, arg_msa_i8 *a)
+{
+ if (a->df == DF_DOUBLE) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_helper_msa_shf_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->sa));
+
+ return true;
+}
+
static bool trans_msa_i5(DisasContext *ctx, arg_msa_i5 *a,
gen_helper_piiii *gen_msa_i5)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:31 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
` (20 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert instructions with an 8-bit immediate value and either
implicit data format or data format df to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: TCG timm is constant
---
target/mips/tcg/msa.decode | 8 ++++
target/mips/tcg/msa_translate.c | 73 ++++++++-------------------------
2 files changed, 24 insertions(+), 57 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 7a4d7549258..af374f08969 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -28,6 +28,7 @@
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8
+@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_i8 df=0
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%dfm_df m=%dfm_m
@@ -40,6 +41,13 @@ BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
{
+ ANDI 011110 00 ........ ..... ..... 000000 @i8
+ ORI 011110 01 ........ ..... ..... 000000 @i8
+ NORI 011110 10 ........ ..... ..... 000000 @i8
+ XORI 011110 11 ........ ..... ..... 000000 @i8
+ BMNZI 011110 00 ........ ..... ..... 000001 @i8
+ BMZI 011110 01 ........ ..... ..... 000001 @i8
+ BSELI 011110 10 ........ ..... ..... 000001 @i8
SHF 011110 .. ........ ..... ..... 000010 @i8_df
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 76c40dc7126..d0b990a49f6 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,9 +27,6 @@ static int msa_bit_df(DisasContext *ctx, int x);
#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
enum {
- OPC_MSA_I8_00 = 0x00 | OPC_MSA,
- OPC_MSA_I8_01 = 0x01 | OPC_MSA,
- OPC_MSA_I8_02 = 0x02 | OPC_MSA,
OPC_MSA_3R_0D = 0x0D | OPC_MSA,
OPC_MSA_3R_0E = 0x0E | OPC_MSA,
OPC_MSA_3R_0F = 0x0F | OPC_MSA,
@@ -57,15 +54,6 @@ enum {
};
enum {
- /* I8 instruction */
- OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
- OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
- OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
- OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
- OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
- OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
- OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
-
/* VEC/2R/2RF instruction */
OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
@@ -334,6 +322,7 @@ static inline bool check_msa_enabled(DisasContext *ctx)
return true;
}
+typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
/*
@@ -441,50 +430,25 @@ static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
}
-static void gen_msa_i8(DisasContext *ctx)
+static bool trans_msa_i8(DisasContext *ctx, arg_msa_i8 *a,
+ gen_helper_piii *gen_msa_i8)
{
-#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
- uint8_t i8 = (ctx->opcode >> 16) & 0xff;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ gen_msa_i8(cpu_env,
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->sa));
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 ti8 = tcg_const_i32(i8);
-
- switch (MASK_MSA_I8(ctx->opcode)) {
- case OPC_ANDI_B:
- gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_ORI_B:
- gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_NORI_B:
- gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_XORI_B:
- gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BMNZI_B:
- gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BMZI_B:
- gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BSELI_B:
- gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(ti8);
+ return true;
}
+TRANS_MSA(ANDI, trans_msa_i8, gen_helper_msa_andi_b);
+TRANS_MSA(ORI, trans_msa_i8, gen_helper_msa_ori_b);
+TRANS_MSA(NORI, trans_msa_i8, gen_helper_msa_nori_b);
+TRANS_MSA(XORI, trans_msa_i8, gen_helper_msa_xori_b);
+TRANS_MSA(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b);
+TRANS_MSA(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b);
+TRANS_MSA(BSELI, trans_msa_i8, gen_helper_msa_bseli_b);
+
static bool trans_SHF(DisasContext *ctx, arg_msa_i8 *a)
{
if (a->df == DF_DOUBLE) {
@@ -2111,11 +2075,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
}
switch (MASK_MSA_MINOR(opcode)) {
- case OPC_MSA_I8_00:
- case OPC_MSA_I8_01:
- case OPC_MSA_I8_02:
- gen_msa_i8(ctx);
- break;
case OPC_MSA_3R_0D:
case OPC_MSA_3R_0E:
case OPC_MSA_3R_0F:
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 13/32] target/mips: Convert MSA load/store instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:42 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
` (19 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert load/store instructions to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Add TRANS_DF_x() and use an array of 4 functions (tip from Richard)
---
target/mips/tcg/msa.decode | 5 ++
target/mips/tcg/msa_translate.c | 86 +++++++++++----------------------
2 files changed, 32 insertions(+), 59 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index af374f08969..ca25d79bda4 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -17,12 +17,14 @@
&msa_ldi df wd sa
&msa_i5 df wd ws sa
&msa_i8 df wd ws sa
+&msa_ldst df wd ws sa
&msa_bit df wd ws m
%dfm_df 16:7 !function=msa_bit_df
%dfm_m 16:7 !function=msa_bit_m
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
+@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@@ -79,5 +81,8 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ LD 011110 .......... ..... ..... 1000 .. @ldst
+ ST 011110 .......... ..... ..... 1001 .. @ldst
+
MSA 011110 --------------------------
}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index d0b990a49f6..afb9124501e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -41,16 +41,6 @@ enum {
OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
OPC_MSA_VEC = 0x1E | OPC_MSA,
-
- /* MI10 instruction */
- OPC_LD_B = (0x20) | OPC_MSA,
- OPC_LD_H = (0x21) | OPC_MSA,
- OPC_LD_W = (0x22) | OPC_MSA,
- OPC_LD_D = (0x23) | OPC_MSA,
- OPC_ST_B = (0x24) | OPC_MSA,
- OPC_ST_H = (0x25) | OPC_MSA,
- OPC_ST_W = (0x26) | OPC_MSA,
- OPC_ST_D = (0x27) | OPC_MSA,
};
enum {
@@ -322,6 +312,7 @@ static inline bool check_msa_enabled(DisasContext *ctx)
return true;
}
+typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv);
typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
@@ -339,6 +330,15 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
return FUNC(ctx, a, __VA_ARGS__); \
}
+#define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \
+ static gen_helper_p##TYPE * const NAME##_tab[4] = { \
+ gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \
+ }; \
+ TRANS_MSA(NAME, trans_func, NAME##_tab[a->df])
+
+#define TRANS_DF_iv(NAME, trans_func, gen_func) \
+ TRANS_DF_x(iv, NAME, trans_func, gen_func)
+
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@@ -2097,55 +2097,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_VEC:
gen_msa_vec(ctx);
break;
- case OPC_LD_B:
- case OPC_LD_H:
- case OPC_LD_W:
- case OPC_LD_D:
- case OPC_ST_B:
- case OPC_ST_H:
- case OPC_ST_W:
- case OPC_ST_D:
- {
- int32_t s10 = sextract32(ctx->opcode, 16, 10);
- uint8_t rs = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 0) & 0x3;
-
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv taddr = tcg_temp_new();
- gen_base_offset_addr(ctx, taddr, rs, s10 << df);
-
- switch (MASK_MSA_MINOR(opcode)) {
- case OPC_LD_B:
- gen_helper_msa_ld_b(cpu_env, twd, taddr);
- break;
- case OPC_LD_H:
- gen_helper_msa_ld_h(cpu_env, twd, taddr);
- break;
- case OPC_LD_W:
- gen_helper_msa_ld_w(cpu_env, twd, taddr);
- break;
- case OPC_LD_D:
- gen_helper_msa_ld_d(cpu_env, twd, taddr);
- break;
- case OPC_ST_B:
- gen_helper_msa_st_b(cpu_env, twd, taddr);
- break;
- case OPC_ST_H:
- gen_helper_msa_st_h(cpu_env, twd, taddr);
- break;
- case OPC_ST_W:
- gen_helper_msa_st_w(cpu_env, twd, taddr);
- break;
- case OPC_ST_D:
- gen_helper_msa_st_d(cpu_env, twd, taddr);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free(taddr);
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -2155,6 +2106,23 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
return true;
}
+static bool trans_msa_ldst(DisasContext *ctx, arg_msa_ldst *a,
+ gen_helper_piv *gen_msa_ldst)
+{
+ TCGv taddr = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
+
+ gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr);
+
+ tcg_temp_free(taddr);
+
+ return true;
+}
+
+TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld);
+TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
+
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 14/32] target/mips: Convert MSA 2RF instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
` (18 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert 2-register floating-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 19 ++++++
target/mips/tcg/msa_translate.c | 111 +++++++-------------------------
2 files changed, 44 insertions(+), 86 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index ca25d79bda4..395a2cbafeb 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,6 +13,7 @@
&r rs rt rd sa
+&msa_r df wd ws wt
&msa_bz df wt sa
&msa_ldi df wd sa
&msa_i5 df wd ws sa
@@ -27,6 +28,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8
@@ -81,6 +83,23 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ FCLASS 011110 110010000 . ..... ..... 011110 @2rf
+ FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
+ FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
+ FSQRT 011110 110010011 . ..... ..... 011110 @2rf
+ FRSQRT 011110 110010100 . ..... ..... 011110 @2rf
+ FRCP 011110 110010101 . ..... ..... 011110 @2rf
+ FRINT 011110 110010110 . ..... ..... 011110 @2rf
+ FLOG2 011110 110010111 . ..... ..... 011110 @2rf
+ FEXUPL 011110 110011000 . ..... ..... 011110 @2rf
+ FEXUPR 011110 110011001 . ..... ..... 011110 @2rf
+ FFQL 011110 110011010 . ..... ..... 011110 @2rf
+ FFQR 011110 110011011 . ..... ..... 011110 @2rf
+ FTINT_S 011110 110011100 . ..... ..... 011110 @2rf
+ FTINT_U 011110 110011101 . ..... ..... 011110 @2rf
+ FFINT_S 011110 110011110 . ..... ..... 011110 @2rf
+ FFINT_U 011110 110011111 . ..... ..... 011110 @2rf
+
LD 011110 .......... ..... ..... 1000 .. @ldst
ST 011110 .......... ..... ..... 1001 .. @ldst
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index afb9124501e..a61ba9a4db8 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -44,7 +44,7 @@ enum {
};
enum {
- /* VEC/2R/2RF instruction */
+ /* VEC/2R instruction */
OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
@@ -54,7 +54,6 @@ enum {
OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
- OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
@@ -62,24 +61,6 @@ enum {
OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
- /* 2RF instruction df(bit 16) = _w, _d */
- OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
- OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF,
- OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF,
- OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
- OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF,
- OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF,
- OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF,
- OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF,
- OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
- OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
- OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF,
- OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF,
- OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF,
- OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF,
-
/* 3R instruction df(bits 22..21) = _b, _h, _w, d */
OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1931,73 +1912,34 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(tws);
}
-static void gen_msa_2rf(DisasContext *ctx)
+static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
+ gen_helper_piii *gen_msa_2rf)
{
-#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
- (op & (0xf << 17)))
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 16) & 0x1;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- /* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
+ gen_msa_2rf(cpu_env,
+ tcg_constant_i32(DF_WORD + a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws));
- switch (MASK_MSA_2RF(ctx->opcode)) {
- case OPC_FCLASS_df:
- gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_S_df:
- gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_U_df:
- gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FSQRT_df:
- gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRSQRT_df:
- gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRCP_df:
- gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRINT_df:
- gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FLOG2_df:
- gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPL_df:
- gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPR_df:
- gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQL_df:
- gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQR_df:
- gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_S_df:
- gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_U_df:
- gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_S_df:
- gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_U_df:
- gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
+ return true;
}
+TRANS_MSA(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS_MSA(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS_MSA(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df);
+TRANS_MSA(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df);
+TRANS_MSA(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df);
+TRANS_MSA(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df);
+TRANS_MSA(FRINT, trans_msa_2rf, gen_helper_msa_frint_df);
+TRANS_MSA(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df);
+TRANS_MSA(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df);
+TRANS_MSA(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df);
+TRANS_MSA(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df);
+TRANS_MSA(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df);
+TRANS_MSA(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df);
+TRANS_MSA(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);
+TRANS_MSA(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);
+TRANS_MSA(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);
+
static void gen_msa_vec_v(DisasContext *ctx)
{
#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
@@ -2056,9 +1998,6 @@ static void gen_msa_vec(DisasContext *ctx)
case OPC_MSA_2R:
gen_msa_2r(ctx);
break;
- case OPC_MSA_2RF:
- gen_msa_2rf(ctx);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 15/32] target/mips: Convert MSA FILL opcode to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:46 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
` (17 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- check TARGET_LONG_BITS != 64 before check_msa_access()
- !check_msa_access returns true
- Use tcg_constant_i32()
---
target/mips/tcg/msa.decode | 2 ++
target/mips/tcg/msa_translate.c | 32 ++++++++++++++++++++------------
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 395a2cbafeb..030ffa9321b 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -28,6 +28,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@@ -83,6 +84,7 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ FILL 011110 11000000 .. ..... ..... 011110 @2r
FCLASS 011110 110010000 . ..... ..... 011110 @2rf
FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index a61ba9a4db8..004eb0b7700 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -56,7 +56,6 @@ enum {
OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
- OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
@@ -1843,17 +1842,6 @@ static void gen_msa_2r(DisasContext *ctx)
TCGv_i32 tws = tcg_const_i32(ws);
switch (MASK_MSA_2R(ctx->opcode)) {
- case OPC_FILL_df:
-#if !defined(TARGET_MIPS64)
- /* Double format valid only for MIPS64 */
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- break;
- }
-#endif
- gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
- twd, tws); /* trs */
- break;
case OPC_NLOC_df:
switch (df) {
case DF_BYTE:
@@ -1912,6 +1900,26 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(tws);
}
+static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
+{
+ if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
+ /* Double format valid only for MIPS64 */
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_helper_msa_fill_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws));
+
+ return true;
+}
+
static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
gen_helper_piii *gen_msa_2rf)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:50 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
` (16 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert 2-register operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- TRANS_DF_ii() uses array[4]
---
target/mips/tcg/msa.decode | 3 ++
target/mips/tcg/msa_translate.c | 87 +++++----------------------------
2 files changed, 15 insertions(+), 75 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 030ffa9321b..a92763af451 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -85,6 +85,9 @@ BNZ 010001 111 .. ..... ................ @bz
SRLRI 011110 011 ....... ..... ..... 001010 @bit
FILL 011110 11000000 .. ..... ..... 011110 @2r
+ PCNT 011110 11000001 .. ..... ..... 011110 @2r
+ NLOC 011110 11000010 .. ..... ..... 011110 @2r
+ NLZC 011110 11000011 .. ..... ..... 011110 @2r
FCLASS 011110 110010000 . ..... ..... 011110 @2rf
FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 004eb0b7700..bff998356ac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -53,13 +53,6 @@ enum {
OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
- OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
-
- /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
- OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
- OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
- OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
-
/* 3R instruction df(bits 22..21) = _b, _h, _w, d */
OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -293,6 +286,7 @@ static inline bool check_msa_enabled(DisasContext *ctx)
}
typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv);
+typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
@@ -319,6 +313,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
#define TRANS_DF_iv(NAME, trans_func, gen_func) \
TRANS_DF_x(iv, NAME, trans_func, gen_func)
+#define TRANS_DF_ii(NAME, trans_func, gen_func) \
+ TRANS_DF_x(ii, NAME, trans_func, gen_func)
+
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@@ -1831,75 +1828,18 @@ static void gen_msa_3rf(DisasContext *ctx)
tcg_temp_free_i32(twt);
}
-static void gen_msa_2r(DisasContext *ctx)
+static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
+ gen_helper_pii *gen_msa_2r)
{
-#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
- (op & (0x7 << 18)))
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 16) & 0x3;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
+ gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
- switch (MASK_MSA_2R(ctx->opcode)) {
- case OPC_NLOC_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_nloc_b(cpu_env, twd, tws);
- break;
- case DF_HALF:
- gen_helper_msa_nloc_h(cpu_env, twd, tws);
- break;
- case DF_WORD:
- gen_helper_msa_nloc_w(cpu_env, twd, tws);
- break;
- case DF_DOUBLE:
- gen_helper_msa_nloc_d(cpu_env, twd, tws);
- break;
- }
- break;
- case OPC_NLZC_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_nlzc_b(cpu_env, twd, tws);
- break;
- case DF_HALF:
- gen_helper_msa_nlzc_h(cpu_env, twd, tws);
- break;
- case DF_WORD:
- gen_helper_msa_nlzc_w(cpu_env, twd, tws);
- break;
- case DF_DOUBLE:
- gen_helper_msa_nlzc_d(cpu_env, twd, tws);
- break;
- }
- break;
- case OPC_PCNT_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_pcnt_b(cpu_env, twd, tws);
- break;
- case DF_HALF:
- gen_helper_msa_pcnt_h(cpu_env, twd, tws);
- break;
- case DF_WORD:
- gen_helper_msa_pcnt_w(cpu_env, twd, tws);
- break;
- case DF_DOUBLE:
- gen_helper_msa_pcnt_d(cpu_env, twd, tws);
- break;
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
+ return true;
}
+TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt);
+TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc);
+TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc);
+
static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
{
if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
@@ -2003,9 +1943,6 @@ static void gen_msa_vec(DisasContext *ctx)
case OPC_BSEL_V:
gen_msa_vec_v(ctx);
break;
- case OPC_MSA_2R:
- gen_msa_2r(ctx);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 17/32] target/mips: Convert MSA VEC instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
` (15 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert 3-register instructions with implicit data formats
to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 8 ++++
target/mips/tcg/msa_translate.c | 84 ++++++---------------------------
2 files changed, 22 insertions(+), 70 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index a92763af451..c9cc1529c8e 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -28,6 +28,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@@ -84,6 +85,13 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ AND_V 011110 00000 ..... ..... ..... 011110 @vec
+ OR_V 011110 00001 ..... ..... ..... 011110 @vec
+ NOR_V 011110 00010 ..... ..... ..... 011110 @vec
+ XOR_V 011110 00011 ..... ..... ..... 011110 @vec
+ BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec
+ BMZ_V 011110 00101 ..... ..... ..... 011110 @vec
+ BSEL_V 011110 00110 ..... ..... ..... 011110 @vec
FILL 011110 11000000 .. ..... ..... 011110 @2r
PCNT 011110 11000001 .. ..... ..... 011110 @2r
NLOC 011110 11000010 .. ..... ..... 011110 @2r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index bff998356ac..c7168608d42 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -40,19 +40,9 @@ enum {
OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
- OPC_MSA_VEC = 0x1E | OPC_MSA,
};
enum {
- /* VEC/2R instruction */
- OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
- OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
- OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
- OPC_XOR_V = (0x03 << 21) | OPC_MSA_VEC,
- OPC_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC,
- OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
- OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
-
/* 3R instruction df(bits 22..21) = _b, _h, _w, d */
OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1888,67 +1878,24 @@ TRANS_MSA(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);
TRANS_MSA(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);
TRANS_MSA(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);
-static void gen_msa_vec_v(DisasContext *ctx)
+static bool trans_msa_vec(DisasContext *ctx, arg_msa_r *a,
+ gen_helper_piii *gen_msa_vec)
{
-#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
+ gen_msa_vec(cpu_env,
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->wt));
- switch (MASK_MSA_VEC(ctx->opcode)) {
- case OPC_AND_V:
- gen_helper_msa_and_v(cpu_env, twd, tws, twt);
- break;
- case OPC_OR_V:
- gen_helper_msa_or_v(cpu_env, twd, tws, twt);
- break;
- case OPC_NOR_V:
- gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
- break;
- case OPC_XOR_V:
- gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BMNZ_V:
- gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BMZ_V:
- gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BSEL_V:
- gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
+ return true;
}
-static void gen_msa_vec(DisasContext *ctx)
-{
- switch (MASK_MSA_VEC(ctx->opcode)) {
- case OPC_AND_V:
- case OPC_OR_V:
- case OPC_NOR_V:
- case OPC_XOR_V:
- case OPC_BMNZ_V:
- case OPC_BMZ_V:
- case OPC_BSEL_V:
- gen_msa_vec_v(ctx);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-}
+TRANS_MSA(AND_V, trans_msa_vec, gen_helper_msa_and_v);
+TRANS_MSA(OR_V, trans_msa_vec, gen_helper_msa_or_v);
+TRANS_MSA(NOR_V, trans_msa_vec, gen_helper_msa_nor_v);
+TRANS_MSA(XOR_V, trans_msa_vec, gen_helper_msa_xor_v);
+TRANS_MSA(BMNZ_V, trans_msa_vec, gen_helper_msa_bmnz_v);
+TRANS_MSA(BMZ_V, trans_msa_vec, gen_helper_msa_bmz_v);
+TRANS_MSA(BSEL_V, trans_msa_vec, gen_helper_msa_bsel_v);
static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
{
@@ -1978,9 +1925,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_3RF_1C:
gen_msa_3rf(ctx);
break;
- case OPC_MSA_VEC:
- gen_msa_vec(ctx);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:53 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
` (14 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert 3-register floating-point or fixed-point operations
to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 8 +++++
target/mips/tcg/msa_translate.c | 64 +++++++++++++--------------------
2 files changed, 33 insertions(+), 39 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index c9cc1529c8e..ace07f2f298 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -31,6 +31,7 @@
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
+@3rf ...... .... df:1 wt:5 ws:5 wd:5 ...... &msa_r
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i8
@@ -85,6 +86,13 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf
+ MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf
+ MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf
+ MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf
+ MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf
+ MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf
+
AND_V 011110 00000 ..... ..... ..... 011110 @vec
OR_V 011110 00001 ..... ..... ..... 011110 @vec
NOR_V 011110 00010 ..... ..... ..... 011110 @vec
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c7168608d42..4e0ad24543e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -133,12 +133,9 @@ enum {
OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
- OPC_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C,
OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
- OPC_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C,
OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
- OPC_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C,
OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
@@ -152,13 +149,10 @@ enum {
OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
- OPC_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
- OPC_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
- OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
};
@@ -1655,6 +1649,30 @@ static void gen_msa_elm(DisasContext *ctx)
gen_msa_elm_df(ctx, df, n);
}
+static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
+ enum CPUMIPSMSADataFormat df_base,
+ gen_helper_piiii *gen_msa_3rf)
+{
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_msa_3rf(cpu_env,
+ tcg_constant_i32(a->df + df_base),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->wt));
+
+ return true;
+}
+
+TRANS(MUL_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mul_q_df);
+TRANS(MADD_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_madd_q_df);
+TRANS(MSUB_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msub_q_df);
+TRANS(MULR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mulr_q_df);
+TRANS(MADDR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_maddr_q_df);
+TRANS(MSUBR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msubr_q_df);
+
static void gen_msa_3rf(DisasContext *ctx)
{
#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -1666,22 +1684,8 @@ static void gen_msa_3rf(DisasContext *ctx)
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twt = tcg_const_i32(wt);
- TCGv_i32 tdf;
-
/* adjust df value for floating-point instruction */
- switch (MASK_MSA_3RF(ctx->opcode)) {
- case OPC_MUL_Q_df:
- case OPC_MADD_Q_df:
- case OPC_MSUB_Q_df:
- case OPC_MULR_Q_df:
- case OPC_MADDR_Q_df:
- case OPC_MSUBR_Q_df:
- tdf = tcg_constant_i32(DF_HALF + df);
- break;
- default:
- tdf = tcg_constant_i32(DF_WORD + df);
- break;
- }
+ TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
switch (MASK_MSA_3RF(ctx->opcode)) {
case OPC_FCAF_df:
@@ -1723,24 +1727,15 @@ static void gen_msa_3rf(DisasContext *ctx)
case OPC_FMADD_df:
gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MUL_Q_df:
- gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FCULT_df:
gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FMSUB_df:
gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MADD_Q_df:
- gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FCLE_df:
gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MSUB_Q_df:
- gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FCULE_df:
gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -1780,27 +1775,18 @@ static void gen_msa_3rf(DisasContext *ctx)
case OPC_FMIN_df:
gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MULR_Q_df:
- gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FSULT_df:
gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FMIN_A_df:
gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MADDR_Q_df:
- gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FSLE_df:
gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FMAX_df:
gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MSUBR_Q_df:
- gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FSULE_df:
gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 21:54 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
` (13 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert 3-register floating-point or fixed-point operations
to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 37 ++++++
target/mips/tcg/msa_translate.c | 213 ++++++--------------------------
2 files changed, 74 insertions(+), 176 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index ace07f2f298..f88ae234cca 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -86,9 +86,46 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
+ FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
+ FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf
+ FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf
+ FCLT 011110 0100 . ..... ..... ..... 011010 @3rf
+ FCULT 011110 0101 . ..... ..... ..... 011010 @3rf
+ FCLE 011110 0110 . ..... ..... ..... 011010 @3rf
+ FCULE 011110 0111 . ..... ..... ..... 011010 @3rf
+ FSAF 011110 1000 . ..... ..... ..... 011010 @3rf
+ FSUN 011110 1001 . ..... ..... ..... 011010 @3rf
+ FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf
+ FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf
+ FSLT 011110 1100 . ..... ..... ..... 011010 @3rf
+ FSULT 011110 1101 . ..... ..... ..... 011010 @3rf
+ FSLE 011110 1110 . ..... ..... ..... 011010 @3rf
+ FSULE 011110 1111 . ..... ..... ..... 011010 @3rf
+
+ FADD 011110 0000 . ..... ..... ..... 011011 @3rf
+ FSUB 011110 0001 . ..... ..... ..... 011011 @3rf
+ FMUL 011110 0010 . ..... ..... ..... 011011 @3rf
+ FDIV 011110 0011 . ..... ..... ..... 011011 @3rf
+ FMADD 011110 0100 . ..... ..... ..... 011011 @3rf
+ FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf
+ FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf
+ FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf
+ FTQ 011110 1010 . ..... ..... ..... 011011 @3rf
+ FMIN 011110 1100 . ..... ..... ..... 011011 @3rf
+ FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf
+ FMAX 011110 1110 . ..... ..... ..... 011011 @3rf
+ FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf
+
+ FCOR 011110 0001 . ..... ..... ..... 011100 @3rf
+ FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf
+ FCNE 011110 0011 . ..... ..... ..... 011100 @3rf
MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf
MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf
MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf
+ FSOR 011110 1001 . ..... ..... ..... 011100 @3rf
+ FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf
+ FSNE 011110 1011 . ..... ..... ..... 011100 @3rf
MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf
MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf
MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 4e0ad24543e..f635b49c13c 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -37,9 +37,6 @@ enum {
OPC_MSA_3R_14 = 0x14 | OPC_MSA,
OPC_MSA_3R_15 = 0x15 | OPC_MSA,
OPC_MSA_ELM = 0x19 | OPC_MSA,
- OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
- OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
- OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
};
enum {
@@ -118,43 +115,6 @@ enum {
OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
-
- /* 3RF instruction _df(bit 21) = _w, _d */
- OPC_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A,
- OPC_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B,
- OPC_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A,
- OPC_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B,
- OPC_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C,
- OPC_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A,
- OPC_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B,
- OPC_FCUNE_df = (0x2 << 22) | OPC_MSA_3RF_1C,
- OPC_FCUEQ_df = (0x3 << 22) | OPC_MSA_3RF_1A,
- OPC_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B,
- OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
- OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
- OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
- OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
- OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
- OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
- OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
- OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
- OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
- OPC_FEXDO_df = (0x8 << 22) | OPC_MSA_3RF_1B,
- OPC_FSUN_df = (0x9 << 22) | OPC_MSA_3RF_1A,
- OPC_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C,
- OPC_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A,
- OPC_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B,
- OPC_FSUNE_df = (0xA << 22) | OPC_MSA_3RF_1C,
- OPC_FSUEQ_df = (0xB << 22) | OPC_MSA_3RF_1A,
- OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
- OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
- OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
- OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
- OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
- OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
- OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
- OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
- OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
};
static const char msaregnames[][6] = {
@@ -1666,144 +1626,50 @@ static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
return true;
}
+TRANS(FCAF, trans_msa_3rf, DF_WORD, gen_helper_msa_fcaf_df);
+TRANS(FCUN, trans_msa_3rf, DF_WORD, gen_helper_msa_fcun_df);
+TRANS(FCEQ, trans_msa_3rf, DF_WORD, gen_helper_msa_fceq_df);
+TRANS(FCUEQ, trans_msa_3rf, DF_WORD, gen_helper_msa_fcueq_df);
+TRANS(FCLT, trans_msa_3rf, DF_WORD, gen_helper_msa_fclt_df);
+TRANS(FCULT, trans_msa_3rf, DF_WORD, gen_helper_msa_fcult_df);
+TRANS(FCLE, trans_msa_3rf, DF_WORD, gen_helper_msa_fcle_df);
+TRANS(FCULE, trans_msa_3rf, DF_WORD, gen_helper_msa_fcule_df);
+TRANS(FSAF, trans_msa_3rf, DF_WORD, gen_helper_msa_fsaf_df);
+TRANS(FSUN, trans_msa_3rf, DF_WORD, gen_helper_msa_fsun_df);
+TRANS(FSEQ, trans_msa_3rf, DF_WORD, gen_helper_msa_fseq_df);
+TRANS(FSUEQ, trans_msa_3rf, DF_WORD, gen_helper_msa_fsueq_df);
+TRANS(FSLT, trans_msa_3rf, DF_WORD, gen_helper_msa_fslt_df);
+TRANS(FSULT, trans_msa_3rf, DF_WORD, gen_helper_msa_fsult_df);
+TRANS(FSLE, trans_msa_3rf, DF_WORD, gen_helper_msa_fsle_df);
+TRANS(FSULE, trans_msa_3rf, DF_WORD, gen_helper_msa_fsule_df);
+
+TRANS(FADD, trans_msa_3rf, DF_WORD, gen_helper_msa_fadd_df);
+TRANS(FSUB, trans_msa_3rf, DF_WORD, gen_helper_msa_fsub_df);
+TRANS(FMUL, trans_msa_3rf, DF_WORD, gen_helper_msa_fmul_df);
+TRANS(FDIV, trans_msa_3rf, DF_WORD, gen_helper_msa_fdiv_df);
+TRANS(FMADD, trans_msa_3rf, DF_WORD, gen_helper_msa_fmadd_df);
+TRANS(FMSUB, trans_msa_3rf, DF_WORD, gen_helper_msa_fmsub_df);
+TRANS(FEXP2, trans_msa_3rf, DF_WORD, gen_helper_msa_fexp2_df);
+TRANS(FEXDO, trans_msa_3rf, DF_WORD, gen_helper_msa_fexdo_df);
+TRANS(FTQ, trans_msa_3rf, DF_WORD, gen_helper_msa_ftq_df);
+TRANS(FMIN, trans_msa_3rf, DF_WORD, gen_helper_msa_fmin_df);
+TRANS(FMIN_A, trans_msa_3rf, DF_WORD, gen_helper_msa_fmin_a_df);
+TRANS(FMAX, trans_msa_3rf, DF_WORD, gen_helper_msa_fmax_df);
+TRANS(FMAX_A, trans_msa_3rf, DF_WORD, gen_helper_msa_fmax_a_df);
+
+TRANS(FCOR, trans_msa_3rf, DF_WORD, gen_helper_msa_fcor_df);
+TRANS(FCUNE, trans_msa_3rf, DF_WORD, gen_helper_msa_fcune_df);
+TRANS(FCNE, trans_msa_3rf, DF_WORD, gen_helper_msa_fcne_df);
TRANS(MUL_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mul_q_df);
TRANS(MADD_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_madd_q_df);
TRANS(MSUB_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msub_q_df);
+TRANS(FSOR, trans_msa_3rf, DF_WORD, gen_helper_msa_fsor_df);
+TRANS(FSUNE, trans_msa_3rf, DF_WORD, gen_helper_msa_fsune_df);
+TRANS(FSNE, trans_msa_3rf, DF_WORD, gen_helper_msa_fsne_df);
TRANS(MULR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mulr_q_df);
TRANS(MADDR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_maddr_q_df);
TRANS(MSUBR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msubr_q_df);
-static void gen_msa_3rf(DisasContext *ctx)
-{
-#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
- uint8_t df = (ctx->opcode >> 21) & 0x1;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
- /* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
-
- switch (MASK_MSA_3RF(ctx->opcode)) {
- case OPC_FCAF_df:
- gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FADD_df:
- gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCUN_df:
- gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUB_df:
- gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCOR_df:
- gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCEQ_df:
- gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMUL_df:
- gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCUNE_df:
- gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCUEQ_df:
- gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FDIV_df:
- gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCNE_df:
- gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCLT_df:
- gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMADD_df:
- gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCULT_df:
- gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMSUB_df:
- gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCLE_df:
- gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCULE_df:
- gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FEXP2_df:
- gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSAF_df:
- gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FEXDO_df:
- gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUN_df:
- gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSOR_df:
- gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSEQ_df:
- gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FTQ_df:
- gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUNE_df:
- gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUEQ_df:
- gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSNE_df:
- gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSLT_df:
- gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMIN_df:
- gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSULT_df:
- gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMIN_A_df:
- gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSLE_df:
- gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMAX_df:
- gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSULE_df:
- gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMAX_A_df:
- gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
-}
-
static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
gen_helper_pii *gen_msa_2r)
{
@@ -1906,11 +1772,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_ELM:
gen_msa_elm(ctx);
break;
- case OPC_MSA_3RF_1A:
- case OPC_MSA_3RF_1B:
- case OPC_MSA_3RF_1C:
- gen_msa_3rf(ctx);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
` (12 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert 3-register operations to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 6 ++++++
target/mips/tcg/msa_translate.c | 29 +++++++++++++++++------------
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index f88ae234cca..7201b821ae0 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -31,6 +31,7 @@
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
+@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
@3rf ...... .... df:1 wt:5 ws:5 wd:5 ...... &msa_r
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@@ -86,6 +87,11 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ SLD 011110 000 .. ..... ..... ..... 010100 @3r
+ SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
+
+ VSHF 011110 000 .. ..... ..... ..... 010101 @3r
+
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index f635b49c13c..c7ca629d684 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -48,15 +48,12 @@ enum {
OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
- OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
- OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
- OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -457,6 +454,23 @@ TRANS_MSA(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df);
TRANS_MSA(SRARI, trans_msa_bit, gen_helper_msa_srari_df);
TRANS_MSA(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df);
+static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
+ gen_helper_piiii *gen_msa_3r_df)
+{
+ gen_msa_3r_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->wt));
+
+ return true;
+}
+
+TRANS_MSA(SLD, trans_msa_3r_df, gen_helper_msa_sld_df);
+TRANS_MSA(SPLAT, trans_msa_3r_df, gen_helper_msa_splat_df);
+
+TRANS_MSA(VSHF, trans_msa_3r_df, gen_helper_msa_vshf_df);
+
static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -1207,12 +1221,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SLD_df:
- gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_VSHF_df:
- gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBV_df:
switch (df) {
case DF_BYTE:
@@ -1245,9 +1253,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SPLAT_df:
- gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUS_U_df:
switch (df) {
case DF_BYTE:
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 22:02 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
` (11 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert 3-register operations to decodetree.
Per the Encoding of Operation Field for 3R Instruction Format'
(Table 3.25), these instructions are not defined for the BYTE
format. Therefore the TRANS_DF_iii_b() macro returns 'false'
in that case, because no such instruction is decoded.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: TRANS_DF_iii_b() uses array[4]
---
target/mips/tcg/msa.decode | 11 ++
target/mips/tcg/msa_translate.c | 195 ++++++--------------------------
2 files changed, 48 insertions(+), 158 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 7201b821ae0..f6471b92fc7 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -87,10 +87,21 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
+ DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
+ DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
+ DPADD_U 011110 011.. ..... ..... ..... 010011 @3r
+ DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r
+ DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r
+
SLD 011110 000 .. ..... ..... ..... 010100 @3r
SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
VSHF 011110 000 .. ..... ..... ..... 010101 @3r
+ HADD_S 011110 100.. ..... ..... ..... 010101 @3r
+ HADD_U 011110 101.. ..... ..... ..... 010101 @3r
+ HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
+ HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c7ca629d684..5cc704c9ace 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -47,13 +47,11 @@ enum {
OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
- OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
- OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -61,7 +59,6 @@ enum {
OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
- OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
@@ -69,7 +66,6 @@ enum {
OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
- OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
@@ -77,30 +73,24 @@ enum {
OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
- OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
- OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
- OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
- OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
- OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
- OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
@@ -257,6 +247,21 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
#define TRANS_DF_ii(NAME, trans_func, gen_func) \
TRANS_DF_x(ii, NAME, trans_func, gen_func)
+#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
+ static gen_helper_piii * const NAME##_tab[4] = { \
+ gen_func##_h, gen_func##_w, gen_func##_d \
+ }; \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { \
+ if (a->df == DF_BYTE) { \
+ return false; \
+ } \
+ if (!check_msa_enabled(ctx)) { \
+ return true; \
+ } \
+ return trans_func(ctx, a, NAME##_tab[a->df - DF_HALF]); \
+ }
+
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@@ -466,10 +471,32 @@ static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
return true;
}
+static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
+ gen_helper_piii *gen_msa_3r)
+{
+ gen_msa_3r(cpu_env,
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->wt));
+
+ return true;
+}
+
+TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s);
+TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u);
+TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s);
+TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u);
+TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s);
+TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u);
+
TRANS_MSA(SLD, trans_msa_3r_df, gen_helper_msa_sld_df);
TRANS_MSA(SPLAT, trans_msa_3r_df, gen_helper_msa_splat_df);
TRANS_MSA(VSHF, trans_msa_3r_df, gen_helper_msa_vshf_df);
+TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s);
+TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u);
+TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s);
+TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u);
static void gen_msa_3r(DisasContext *ctx)
{
@@ -1285,154 +1312,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
-
- case OPC_DOTP_S_df:
- case OPC_DOTP_U_df:
- case OPC_DPADD_S_df:
- case OPC_DPADD_U_df:
- case OPC_DPSUB_S_df:
- case OPC_HADD_S_df:
- case OPC_DPSUB_U_df:
- case OPC_HADD_U_df:
- case OPC_HSUB_S_df:
- case OPC_HSUB_U_df:
- if (df == DF_BYTE) {
- gen_reserved_instruction(ctx);
- break;
- }
- switch (MASK_MSA_3R(ctx->opcode)) {
- case OPC_HADD_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_HADD_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_HSUB_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_HSUB_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DOTP_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DOTP_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPADD_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPADD_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPSUB_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPSUB_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- }
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
` (10 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 3 +++
target/mips/tcg/msa_translate.c | 40 +++++----------------------------
2 files changed, 9 insertions(+), 34 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index f6471b92fc7..19458f180f5 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -87,6 +87,9 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ BINSL 011110 110.. ..... ..... ..... 001101 @3r
+ BINSR 011110 111.. ..... ..... ..... 001101 @3r
+
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5cc704c9ace..a5a5cc4bcac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -81,12 +81,10 @@ enum {
OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
- OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
- OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
@@ -247,6 +245,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
#define TRANS_DF_ii(NAME, trans_func, gen_func) \
TRANS_DF_x(ii, NAME, trans_func, gen_func)
+#define TRANS_DF_iii(NAME, trans_func, gen_func) \
+ TRANS_DF_x(iii, NAME, trans_func, gen_func)
+
#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
static gen_helper_piii * const NAME##_tab[4] = { \
gen_func##_h, gen_func##_w, gen_func##_d \
@@ -482,6 +483,9 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
return true;
}
+TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl);
+TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr);
+
TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s);
TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u);
TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s);
@@ -512,38 +516,6 @@ static void gen_msa_3r(DisasContext *ctx)
TCGv_i32 twt = tcg_const_i32(wt);
switch (MASK_MSA_3R(ctx->opcode)) {
- case OPC_BINSL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BINSR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
case OPC_BCLR_df:
switch (df) {
case DF_BYTE:
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (21 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
` (9 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert 3-register operations to decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 53 ++
target/mips/tcg/msa_translate.c | 916 ++------------------------------
2 files changed, 106 insertions(+), 863 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 19458f180f5..985af71889e 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -87,9 +87,54 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ SLL 011110 000.. ..... ..... ..... 001101 @3r
+ SRA 011110 001.. ..... ..... ..... 001101 @3r
+ SRL 011110 010.. ..... ..... ..... 001101 @3r
+ BCLR 011110 011.. ..... ..... ..... 001101 @3r
+ BSET 011110 100.. ..... ..... ..... 001101 @3r
+ BNEG 011110 101.. ..... ..... ..... 001101 @3r
BINSL 011110 110.. ..... ..... ..... 001101 @3r
BINSR 011110 111.. ..... ..... ..... 001101 @3r
+ ADDV 011110 000.. ..... ..... ..... 001110 @3r
+ SUBV 011110 001.. ..... ..... ..... 001110 @3r
+ MAX_S 011110 010.. ..... ..... ..... 001110 @3r
+ MAX_U 011110 011.. ..... ..... ..... 001110 @3r
+ MIN_S 011110 100.. ..... ..... ..... 001110 @3r
+ MIN_U 011110 101.. ..... ..... ..... 001110 @3r
+ MAX_A 011110 110.. ..... ..... ..... 001110 @3r
+ MIN_A 011110 111.. ..... ..... ..... 001110 @3r
+
+ CEQ 011110 000.. ..... ..... ..... 001111 @3r
+ CLT_S 011110 010.. ..... ..... ..... 001111 @3r
+ CLT_U 011110 011.. ..... ..... ..... 001111 @3r
+ CLE_S 011110 100.. ..... ..... ..... 001111 @3r
+ CLE_U 011110 101.. ..... ..... ..... 001111 @3r
+
+ ADD_A 011110 000.. ..... ..... ..... 010000 @3r
+ ADDS_A 011110 001.. ..... ..... ..... 010000 @3r
+ ADDS_S 011110 010.. ..... ..... ..... 010000 @3r
+ ADDS_U 011110 011.. ..... ..... ..... 010000 @3r
+ AVE_S 011110 100.. ..... ..... ..... 010000 @3r
+ AVE_U 011110 101.. ..... ..... ..... 010000 @3r
+ AVER_S 011110 110.. ..... ..... ..... 010000 @3r
+ AVER_U 011110 111.. ..... ..... ..... 010000 @3r
+
+ SUBS_S 011110 000.. ..... ..... ..... 010001 @3r
+ SUBS_U 011110 001.. ..... ..... ..... 010001 @3r
+ SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r
+ SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r
+ ASUB_S 011110 100.. ..... ..... ..... 010001 @3r
+ ASUB_U 011110 101.. ..... ..... ..... 010001 @3r
+
+ MULV 011110 000.. ..... ..... ..... 010010 @3r
+ MADDV 011110 001.. ..... ..... ..... 010010 @3r
+ MSUBV 011110 010.. ..... ..... ..... 010010 @3r
+ DIV_S 011110 100.. ..... ..... ..... 010010 @3r
+ DIV_U 011110 101.. ..... ..... ..... 010010 @3r
+ MOD_S 011110 110.. ..... ..... ..... 010010 @3r
+ MOD_U 011110 111.. ..... ..... ..... 010010 @3r
+
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
@@ -99,8 +144,16 @@ BNZ 010001 111 .. ..... ................ @bz
SLD 011110 000 .. ..... ..... ..... 010100 @3r
SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
+ PCKEV 011110 010 .. ..... ..... ..... 010100 @3r
+ PCKOD 011110 011 .. ..... ..... ..... 010100 @3r
+ ILVL 011110 100 .. ..... ..... ..... 010100 @3r
+ ILVR 011110 101 .. ..... ..... ..... 010100 @3r
+ ILVEV 011110 110 .. ..... ..... ..... 010100 @3r
+ ILVOD 011110 111 .. ..... ..... ..... 010100 @3r
VSHF 011110 000 .. ..... ..... ..... 010101 @3r
+ SRAR 011110 001 .. ..... ..... ..... 010101 @3r
+ SRLR 011110 010 .. ..... ..... ..... 010101 @3r
HADD_S 011110 100.. ..... ..... ..... 010101 @3r
HADD_U 011110 101.. ..... ..... ..... 010101 @3r
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index a5a5cc4bcac..d846f72c72b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,69 +27,10 @@ static int msa_bit_df(DisasContext *ctx, int x);
#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
enum {
- OPC_MSA_3R_0D = 0x0D | OPC_MSA,
- OPC_MSA_3R_0E = 0x0E | OPC_MSA,
- OPC_MSA_3R_0F = 0x0F | OPC_MSA,
- OPC_MSA_3R_10 = 0x10 | OPC_MSA,
- OPC_MSA_3R_11 = 0x11 | OPC_MSA,
- OPC_MSA_3R_12 = 0x12 | OPC_MSA,
- OPC_MSA_3R_13 = 0x13 | OPC_MSA,
- OPC_MSA_3R_14 = 0x14 | OPC_MSA,
- OPC_MSA_3R_15 = 0x15 | OPC_MSA,
OPC_MSA_ELM = 0x19 | OPC_MSA,
};
enum {
- /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
- OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
- OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
- OPC_CEQ_df = (0x0 << 23) | OPC_MSA_3R_0F,
- OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
- OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
- OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
- OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
- OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
- OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
- OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
- OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
- OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
- OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
- OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
- OPC_CLT_S_df = (0x2 << 23) | OPC_MSA_3R_0F,
- OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
- OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
- OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
- OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
- OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
- OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
- OPC_MAX_U_df = (0x3 << 23) | OPC_MSA_3R_0E,
- OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
- OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
- OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
- OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
- OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
- OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
- OPC_CLE_S_df = (0x4 << 23) | OPC_MSA_3R_0F,
- OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
- OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
- OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
- OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
- OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
- OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
- OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
- OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
- OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
- OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
- OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
- OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
- OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
- OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
- OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
- OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
- OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
- OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
- OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
-
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
@@ -483,9 +424,54 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
return true;
}
+TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll);
+TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra);
+TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl);
+TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr);
+TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset);
+TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg);
TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl);
TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr);
+TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv);
+TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv);
+TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s);
+TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u);
+TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s);
+TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u);
+TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a);
+TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a);
+
+TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq);
+TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s);
+TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u);
+TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s);
+TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u);
+
+TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a);
+TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a);
+TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s);
+TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u);
+TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s);
+TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u);
+TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s);
+TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u);
+
+TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s);
+TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u);
+TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u);
+TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s);
+TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s);
+TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u);
+
+TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv);
+TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv);
+TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv);
+TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s);
+TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u);
+TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s);
+TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u);
+
TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s);
TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u);
TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s);
@@ -495,806 +481,21 @@ TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u);
TRANS_MSA(SLD, trans_msa_3r_df, gen_helper_msa_sld_df);
TRANS_MSA(SPLAT, trans_msa_3r_df, gen_helper_msa_splat_df);
+TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev);
+TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod);
+TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl);
+TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr);
+TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev);
+TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod);
TRANS_MSA(VSHF, trans_msa_3r_df, gen_helper_msa_vshf_df);
+TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar);
+TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr);
TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s);
TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u);
TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s);
TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u);
-static void gen_msa_3r(DisasContext *ctx)
-{
-#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 tdf = tcg_const_i32(df);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
-
- switch (MASK_MSA_3R(ctx->opcode)) {
- case OPC_BCLR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_bclr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_bclr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_bclr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_bclr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BNEG_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_bneg_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_bneg_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_bneg_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_bneg_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BSET_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_bset_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_bset_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_bset_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_bset_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADD_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_add_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_add_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_add_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_add_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDS_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDS_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDS_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_addv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_addv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_addv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_addv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVE_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVE_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVER_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVER_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CEQ_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ceq_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ceq_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ceq_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ceq_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLE_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLE_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLT_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLT_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DIV_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_div_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_div_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_div_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_div_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DIV_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_div_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_div_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_div_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_div_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MAX_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MAX_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_max_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_max_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_max_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_max_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MAX_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_max_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_max_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_max_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_max_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MIN_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MIN_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_min_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_min_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_min_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_min_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MIN_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_min_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_min_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_min_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_min_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MOD_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MOD_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MADDV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MSUBV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ASUB_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ASUB_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVEV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVOD_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_PCKEV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_pckev_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_pckev_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_pckev_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_pckev_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_PCKOD_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_pckod_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_pckod_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_pckod_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_pckod_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SLL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_sll_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_sll_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_sll_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_sll_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRA_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_sra_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_sra_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_sra_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_sra_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRAR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_srar_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_srar_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_srar_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_srar_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_srl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_srl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_srl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_srl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRLR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_srlr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_srlr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_srlr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_srlr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBS_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MULV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_mulv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_mulv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_mulv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_mulv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBS_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBSUS_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBSUU_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
- tcg_temp_free_i32(tdf);
-}
-
static void gen_msa_elm_3e(DisasContext *ctx)
{
#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -1614,17 +815,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
}
switch (MASK_MSA_MINOR(opcode)) {
- case OPC_MSA_3R_0D:
- case OPC_MSA_3R_0E:
- case OPC_MSA_3R_0F:
- case OPC_MSA_3R_10:
- case OPC_MSA_3R_11:
- case OPC_MSA_3R_12:
- case OPC_MSA_3R_13:
- case OPC_MSA_3R_14:
- case OPC_MSA_3R_15:
- gen_msa_3r(ctx);
- break;
case OPC_MSA_ELM:
gen_msa_elm(ctx);
break;
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (22 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 22:05 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
` (8 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert instructions with an immediate element index
and data format df/n to decodetree.
Since the 'data format' and 'n' fields are constant values,
use tcg_constant_i32() instead of a TCG temporaries.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Return 'false' (not decoded) for invalid DF values (Richard)
---
target/mips/tcg/msa.decode | 8 +++++
target/mips/tcg/msa_translate.c | 53 +++++++++++++++++++++++++--------
2 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 985af71889e..e701e507bfc 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -20,7 +20,10 @@
&msa_i8 df wd ws sa
&msa_ldst df wd ws sa
&msa_bit df wd ws m
+&msa_elm_df df wd ws n
+%dfn_df 16:6 !function=msa_elm_df
+%dfn_n 16:6 !function=msa_elm_n
%dfm_df 16:7 !function=msa_bit_df
%dfm_m 16:7 !function=msa_bit_m
@@ -28,6 +31,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%dfn_df n=%dfn_n
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@@ -159,6 +163,10 @@ BNZ 010001 111 .. ..... ................ @bz
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
+ SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
+ SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
+
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index d846f72c72b..fabc7f5538b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -17,6 +17,8 @@
#include "fpu_helper.h"
#include "internal.h"
+static int msa_elm_n(DisasContext *ctx, int x);
+static int msa_elm_df(DisasContext *ctx, int x);
static int msa_bit_m(DisasContext *ctx, int x);
static int msa_bit_df(DisasContext *ctx, int x);
@@ -32,15 +34,12 @@ enum {
enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
- OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
- OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -97,6 +96,24 @@ static int msa_df_extract_df(DisasContext *ctx, int x, const struct dfe *s)
return -1;
}
+static const struct dfe df_elm[] = {
+ /* Table 3.26 ELM Instruction Format */
+ [DF_BYTE] = {4, 2, 0b00},
+ [DF_HALF] = {3, 3, 0b100},
+ [DF_WORD] = {2, 4, 0b1100},
+ [DF_DOUBLE] = {1, 5, 0b11100}
+};
+
+static int msa_elm_n(DisasContext *ctx, int x)
+{
+ return msa_df_extract_val(ctx, x, df_elm);
+}
+
+static int msa_elm_df(DisasContext *ctx, int x)
+{
+ return msa_df_extract_df(ctx, x, df_elm);
+}
+
static const struct dfe df_bit[] = {
/* Table 3.28 BIT Instruction Format */
[DF_BYTE] = {3, 4, 0b1110},
@@ -528,6 +545,26 @@ static void gen_msa_elm_3e(DisasContext *ctx)
tcg_temp_free_i32(tsr);
}
+static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm_df *a,
+ gen_helper_piiii *gen_msa_elm_df)
+{
+ if (a->df < 0) {
+ return false;
+ }
+
+ gen_msa_elm_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->n));
+
+ return true;
+}
+
+TRANS_MSA(SLDI, trans_msa_elm_df, gen_helper_msa_sldi_df);
+TRANS_MSA(SPLATI, trans_msa_elm_df, gen_helper_msa_splati_df);
+TRANS_MSA(INSVE, trans_msa_elm_df, gen_helper_msa_insve_df);
+
static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -537,18 +574,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tn = tcg_const_i32(n);
- TCGv_i32 tdf = tcg_constant_i32(df);
switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_SLDI_df:
- gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
- break;
- case OPC_SPLATI_df:
- gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
- break;
- case OPC_INSVE_df:
- gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
- break;
case OPC_COPY_S_df:
case OPC_COPY_U_df:
case OPC_INSERT_df:
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (23 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 22:08 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
` (7 subsequent siblings)
32 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Aurelien Jarno
Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
decodetree.
Since the 'n' field is a constant value, use tcg_constant_i32()
instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Add NULL_IF_TARGET_MIPS32() macro, use array of 4 functions
---
target/mips/tcg/msa.decode | 1 +
target/mips/tcg/msa_translate.c | 66 ++++++++++++++++++++-------------
2 files changed, 41 insertions(+), 26 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index e701e507bfc..4e1d3caadc5 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -165,6 +165,7 @@ BNZ 010001 111 .. ..... ................ @bz
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index fabc7f5538b..a2d7bbe912f 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -38,7 +38,6 @@ enum {
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
@@ -565,6 +564,46 @@ TRANS_MSA(SLDI, trans_msa_elm_df, gen_helper_msa_sldi_df);
TRANS_MSA(SPLATI, trans_msa_elm_df, gen_helper_msa_splati_df);
TRANS_MSA(INSVE, trans_msa_elm_df, gen_helper_msa_insve_df);
+static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm_df *a,
+ gen_helper_piii * const gen_msa[4])
+{
+ if (a->df < 0 || !gen_msa[a->df]) {
+ return false;
+ }
+
+ if (check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ if (a->wd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ gen_msa[a->df](cpu_env,
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->n));
+
+ return true;
+}
+
+#if defined(TARGET_MIPS64)
+#define NULL_IF_TARGET_MIPS32(function) function
+#else
+#define NULL_IF_TARGET_MIPS32(function) NULL
+#endif
+
+static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
+{
+ static gen_helper_piii * const gen_msa_copy_u[4] = {
+ gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h,
+ NULL_IF_TARGET_MIPS32(gen_helper_msa_copy_u_w), NULL
+ };
+
+ return trans_msa_elm_d64(ctx, a, gen_msa_copy_u);
+}
+
static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -577,7 +616,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
- case OPC_COPY_U_df:
case OPC_INSERT_df:
#if !defined(TARGET_MIPS64)
/* Double format valid only for MIPS64 */
@@ -585,11 +623,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
gen_reserved_instruction(ctx);
break;
}
- if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
- (df == DF_WORD)) {
- gen_reserved_instruction(ctx);
- break;
- }
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
@@ -608,25 +641,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
case DF_DOUBLE:
gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
break;
-#endif
- default:
- assert(0);
- }
- }
- break;
- case OPC_COPY_U_df:
- if (likely(wd != 0)) {
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_WORD:
- gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
- break;
#endif
default:
assert(0);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (24 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
` (6 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 2 +
target/mips/tcg/msa_translate.c | 103 +++++---------------------------
2 files changed, 18 insertions(+), 87 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 4e1d3caadc5..7c309526444 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -165,7 +165,9 @@ BNZ 010001 111 .. ..... ................ @bz
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
+ INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index a2d7bbe912f..2ed637f16da 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -36,9 +36,7 @@ enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -604,98 +602,31 @@ static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
return trans_msa_elm_d64(ctx, a, gen_msa_copy_u);
}
-static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
+static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a)
{
-#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ static gen_helper_piii * const gen_msa_copy_s[4] = {
+ gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h,
+ gen_helper_msa_copy_s_w, NULL_IF_TARGET_MIPS32(gen_helper_msa_copy_s_d)
+ };
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tn = tcg_const_i32(n);
+ return trans_msa_elm_d64(ctx, a, gen_msa_copy_s);
+}
- switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_COPY_S_df:
- case OPC_INSERT_df:
-#if !defined(TARGET_MIPS64)
- /* Double format valid only for MIPS64 */
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- break;
- }
-#endif
- switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_COPY_S_df:
- if (likely(wd != 0)) {
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
- break;
- case DF_WORD:
- gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_DOUBLE:
- gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
- break;
-#endif
- default:
- assert(0);
- }
- }
- break;
- case OPC_INSERT_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
- break;
- case DF_WORD:
- gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_DOUBLE:
- gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
- break;
-#endif
- default:
- assert(0);
- }
- break;
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- }
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(tn);
+static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a)
+{
+ static gen_helper_piii * const gen_msa_insert[4] = {
+ gen_helper_msa_insert_b, gen_helper_msa_insert_h,
+ gen_helper_msa_insert_w, NULL_IF_TARGET_MIPS32(gen_helper_msa_insert_d)
+ };
+
+ return trans_msa_elm_d64(ctx, a, gen_msa_insert);
}
static void gen_msa_elm(DisasContext *ctx)
{
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
- uint32_t df = 0, n = 0;
- if ((dfn & 0x30) == 0x00) {
- n = dfn & 0x0f;
- df = DF_BYTE;
- } else if ((dfn & 0x38) == 0x20) {
- n = dfn & 0x07;
- df = DF_HALF;
- } else if ((dfn & 0x3c) == 0x30) {
- n = dfn & 0x03;
- df = DF_WORD;
- } else if ((dfn & 0x3e) == 0x38) {
- n = dfn & 0x01;
- df = DF_DOUBLE;
- } else if (dfn == 0x3E) {
+ if (dfn == 0x3E) {
/* CTCMSA, CFCMSA, MOVE.V */
gen_msa_elm_3e(ctx);
return;
@@ -703,8 +634,6 @@ static void gen_msa_elm(DisasContext *ctx)
gen_reserved_instruction(ctx);
return;
}
-
- gen_msa_elm_df(ctx, df, n);
}
static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (25 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
` (5 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert the MOVE.V opcode (Vector Move) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 7 ++++++-
target/mips/tcg/msa_translate.c | 19 ++++++++++++++-----
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 7c309526444..cfa5fa5d688 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
&msa_ldst df wd ws sa
&msa_bit df wd ws m
&msa_elm_df df wd ws n
+&msa_elm wd ws
%dfn_df 16:6 !function=msa_elm_df
%dfn_n 16:6 !function=msa_elm_n
@@ -32,6 +33,7 @@
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%dfn_df n=%dfn_n
+@elm ...... .......... ws:5 wd:5 ...... &msa_elm
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@@ -165,7 +167,10 @@ BNZ 010001 111 .. ..... ................ @bz
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
- COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
+ {
+ MOVE_V 011110 0010111110 ..... ..... 011001 @elm
+ COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
+ }
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 2ed637f16da..0655b61801b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -36,7 +36,6 @@ enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -510,6 +509,19 @@ TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u);
TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s);
TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u);
+static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
+{
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_helper_msa_move_v(cpu_env,
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws));
+
+ return true;
+}
+
static void gen_msa_elm_3e(DisasContext *ctx)
{
#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -528,9 +540,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
gen_store_gpr(telm, dest);
break;
- case OPC_MOVE_V:
- gen_helper_msa_move_v(cpu_env, tdt, tsr);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -627,7 +636,7 @@ static void gen_msa_elm(DisasContext *ctx)
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
if (dfn == 0x3E) {
- /* CTCMSA, CFCMSA, MOVE.V */
+ /* CTCMSA, CFCMSA */
gen_msa_elm_3e(ctx);
return;
} else {
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 28/32] target/mips: Convert CFCMSA opcode to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (26 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
` (4 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert the CFCMSA (Copy From Control MSA register) opcode
to decodetree. Since it overlaps with the SPLATI opcode,
use a decodetree overlap group.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 5 ++++-
target/mips/tcg/msa_translate.c | 27 +++++++++++++++++++--------
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index cfa5fa5d688..12358e7a6ba 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -166,7 +166,10 @@ BNZ 010001 111 .. ..... ................ @bz
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
- SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ {
+ CFCMSA 011110 0001111110 ..... ..... 011001 @elm
+ SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ }
{
MOVE_V 011110 0010111110 ..... ..... 011001 @elm
COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 0655b61801b..56db02f73e7 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -35,7 +35,6 @@ enum {
enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -528,7 +527,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
uint8_t source = (ctx->opcode >> 11) & 0x1f;
uint8_t dest = (ctx->opcode >> 6) & 0x1f;
TCGv telm = tcg_temp_new();
- TCGv_i32 tsr = tcg_const_i32(source);
TCGv_i32 tdt = tcg_const_i32(dest);
switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
@@ -536,10 +534,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
gen_load_gpr(telm, source);
gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
break;
- case OPC_CFCMSA:
- gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
- gen_store_gpr(telm, dest);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -548,7 +542,24 @@ static void gen_msa_elm_3e(DisasContext *ctx)
tcg_temp_free(telm);
tcg_temp_free_i32(tdt);
- tcg_temp_free_i32(tsr);
+}
+
+static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
+{
+ TCGv telm;
+
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ telm = tcg_temp_new();
+
+ gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
+ gen_store_gpr(telm, a->wd);
+
+ tcg_temp_free(telm);
+
+ return true;
}
static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm_df *a,
@@ -636,7 +647,7 @@ static void gen_msa_elm(DisasContext *ctx)
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
if (dfn == 0x3E) {
- /* CTCMSA, CFCMSA */
+ /* CTCMSA */
gen_msa_elm_3e(ctx);
return;
} else {
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 29/32] target/mips: Convert CTCMSA opcode to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (27 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
` (3 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Convert the CTCMSA (Copy To Control MSA register) opcode
to decodetree. Since it overlaps with the SLDI opcode,
use a decodetree overlap group.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 5 ++-
target/mips/tcg/msa_translate.c | 69 ++++++---------------------------
2 files changed, 16 insertions(+), 58 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 12358e7a6ba..f3ec195bac0 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -165,7 +165,10 @@ BNZ 010001 111 .. ..... ................ @bz
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
- SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
+ {
+ CTCMSA 011110 0000111110 ..... ..... 011001 @elm
+ SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
+ }
{
CFCMSA 011110 0001111110 ..... ..... 011001 @elm
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 56db02f73e7..4a2a02bd6d2 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -25,18 +25,6 @@ static int msa_bit_df(DisasContext *ctx, int x);
/* Include the auto-generated decoder. */
#include "decode-msa.c.inc"
-#define OPC_MSA (0x1E << 26)
-
-#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
-enum {
- OPC_MSA_ELM = 0x19 | OPC_MSA,
-};
-
-enum {
- /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
- OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-};
-
static const char msaregnames[][6] = {
"w0.d0", "w0.d1", "w1.d0", "w1.d1",
"w2.d0", "w2.d1", "w3.d0", "w3.d1",
@@ -521,27 +509,22 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
return true;
}
-static void gen_msa_elm_3e(DisasContext *ctx)
+static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
{
-#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
- uint8_t source = (ctx->opcode >> 11) & 0x1f;
- uint8_t dest = (ctx->opcode >> 6) & 0x1f;
- TCGv telm = tcg_temp_new();
- TCGv_i32 tdt = tcg_const_i32(dest);
+ TCGv telm;
- switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
- case OPC_CTCMSA:
- gen_load_gpr(telm, source);
- gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
+ if (!check_msa_enabled(ctx)) {
+ return true;
}
+ telm = tcg_temp_new();
+
+ gen_load_gpr(telm, a->ws);
+ gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd));
+
tcg_temp_free(telm);
- tcg_temp_free_i32(tdt);
+
+ return true;
}
static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
@@ -642,20 +625,6 @@ static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a)
return trans_msa_elm_d64(ctx, a, gen_msa_insert);
}
-static void gen_msa_elm(DisasContext *ctx)
-{
- uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-
- if (dfn == 0x3E) {
- /* CTCMSA */
- gen_msa_elm_3e(ctx);
- return;
- } else {
- gen_reserved_instruction(ctx);
- return;
- }
-}
-
static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
enum CPUMIPSMSADataFormat df_base,
gen_helper_piiii *gen_msa_3rf)
@@ -798,21 +767,7 @@ TRANS_MSA(BSEL_V, trans_msa_vec, gen_helper_msa_bsel_v);
static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
{
- uint32_t opcode = ctx->opcode;
-
- if (!check_msa_enabled(ctx)) {
- return true;
- }
-
- switch (MASK_MSA_MINOR(opcode)) {
- case OPC_MSA_ELM:
- gen_msa_elm(ctx);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
+ gen_reserved_instruction(ctx);
return true;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 30/32] target/mips: Remove generic MSA opcode
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (28 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
` (2 subsequent siblings)
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
All opcodes have been converted to decodetree. The generic
MSA handler is now pointless, remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 2 --
target/mips/tcg/msa_translate.c | 7 -------
2 files changed, 9 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index f3ec195bac0..3e1b577f326 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -255,6 +255,4 @@ BNZ 010001 111 .. ..... ................ @bz
LD 011110 .......... ..... ..... 1000 .. @ldst
ST 011110 .......... ..... ..... 1001 .. @ldst
-
- MSA 011110 --------------------------
}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 4a2a02bd6d2..ef0e00772a6 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -765,13 +765,6 @@ TRANS_MSA(BMNZ_V, trans_msa_vec, gen_helper_msa_bmnz_v);
TRANS_MSA(BMZ_V, trans_msa_vec, gen_helper_msa_bmz_v);
TRANS_MSA(BSEL_V, trans_msa_vec, gen_helper_msa_bsel_v);
-static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
-{
- gen_reserved_instruction(ctx);
-
- return true;
-}
-
static bool trans_msa_ldst(DisasContext *ctx, arg_msa_ldst *a,
gen_helper_piv *gen_msa_ldst)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (29 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Only the MSA generic opcode was overlapping with the other
instructions. Since the previous commit removed it, we can
now remove the overlap group. The decodetree script forces
us to re-indent the opcodes.
Diff trivial to review using `git-diff --ignore-all-space`.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 398 ++++++++++++++++++-------------------
1 file changed, 198 insertions(+), 200 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 3e1b577f326..2c5cd3f03b8 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -54,205 +54,203 @@ BNZ_V 010001 01111 ..... ................ @bz_v
BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
+ANDI 011110 00 ........ ..... ..... 000000 @i8
+ORI 011110 01 ........ ..... ..... 000000 @i8
+NORI 011110 10 ........ ..... ..... 000000 @i8
+XORI 011110 11 ........ ..... ..... 000000 @i8
+BMNZI 011110 00 ........ ..... ..... 000001 @i8
+BMZI 011110 01 ........ ..... ..... 000001 @i8
+BSELI 011110 10 ........ ..... ..... 000001 @i8
+SHF 011110 .. ........ ..... ..... 000010 @i8_df
+
+ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
+SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
+MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
+MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
+MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
+MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
+
+CEQI 011110 000 .. ..... ..... ..... 000111 @s5
+CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
+CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
+CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
+CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
+
+LDI 011110 110 .. .......... ..... 000111 @ldi
+
+SLLI 011110 000 ....... ..... ..... 001001 @bit
+SRAI 011110 001 ....... ..... ..... 001001 @bit
+SRLI 011110 010 ....... ..... ..... 001001 @bit
+BCLRI 011110 011 ....... ..... ..... 001001 @bit
+BSETI 011110 100 ....... ..... ..... 001001 @bit
+BNEGI 011110 101 ....... ..... ..... 001001 @bit
+BINSLI 011110 110 ....... ..... ..... 001001 @bit
+BINSRI 011110 111 ....... ..... ..... 001001 @bit
+
+SAT_S 011110 000 ....... ..... ..... 001010 @bit
+SAT_U 011110 001 ....... ..... ..... 001010 @bit
+SRARI 011110 010 ....... ..... ..... 001010 @bit
+SRLRI 011110 011 ....... ..... ..... 001010 @bit
+
+SLL 011110 000.. ..... ..... ..... 001101 @3r
+SRA 011110 001.. ..... ..... ..... 001101 @3r
+SRL 011110 010.. ..... ..... ..... 001101 @3r
+BCLR 011110 011.. ..... ..... ..... 001101 @3r
+BSET 011110 100.. ..... ..... ..... 001101 @3r
+BNEG 011110 101.. ..... ..... ..... 001101 @3r
+BINSL 011110 110.. ..... ..... ..... 001101 @3r
+BINSR 011110 111.. ..... ..... ..... 001101 @3r
+
+ADDV 011110 000.. ..... ..... ..... 001110 @3r
+SUBV 011110 001.. ..... ..... ..... 001110 @3r
+MAX_S 011110 010.. ..... ..... ..... 001110 @3r
+MAX_U 011110 011.. ..... ..... ..... 001110 @3r
+MIN_S 011110 100.. ..... ..... ..... 001110 @3r
+MIN_U 011110 101.. ..... ..... ..... 001110 @3r
+MAX_A 011110 110.. ..... ..... ..... 001110 @3r
+MIN_A 011110 111.. ..... ..... ..... 001110 @3r
+
+CEQ 011110 000.. ..... ..... ..... 001111 @3r
+CLT_S 011110 010.. ..... ..... ..... 001111 @3r
+CLT_U 011110 011.. ..... ..... ..... 001111 @3r
+CLE_S 011110 100.. ..... ..... ..... 001111 @3r
+CLE_U 011110 101.. ..... ..... ..... 001111 @3r
+
+ADD_A 011110 000.. ..... ..... ..... 010000 @3r
+ADDS_A 011110 001.. ..... ..... ..... 010000 @3r
+ADDS_S 011110 010.. ..... ..... ..... 010000 @3r
+ADDS_U 011110 011.. ..... ..... ..... 010000 @3r
+AVE_S 011110 100.. ..... ..... ..... 010000 @3r
+AVE_U 011110 101.. ..... ..... ..... 010000 @3r
+AVER_S 011110 110.. ..... ..... ..... 010000 @3r
+AVER_U 011110 111.. ..... ..... ..... 010000 @3r
+
+SUBS_S 011110 000.. ..... ..... ..... 010001 @3r
+SUBS_U 011110 001.. ..... ..... ..... 010001 @3r
+SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r
+SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r
+ASUB_S 011110 100.. ..... ..... ..... 010001 @3r
+ASUB_U 011110 101.. ..... ..... ..... 010001 @3r
+
+MULV 011110 000.. ..... ..... ..... 010010 @3r
+MADDV 011110 001.. ..... ..... ..... 010010 @3r
+MSUBV 011110 010.. ..... ..... ..... 010010 @3r
+DIV_S 011110 100.. ..... ..... ..... 010010 @3r
+DIV_U 011110 101.. ..... ..... ..... 010010 @3r
+MOD_S 011110 110.. ..... ..... ..... 010010 @3r
+MOD_U 011110 111.. ..... ..... ..... 010010 @3r
+
+DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
+DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
+DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
+DPADD_U 011110 011.. ..... ..... ..... 010011 @3r
+DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r
+DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r
+
+SLD 011110 000 .. ..... ..... ..... 010100 @3r
+SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
+PCKEV 011110 010 .. ..... ..... ..... 010100 @3r
+PCKOD 011110 011 .. ..... ..... ..... 010100 @3r
+ILVL 011110 100 .. ..... ..... ..... 010100 @3r
+ILVR 011110 101 .. ..... ..... ..... 010100 @3r
+ILVEV 011110 110 .. ..... ..... ..... 010100 @3r
+ILVOD 011110 111 .. ..... ..... ..... 010100 @3r
+
+VSHF 011110 000 .. ..... ..... ..... 010101 @3r
+SRAR 011110 001 .. ..... ..... ..... 010101 @3r
+SRLR 011110 010 .. ..... ..... ..... 010101 @3r
+HADD_S 011110 100.. ..... ..... ..... 010101 @3r
+HADD_U 011110 101.. ..... ..... ..... 010101 @3r
+HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
+HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
+
{
- ANDI 011110 00 ........ ..... ..... 000000 @i8
- ORI 011110 01 ........ ..... ..... 000000 @i8
- NORI 011110 10 ........ ..... ..... 000000 @i8
- XORI 011110 11 ........ ..... ..... 000000 @i8
- BMNZI 011110 00 ........ ..... ..... 000001 @i8
- BMZI 011110 01 ........ ..... ..... 000001 @i8
- BSELI 011110 10 ........ ..... ..... 000001 @i8
- SHF 011110 .. ........ ..... ..... 000010 @i8_df
-
- ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
- SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
- MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
- MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
- MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
- MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
-
- CEQI 011110 000 .. ..... ..... ..... 000111 @s5
- CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
- CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
- CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
- CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
-
- LDI 011110 110 .. .......... ..... 000111 @ldi
-
- SLLI 011110 000 ....... ..... ..... 001001 @bit
- SRAI 011110 001 ....... ..... ..... 001001 @bit
- SRLI 011110 010 ....... ..... ..... 001001 @bit
- BCLRI 011110 011 ....... ..... ..... 001001 @bit
- BSETI 011110 100 ....... ..... ..... 001001 @bit
- BNEGI 011110 101 ....... ..... ..... 001001 @bit
- BINSLI 011110 110 ....... ..... ..... 001001 @bit
- BINSRI 011110 111 ....... ..... ..... 001001 @bit
-
- SAT_S 011110 000 ....... ..... ..... 001010 @bit
- SAT_U 011110 001 ....... ..... ..... 001010 @bit
- SRARI 011110 010 ....... ..... ..... 001010 @bit
- SRLRI 011110 011 ....... ..... ..... 001010 @bit
-
- SLL 011110 000.. ..... ..... ..... 001101 @3r
- SRA 011110 001.. ..... ..... ..... 001101 @3r
- SRL 011110 010.. ..... ..... ..... 001101 @3r
- BCLR 011110 011.. ..... ..... ..... 001101 @3r
- BSET 011110 100.. ..... ..... ..... 001101 @3r
- BNEG 011110 101.. ..... ..... ..... 001101 @3r
- BINSL 011110 110.. ..... ..... ..... 001101 @3r
- BINSR 011110 111.. ..... ..... ..... 001101 @3r
-
- ADDV 011110 000.. ..... ..... ..... 001110 @3r
- SUBV 011110 001.. ..... ..... ..... 001110 @3r
- MAX_S 011110 010.. ..... ..... ..... 001110 @3r
- MAX_U 011110 011.. ..... ..... ..... 001110 @3r
- MIN_S 011110 100.. ..... ..... ..... 001110 @3r
- MIN_U 011110 101.. ..... ..... ..... 001110 @3r
- MAX_A 011110 110.. ..... ..... ..... 001110 @3r
- MIN_A 011110 111.. ..... ..... ..... 001110 @3r
-
- CEQ 011110 000.. ..... ..... ..... 001111 @3r
- CLT_S 011110 010.. ..... ..... ..... 001111 @3r
- CLT_U 011110 011.. ..... ..... ..... 001111 @3r
- CLE_S 011110 100.. ..... ..... ..... 001111 @3r
- CLE_U 011110 101.. ..... ..... ..... 001111 @3r
-
- ADD_A 011110 000.. ..... ..... ..... 010000 @3r
- ADDS_A 011110 001.. ..... ..... ..... 010000 @3r
- ADDS_S 011110 010.. ..... ..... ..... 010000 @3r
- ADDS_U 011110 011.. ..... ..... ..... 010000 @3r
- AVE_S 011110 100.. ..... ..... ..... 010000 @3r
- AVE_U 011110 101.. ..... ..... ..... 010000 @3r
- AVER_S 011110 110.. ..... ..... ..... 010000 @3r
- AVER_U 011110 111.. ..... ..... ..... 010000 @3r
-
- SUBS_S 011110 000.. ..... ..... ..... 010001 @3r
- SUBS_U 011110 001.. ..... ..... ..... 010001 @3r
- SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r
- SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r
- ASUB_S 011110 100.. ..... ..... ..... 010001 @3r
- ASUB_U 011110 101.. ..... ..... ..... 010001 @3r
-
- MULV 011110 000.. ..... ..... ..... 010010 @3r
- MADDV 011110 001.. ..... ..... ..... 010010 @3r
- MSUBV 011110 010.. ..... ..... ..... 010010 @3r
- DIV_S 011110 100.. ..... ..... ..... 010010 @3r
- DIV_U 011110 101.. ..... ..... ..... 010010 @3r
- MOD_S 011110 110.. ..... ..... ..... 010010 @3r
- MOD_U 011110 111.. ..... ..... ..... 010010 @3r
-
- DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
- DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
- DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
- DPADD_U 011110 011.. ..... ..... ..... 010011 @3r
- DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r
- DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r
-
- SLD 011110 000 .. ..... ..... ..... 010100 @3r
- SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
- PCKEV 011110 010 .. ..... ..... ..... 010100 @3r
- PCKOD 011110 011 .. ..... ..... ..... 010100 @3r
- ILVL 011110 100 .. ..... ..... ..... 010100 @3r
- ILVR 011110 101 .. ..... ..... ..... 010100 @3r
- ILVEV 011110 110 .. ..... ..... ..... 010100 @3r
- ILVOD 011110 111 .. ..... ..... ..... 010100 @3r
-
- VSHF 011110 000 .. ..... ..... ..... 010101 @3r
- SRAR 011110 001 .. ..... ..... ..... 010101 @3r
- SRLR 011110 010 .. ..... ..... ..... 010101 @3r
- HADD_S 011110 100.. ..... ..... ..... 010101 @3r
- HADD_U 011110 101.. ..... ..... ..... 010101 @3r
- HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
- HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
-
- {
- CTCMSA 011110 0000111110 ..... ..... 011001 @elm
- SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
- }
- {
- CFCMSA 011110 0001111110 ..... ..... 011001 @elm
- SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
- }
- {
- MOVE_V 011110 0010111110 ..... ..... 011001 @elm
- COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
- }
- COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
- INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
- INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
-
- FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
- FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
- FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf
- FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf
- FCLT 011110 0100 . ..... ..... ..... 011010 @3rf
- FCULT 011110 0101 . ..... ..... ..... 011010 @3rf
- FCLE 011110 0110 . ..... ..... ..... 011010 @3rf
- FCULE 011110 0111 . ..... ..... ..... 011010 @3rf
- FSAF 011110 1000 . ..... ..... ..... 011010 @3rf
- FSUN 011110 1001 . ..... ..... ..... 011010 @3rf
- FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf
- FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf
- FSLT 011110 1100 . ..... ..... ..... 011010 @3rf
- FSULT 011110 1101 . ..... ..... ..... 011010 @3rf
- FSLE 011110 1110 . ..... ..... ..... 011010 @3rf
- FSULE 011110 1111 . ..... ..... ..... 011010 @3rf
-
- FADD 011110 0000 . ..... ..... ..... 011011 @3rf
- FSUB 011110 0001 . ..... ..... ..... 011011 @3rf
- FMUL 011110 0010 . ..... ..... ..... 011011 @3rf
- FDIV 011110 0011 . ..... ..... ..... 011011 @3rf
- FMADD 011110 0100 . ..... ..... ..... 011011 @3rf
- FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf
- FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf
- FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf
- FTQ 011110 1010 . ..... ..... ..... 011011 @3rf
- FMIN 011110 1100 . ..... ..... ..... 011011 @3rf
- FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf
- FMAX 011110 1110 . ..... ..... ..... 011011 @3rf
- FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf
-
- FCOR 011110 0001 . ..... ..... ..... 011100 @3rf
- FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf
- FCNE 011110 0011 . ..... ..... ..... 011100 @3rf
- MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf
- MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf
- MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf
- FSOR 011110 1001 . ..... ..... ..... 011100 @3rf
- FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf
- FSNE 011110 1011 . ..... ..... ..... 011100 @3rf
- MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf
- MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf
- MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf
-
- AND_V 011110 00000 ..... ..... ..... 011110 @vec
- OR_V 011110 00001 ..... ..... ..... 011110 @vec
- NOR_V 011110 00010 ..... ..... ..... 011110 @vec
- XOR_V 011110 00011 ..... ..... ..... 011110 @vec
- BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec
- BMZ_V 011110 00101 ..... ..... ..... 011110 @vec
- BSEL_V 011110 00110 ..... ..... ..... 011110 @vec
- FILL 011110 11000000 .. ..... ..... 011110 @2r
- PCNT 011110 11000001 .. ..... ..... 011110 @2r
- NLOC 011110 11000010 .. ..... ..... 011110 @2r
- NLZC 011110 11000011 .. ..... ..... 011110 @2r
- FCLASS 011110 110010000 . ..... ..... 011110 @2rf
- FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
- FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
- FSQRT 011110 110010011 . ..... ..... 011110 @2rf
- FRSQRT 011110 110010100 . ..... ..... 011110 @2rf
- FRCP 011110 110010101 . ..... ..... 011110 @2rf
- FRINT 011110 110010110 . ..... ..... 011110 @2rf
- FLOG2 011110 110010111 . ..... ..... 011110 @2rf
- FEXUPL 011110 110011000 . ..... ..... 011110 @2rf
- FEXUPR 011110 110011001 . ..... ..... 011110 @2rf
- FFQL 011110 110011010 . ..... ..... 011110 @2rf
- FFQR 011110 110011011 . ..... ..... 011110 @2rf
- FTINT_S 011110 110011100 . ..... ..... 011110 @2rf
- FTINT_U 011110 110011101 . ..... ..... 011110 @2rf
- FFINT_S 011110 110011110 . ..... ..... 011110 @2rf
- FFINT_U 011110 110011111 . ..... ..... 011110 @2rf
-
- LD 011110 .......... ..... ..... 1000 .. @ldst
- ST 011110 .......... ..... ..... 1001 .. @ldst
+ CTCMSA 011110 0000111110 ..... ..... 011001 @elm
+ SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
}
+{
+ CFCMSA 011110 0001111110 ..... ..... 011001 @elm
+ SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+}
+{
+ MOVE_V 011110 0010111110 ..... ..... 011001 @elm
+ COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
+}
+COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
+INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
+INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
+
+FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
+FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
+FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf
+FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf
+FCLT 011110 0100 . ..... ..... ..... 011010 @3rf
+FCULT 011110 0101 . ..... ..... ..... 011010 @3rf
+FCLE 011110 0110 . ..... ..... ..... 011010 @3rf
+FCULE 011110 0111 . ..... ..... ..... 011010 @3rf
+FSAF 011110 1000 . ..... ..... ..... 011010 @3rf
+FSUN 011110 1001 . ..... ..... ..... 011010 @3rf
+FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf
+FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf
+FSLT 011110 1100 . ..... ..... ..... 011010 @3rf
+FSULT 011110 1101 . ..... ..... ..... 011010 @3rf
+FSLE 011110 1110 . ..... ..... ..... 011010 @3rf
+FSULE 011110 1111 . ..... ..... ..... 011010 @3rf
+
+FADD 011110 0000 . ..... ..... ..... 011011 @3rf
+FSUB 011110 0001 . ..... ..... ..... 011011 @3rf
+FMUL 011110 0010 . ..... ..... ..... 011011 @3rf
+FDIV 011110 0011 . ..... ..... ..... 011011 @3rf
+FMADD 011110 0100 . ..... ..... ..... 011011 @3rf
+FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf
+FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf
+FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf
+FTQ 011110 1010 . ..... ..... ..... 011011 @3rf
+FMIN 011110 1100 . ..... ..... ..... 011011 @3rf
+FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf
+FMAX 011110 1110 . ..... ..... ..... 011011 @3rf
+FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf
+
+FCOR 011110 0001 . ..... ..... ..... 011100 @3rf
+FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf
+FCNE 011110 0011 . ..... ..... ..... 011100 @3rf
+MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf
+MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf
+MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf
+FSOR 011110 1001 . ..... ..... ..... 011100 @3rf
+FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf
+FSNE 011110 1011 . ..... ..... ..... 011100 @3rf
+MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf
+MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf
+MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf
+
+AND_V 011110 00000 ..... ..... ..... 011110 @vec
+OR_V 011110 00001 ..... ..... ..... 011110 @vec
+NOR_V 011110 00010 ..... ..... ..... 011110 @vec
+XOR_V 011110 00011 ..... ..... ..... 011110 @vec
+BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec
+BMZ_V 011110 00101 ..... ..... ..... 011110 @vec
+BSEL_V 011110 00110 ..... ..... ..... 011110 @vec
+FILL 011110 11000000 .. ..... ..... 011110 @2r
+PCNT 011110 11000001 .. ..... ..... 011110 @2r
+NLOC 011110 11000010 .. ..... ..... 011110 @2r
+NLZC 011110 11000011 .. ..... ..... 011110 @2r
+FCLASS 011110 110010000 . ..... ..... 011110 @2rf
+FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
+FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
+FSQRT 011110 110010011 . ..... ..... 011110 @2rf
+FRSQRT 011110 110010100 . ..... ..... 011110 @2rf
+FRCP 011110 110010101 . ..... ..... 011110 @2rf
+FRINT 011110 110010110 . ..... ..... 011110 @2rf
+FLOG2 011110 110010111 . ..... ..... 011110 @2rf
+FEXUPL 011110 110011000 . ..... ..... 011110 @2rf
+FEXUPR 011110 110011001 . ..... ..... 011110 @2rf
+FFQL 011110 110011010 . ..... ..... 011110 @2rf
+FFQR 011110 110011011 . ..... ..... 011110 @2rf
+FTINT_S 011110 110011100 . ..... ..... 011110 @2rf
+FTINT_U 011110 110011101 . ..... ..... 011110 @2rf
+FFINT_S 011110 110011110 . ..... ..... 011110 @2rf
+FFINT_U 011110 110011111 . ..... ..... 011110 @2rf
+
+LD 011110 .......... ..... ..... 1000 .. @ldst
+ST 011110 .......... ..... ..... 1001 .. @ldst
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init()
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (30 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
@ 2021-10-27 18:07 ` Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:07 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ef0e00772a6..f6d4f32248c 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -122,13 +122,15 @@ void msa_translate_init(void)
int i;
for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+ int off;
/*
* The MSA vector registers are mapped on the
* scalar floating-point unit (FPU) registers.
*/
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
msa_wr_d[i * 2] = fpu_f64[i];
+
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
--
2.31.1
^ permalink raw reply related [flat|nested] 54+ messages in thread
* Re: [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
` (31 preceding siblings ...)
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
@ 2021-10-27 18:12 ` Philippe Mathieu-Daudé
32 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 18:12 UTC (permalink / raw)
To: qemu-devel, Richard Henderson; +Cc: Aleksandar Rikalo, Aurelien Jarno
Forgot to Cc Richard...
On 10/27/21 20:06, Philippe Mathieu-Daudé wrote:
> Since v1:
> - Addressed Richard comments (thanks, I learned a lot doing so!
> Although I consider this series 'boring' I enjoyed working on
> your review comments).
> - Included Jiaxun R-b tags, but they are conditional on Richard
> ones.
>
> v1 unchanged cover:
>
> Hi,
>
> This series converts 2000+ lines of switch() code to decodetree
> description, so this hard-to-review/modify switch is auto generated
> by the decodetree script. This is a big win for maintenance (and
> indeed the convertion revealed 2 bugs).
>
> Massive convertions are - beside being often boring - bug-prone.
> In this series we re-start running the MSA tests (the tests are
> run automagically in the 'build-user-static' job on gitlab CI).
>
> Although boring, the conversion is very clean, so I hope it will
> be easy enough to review. The TRANS*() macros are heavily used.
>
> When possible, constant fields are hold with tcg_constant().
>
> Note, various opcodes can be optimized using TCG host vectors.
> We won't address that in this series, as it makes the resulting
> review harder. We will post that in a following series. Here we
> simply dummy-convert.
>
> The resulting msa.decode file is quite pleasant to look at, and
> the diff-stat is encouraging: number of LoC halved.
>
> Regards,
>
> Phil.
>
> git: https://gitlab.com/philmd/qemu.git tree/mips-msa-decodetree
> Based-on: <20211023164329.328137-1-f4bug@amsat.org>
>
> Philippe Mathieu-Daudé (32):
> target/mips: Fix MSA MADDV.B opcode
> target/mips: Fix MSA MSUBV.B opcode
> tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
> target/mips: Use dup_const() to simplify
> target/mips: Have check_msa_access() return a boolean
> target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
> target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
> target/mips: Convert MSA LDI opcode to decodetree
> target/mips: Convert MSA I5 instruction format to decodetree
> target/mips: Convert MSA BIT instruction format to decodetree
> target/mips: Convert MSA SHF opcode to decodetree
> target/mips: Convert MSA I8 instruction format to decodetree
> target/mips: Convert MSA load/store instruction format to decodetree
> target/mips: Convert MSA 2RF instruction format to decodetree
> target/mips: Convert MSA FILL opcode to decodetree
> target/mips: Convert MSA 2R instruction format to decodetree
> target/mips: Convert MSA VEC instruction format to decodetree
> target/mips: Convert MSA 3RF instruction format to decodetree
> (DF_HALF)
> target/mips: Convert MSA 3RF instruction format to decodetree
> (DF_WORD)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 1/4)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 2/4)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 3/4)
> target/mips: Convert MSA 3R instruction format to decodetree (part
> 4/4)
> target/mips: Convert MSA ELM instruction format to decodetree
> target/mips: Convert MSA COPY_U opcode to decodetree
> target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
> target/mips: Convert MSA MOVE.V opcode to decodetree
> target/mips: Convert CFCMSA opcode to decodetree
> target/mips: Convert CTCMSA opcode to decodetree
> target/mips: Remove generic MSA opcode
> target/mips: Remove one MSA unnecessary decodetree overlap group
> target/mips: Adjust style in msa_translate_init()
>
> tests/tcg/mips/ase-msa.mak | 30 +
> target/mips/tcg/msa.decode | 241 ++-
> target/mips/tcg/msa_helper.c | 64 +-
> target/mips/tcg/msa_translate.c | 2746 +++++++---------------------
> MAINTAINERS | 1 +
> tests/tcg/mips/Makefile.target | 5 +
> tests/tcg/mips64/Makefile.target | 9 +
> tests/tcg/mips64el/Makefile.target | 12 +
> tests/tcg/mipsel/Makefile.target | 9 +
> 9 files changed, 969 insertions(+), 2148 deletions(-)
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 04/32] target/mips: Use dup_const() to simplify
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
@ 2021-10-27 19:06 ` Richard Henderson
2021-10-28 20:53 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 19:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> + uint64_t eval_big = dup_const(df, 0x80);
> TCGv_i64 t0 = tcg_temp_new_i64();
> TCGv_i64 t1 = tcg_temp_new_i64();
> - switch (df) {
> - case DF_BYTE:
> - eval_zero_or_big = 0x0101010101010101ULL;
> - eval_big = 0x8080808080808080ULL;
> - break;
> - case DF_HALF:
> - eval_zero_or_big = 0x0001000100010001ULL;
> - eval_big = 0x8000800080008000ULL;
> - break;
> - case DF_WORD:
> - eval_zero_or_big = 0x0000000100000001ULL;
> - eval_big = 0x8000000080000000ULL;
> - break;
> - case DF_DOUBLE:
> - eval_zero_or_big = 0x0000000000000001ULL;
> - eval_big = 0x8000000000000000ULL;
The conversion is incorrect for eval_big.
The conversion creates e.g.
0x0080 0080 0080 0080
not
0x8000 8000 8000 8000
You'd have to do something like
uint64_t eval_one = dup_const(df, 1);
uint64_t eval_big = eval_one << ((8 << df) - 1);
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
@ 2021-10-27 19:07 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 19:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Have check_msa_access() return a boolean value so we can
> return early if MSA is not enabled (the instruction got
> decoded properly, but we raised an exception).
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2: return true (opcode decoded) because the opcode is decoded, reword
> ---
> target/mips/tcg/msa_translate.c | 25 ++++++++++++++++++-------
> 1 file changed, 18 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
@ 2021-10-27 19:10 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 19:10 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert the LDI opcode (Immediate Load) to decodetree. Since it
> overlaps with the generic MSA handler, use a decodetree overlap
> group.
>
> Since the 'data format' field is a constant value, use
> tcg_constant_i32() instead of a TCG temporary.
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2:
> - add &msa_ldi format
> - !check_msa_enabled -> return true
> - TCG timm is constant
> ---
> target/mips/tcg/msa.decode | 8 +++++++-
> target/mips/tcg/msa_translate.c | 22 ++++++++++++++--------
> 2 files changed, 21 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format to decodetree
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
@ 2021-10-27 19:17 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 19:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert instructions with a 5-bit immediate value to decodetree.
>
> Since the 'data format' field is a constant value, use
> tcg_constant_i32() instead of a TCG temporary.
>
> Reviewed-by: Richard Henderson<richard.henderson@linaro.org>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2:
> - add &msa_i5 format
> - TRANS_MSA() calls check_msa_enabled()
> - TCG timm is constant
> ---
> target/mips/tcg/msa.decode | 16 +++++
> target/mips/tcg/msa_translate.c | 114 ++++++++++----------------------
> 2 files changed, 52 insertions(+), 78 deletions(-)
I think you should drop TRANS_MSA and include the check in trans_msa_i5 instead. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 10/32] target/mips: Convert MSA BIT instruction format to decodetree
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
@ 2021-10-27 21:20 ` Richard Henderson
2021-10-28 11:04 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:20 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a,
> + gen_helper_piiii *gen_msa_bit)
> {
> + if (a->df < 0) {
> + return false;
> }
This test should happen before the msa check...
>
> + gen_msa_bit(cpu_env,
> + tcg_constant_i32(a->df),
> + tcg_constant_i32(a->wd),
> + tcg_constant_i32(a->ws),
> + tcg_constant_i32(a->m));
>
> + return true;
> }
>
> +TRANS_MSA(SLLI, trans_msa_bit, gen_helper_msa_slli_df);
... currently being hidden in here.
This is the reason why I suggest TRANS_MSA be dispensed with. You won't have over-many
explicit trans_* functions in which you need to place the msa check, I think.
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 11/32] target/mips: Convert MSA SHF opcode to decodetree
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
@ 2021-10-27 21:21 ` Richard Henderson
2021-10-28 11:45 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> +static bool trans_SHF(DisasContext *ctx, arg_msa_i8 *a)
> +{
> + if (a->df == DF_DOUBLE) {
> + gen_reserved_instruction(ctx);
> + return true;
> + }
Here you have the option to return false, as you choose.
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format to decodetree
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
@ 2021-10-27 21:31 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:31 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert instructions with an 8-bit immediate value and either
> implicit data format or data format df to decodetree.
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2: TCG timm is constant
> ---
> target/mips/tcg/msa.decode | 8 ++++
> target/mips/tcg/msa_translate.c | 73 ++++++++-------------------------
> 2 files changed, 24 insertions(+), 57 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Though of course it would be affected by any adjustment to TRANS_MSA.
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 13/32] target/mips: Convert MSA load/store instruction format to decodetree
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
@ 2021-10-27 21:42 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:42 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert load/store instructions to decodetree.
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2: Add TRANS_DF_x() and use an array of 4 functions (tip from Richard)
> ---
> target/mips/tcg/msa.decode | 5 ++
> target/mips/tcg/msa_translate.c | 86 +++++++++++----------------------
> 2 files changed, 32 insertions(+), 59 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 15/32] target/mips: Convert MSA FILL opcode to decodetree
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
@ 2021-10-27 21:46 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
> +{
> + if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
> + /* Double format valid only for MIPS64 */
> + gen_reserved_instruction(ctx);
> + return true;
> + }
Here you have the option to return false. But either way,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format to decodetree
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
@ 2021-10-27 21:50 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert 2-register operations to decodetree.
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2:
> - TRANS_DF_ii() uses array[4]
> ---
> target/mips/tcg/msa.decode | 3 ++
> target/mips/tcg/msa_translate.c | 87 +++++----------------------------
> 2 files changed, 15 insertions(+), 75 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
@ 2021-10-27 21:53 ` Richard Henderson
2021-10-28 13:14 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> +@3rf ...... .... df:1 wt:5ws:5 wd:5 ...... &msa_r
Add DF_HALF to df during decode?
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
@ 2021-10-27 21:54 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 21:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> +TRANS(FCAF, trans_msa_3rf, DF_WORD, gen_helper_msa_fcaf_df);
Add DF_WORD to df during decode?
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
@ 2021-10-27 22:02 ` Richard Henderson
2021-10-28 13:40 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 22:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert 3-register operations to decodetree.
>
> Per the Encoding of Operation Field for 3R Instruction Format'
> (Table 3.25), these instructions are not defined for the BYTE
> format. Therefore the TRANS_DF_iii_b() macro returns 'false'
> in that case, because no such instruction is decoded.
>
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v2: TRANS_DF_iii_b() uses array[4]
> ---
> target/mips/tcg/msa.decode | 11 ++
> target/mips/tcg/msa_translate.c | 195 ++++++--------------------------
> 2 files changed, 48 insertions(+), 158 deletions(-)
>
> diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
> index 7201b821ae0..f6471b92fc7 100644
> --- a/target/mips/tcg/msa.decode
> +++ b/target/mips/tcg/msa.decode
> @@ -87,10 +87,21 @@ BNZ 010001 111 .. ..... ................ @bz
> SRARI 011110 010 ....... ..... ..... 001010 @bit
> SRLRI 011110 011 ....... ..... ..... 001010 @bit
>
> + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
> + DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
> + DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
> + DPADD_U 011110 011.. ..... ..... ..... 010011 @3r
> + DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r
> + DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r
> +
> SLD 011110 000 .. ..... ..... ..... 010100 @3r
> SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
>
> VSHF 011110 000 .. ..... ..... ..... 010101 @3r
> + HADD_S 011110 100.. ..... ..... ..... 010101 @3r
> + HADD_U 011110 101.. ..... ..... ..... 010101 @3r
> + HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
> + HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
>
> FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
> FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index c7ca629d684..5cc704c9ace 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -47,13 +47,11 @@ enum {
> OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
> OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
> OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
> - OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
> OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
> OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
> OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
> OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
> OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
> - OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
> OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
> OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
> OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
> @@ -61,7 +59,6 @@ enum {
> OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
> OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
> OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
> - OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
> OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
> OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
> OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
> @@ -69,7 +66,6 @@ enum {
> OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
> OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
> OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
> - OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
> OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
> OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
> OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
> @@ -77,30 +73,24 @@ enum {
> OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
> OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
> OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
> - OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
> OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
> - OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
> OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
> OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
> OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
> OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
> OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
> OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
> - OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
> OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
> - OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
> OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
> OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
> OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
> OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
> OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
> - OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
> OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
> OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
> OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
> OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
> OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
> - OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
>
> /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
> OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> @@ -257,6 +247,21 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
> #define TRANS_DF_ii(NAME, trans_func, gen_func) \
> TRANS_DF_x(ii, NAME, trans_func, gen_func)
>
> +#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
> + static gen_helper_piii * const NAME##_tab[4] = { \
> + gen_func##_h, gen_func##_w, gen_func##_d \
> + }; \
> + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
> + { \
> + if (a->df == DF_BYTE) { \
> + return false; \
> + } \
> + if (!check_msa_enabled(ctx)) { \
> + return true; \
> + } \
> + return trans_func(ctx, a, NAME##_tab[a->df - DF_HALF]); \
Either reduce the size of the array by one, or place the NULL in its proper place at the
beginning rather than the end of the array. I think the latter is in the end clearer.
You could just as well place the checks within trans_msa_3r:
if (gen_msa_3r == NULL) {
return false;
}
if (!check_msa_enabled(ctx)) {
return true;
}
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
@ 2021-10-27 22:05 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 22:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm_df *a,
> + gen_helper_piiii *gen_msa_elm_df)
> +{
> + if (a->df < 0) {
> + return false;
> + }
> +
> + gen_msa_elm_df(cpu_env,
> + tcg_constant_i32(a->df),
> + tcg_constant_i32(a->wd),
> + tcg_constant_i32(a->ws),
> + tcg_constant_i32(a->n));
> +
> + return true;
> +}
> +
> +TRANS_MSA(SLDI, trans_msa_elm_df, gen_helper_msa_sldi_df);
This suffers from the same test ordering problem as in patch 10.
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode to decodetree
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
@ 2021-10-27 22:08 ` Richard Henderson
0 siblings, 0 replies; 54+ messages in thread
From: Richard Henderson @ 2021-10-27 22:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
> decodetree.
>
> Since the 'n' field is a constant value, use tcg_constant_i32()
> instead of a TCG temporary.
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> v2: Add NULL_IF_TARGET_MIPS32() macro, use array of 4 functions
> ---
> target/mips/tcg/msa.decode | 1 +
> target/mips/tcg/msa_translate.c | 66 ++++++++++++++++++++-------------
> 2 files changed, 41 insertions(+), 26 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 10/32] target/mips: Convert MSA BIT instruction format to decodetree
2021-10-27 21:20 ` Richard Henderson
@ 2021-10-28 11:04 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-28 11:04 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 23:20, Richard Henderson wrote:
> On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
>> +static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a,
>> + gen_helper_piiii *gen_msa_bit)
>> {
>> + if (a->df < 0) {
>> + return false;
>> }
>
> This test should happen before the msa check...
>> + gen_msa_bit(cpu_env,
>> + tcg_constant_i32(a->df),
>> + tcg_constant_i32(a->wd),
>> + tcg_constant_i32(a->ws),
>> + tcg_constant_i32(a->m));
>> + return true;
>> }
>> +TRANS_MSA(SLLI, trans_msa_bit, gen_helper_msa_slli_df);
>
> ... currently being hidden in here.
>
> This is the reason why I suggest TRANS_MSA be dispensed with. You won't
> have over-many explicit trans_* functions in which you need to place the
> msa check, I think.
Yes, you are right.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 11/32] target/mips: Convert MSA SHF opcode to decodetree
2021-10-27 21:21 ` Richard Henderson
@ 2021-10-28 11:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-28 11:45 UTC (permalink / raw)
To: Richard Henderson
Cc: Aleksandar Rikalo, qemu-devel@nongnu.org Developers, Aurelien Jarno
On Wed, Oct 27, 2021 at 11:21 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> > +static bool trans_SHF(DisasContext *ctx, arg_msa_i8 *a)
> > +{
> > + if (a->df == DF_DOUBLE) {
> > + gen_reserved_instruction(ctx);
> > + return true;
> > + }
>
> Here you have the option to return false, as you choose.
Yes, I prefer to return false. Thanks for re-reviewing patches where I
included your R-b tag :)
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
2021-10-27 21:53 ` Richard Henderson
@ 2021-10-28 13:14 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-28 13:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 23:53, Richard Henderson wrote:
> On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
>> +@3rf ...... .... df:1 wt:5ws:5 wd:5 ...... &msa_r
>
> Add DF_HALF to df during decode?
Yet another tip, thanks :)
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
2021-10-27 22:02 ` Richard Henderson
@ 2021-10-28 13:40 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-28 13:40 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/28/21 00:02, Richard Henderson wrote:
> On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
>> Convert 3-register operations to decodetree.
>>
>> Per the Encoding of Operation Field for 3R Instruction Format'
>> (Table 3.25), these instructions are not defined for the BYTE
>> format. Therefore the TRANS_DF_iii_b() macro returns 'false'
>> in that case, because no such instruction is decoded.
>>
>> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> v2: TRANS_DF_iii_b() uses array[4]
>> ---
>> target/mips/tcg/msa.decode | 11 ++
>> target/mips/tcg/msa_translate.c | 195 ++++++--------------------------
>> 2 files changed, 48 insertions(+), 158 deletions(-)
>> +#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
>> + static gen_helper_piii * const NAME##_tab[4] = { \
>> + gen_func##_h, gen_func##_w, gen_func##_d \
>> + }; \
>> + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
>> + { \
>> + if (a->df == DF_BYTE) { \
>> + return false; \
>> + } \
>> + if (!check_msa_enabled(ctx)) { \
>> + return true; \
>> + } \
>> + return trans_func(ctx, a, NAME##_tab[a->df - DF_HALF]); \
>
> Either reduce the size of the array by one, or place the NULL in its
> proper place at the beginning rather than the end of the array. I think
> the latter is in the end clearer.
Yes.
> You could just as well place the checks within trans_msa_3r:
>
> if (gen_msa_3r == NULL) {
> return false;
> }
> if (!check_msa_enabled(ctx)) {
> return true;
> }
Indeed, thank you.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v2 04/32] target/mips: Use dup_const() to simplify
2021-10-27 19:06 ` Richard Henderson
@ 2021-10-28 20:53 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-28 20:53 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/27/21 21:06, Richard Henderson wrote:
> On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
>> + uint64_t eval_big = dup_const(df, 0x80);
>> TCGv_i64 t0 = tcg_temp_new_i64();
>> TCGv_i64 t1 = tcg_temp_new_i64();
>> - switch (df) {
>> - case DF_BYTE:
>> - eval_zero_or_big = 0x0101010101010101ULL;
>> - eval_big = 0x8080808080808080ULL;
>> - break;
>> - case DF_HALF:
>> - eval_zero_or_big = 0x0001000100010001ULL;
>> - eval_big = 0x8000800080008000ULL;
>> - break;
>> - case DF_WORD:
>> - eval_zero_or_big = 0x0000000100000001ULL;
>> - eval_big = 0x8000000080000000ULL;
>> - break;
>> - case DF_DOUBLE:
>> - eval_zero_or_big = 0x0000000000000001ULL;
>> - eval_big = 0x8000000000000000ULL;
>
> The conversion is incorrect for eval_big.
> The conversion creates e.g.
>
> 0x0080 0080 0080 0080
> not
> 0x8000 8000 8000 8000
Oops...
> You'd have to do something like
>
> uint64_t eval_one = dup_const(df, 1);
> uint64_t eval_big = eval_one << ((8 << df) - 1);
Nice :)
^ permalink raw reply [flat|nested] 54+ messages in thread
end of thread, other threads:[~2021-10-28 20:55 UTC | newest]
Thread overview: 54+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-27 19:06 ` Richard Henderson
2021-10-28 20:53 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-27 19:07 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-27 19:10 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-27 19:17 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-27 21:20 ` Richard Henderson
2021-10-28 11:04 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-27 21:21 ` Richard Henderson
2021-10-28 11:45 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-27 21:31 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-27 21:42 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-27 21:46 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-27 21:50 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-27 21:53 ` Richard Henderson
2021-10-28 13:14 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-27 21:54 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-27 22:02 ` Richard Henderson
2021-10-28 13:40 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-27 22:05 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-27 22:08 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
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