From: "Cédric Le Goater" <clg@kaod.org>
To: Guenter Roeck <linux@roeck-us.net>
Cc: Andrew Jeffery <andrew@aj.id.au>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, Joel Stanley <joel@jms.id.au>,
qemu-devel@nongnu.org
Subject: Re: [PATCH] hw/arm: ast2400/ast2500: Wire up EHCI controllers
Date: Fri, 7 Feb 2020 09:16:28 +0100 [thread overview]
Message-ID: <e9f490fe-34d3-6830-832c-155f6fa63482@kaod.org> (raw)
In-Reply-To: <20200206183437.3979-1-linux@roeck-us.net>
On 2/6/20 7:34 PM, Guenter Roeck wrote:
> Initialize EHCI controllers on AST2400 and AST2500 using the existing
> TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
> successfully instantiates a USB interface.
>
> ehci-platform 1e6a3000.usb: EHCI Host Controller
> ehci-platform 1e6a3000.usb: new USB bus registered, assigned bus number 1
> ehci-platform 1e6a3000.usb: irq 21, io mem 0x1e6a3000
> ehci-platform 1e6a3000.usb: USB 2.0 started, EHCI 1.00
> usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.05
> usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
> usb usb1: Product: EHCI Host Controller
Cool. Have you tried to plug any devices ?
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This looks good. Could you add the AST2600 also ?
Thanks,
C.
> ---
> hw/arm/aspeed_soc.c | 25 +++++++++++++++++++++++++
> include/hw/arm/aspeed_soc.h | 6 ++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index b5e809a1d3..696c7fda14 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -30,6 +30,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
> [ASPEED_IOMEM] = 0x1E600000,
> [ASPEED_FMC] = 0x1E620000,
> [ASPEED_SPI1] = 0x1E630000,
> + [ASPEED_EHCI1] = 0x1E6A1000,
> [ASPEED_VIC] = 0x1E6C0000,
> [ASPEED_SDMC] = 0x1E6E0000,
> [ASPEED_SCU] = 0x1E6E2000,
> @@ -59,6 +60,8 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
> [ASPEED_FMC] = 0x1E620000,
> [ASPEED_SPI1] = 0x1E630000,
> [ASPEED_SPI2] = 0x1E631000,
> + [ASPEED_EHCI1] = 0x1E6A1000,
> + [ASPEED_EHCI2] = 0x1E6A3000,
> [ASPEED_VIC] = 0x1E6C0000,
> [ASPEED_SDMC] = 0x1E6E0000,
> [ASPEED_SCU] = 0x1E6E2000,
> @@ -91,6 +94,8 @@ static const int aspeed_soc_ast2400_irqmap[] = {
> [ASPEED_UART5] = 10,
> [ASPEED_VUART] = 8,
> [ASPEED_FMC] = 19,
> + [ASPEED_EHCI1] = 5,
> + [ASPEED_EHCI2] = 13,
> [ASPEED_SDMC] = 0,
> [ASPEED_SCU] = 21,
> [ASPEED_ADC] = 31,
> @@ -180,6 +185,11 @@ static void aspeed_soc_init(Object *obj)
> sizeof(s->spi[i]), typename);
> }
>
> + for (i = 0; i < sc->ehcis_num; i++) {
> + sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
> + sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
> + }
> +
> snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
> sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
> typename);
> @@ -364,6 +374,19 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> s->spi[i].ctrl->flash_window_base);
> }
>
> + /* EHCI */
> + for (i = 0; i < sc->ehcis_num; i++) {
> + object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
> + sc->memmap[ASPEED_EHCI1 + i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
> + aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
> + }
> +
> /* SDMC - SDRAM Memory Controller */
> object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
> if (err) {
> @@ -472,6 +495,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> sc->silicon_rev = AST2400_A1_SILICON_REV;
> sc->sram_size = 0x8000;
> sc->spis_num = 1;
> + sc->ehcis_num = 1;
> sc->wdts_num = 2;
> sc->macs_num = 2;
> sc->irqmap = aspeed_soc_ast2400_irqmap;
> @@ -496,6 +520,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> sc->silicon_rev = AST2500_A1_SILICON_REV;
> sc->sram_size = 0x9000;
> sc->spis_num = 2;
> + sc->ehcis_num = 2;
> sc->wdts_num = 3;
> sc->macs_num = 2;
> sc->irqmap = aspeed_soc_ast2500_irqmap;
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 90ac7f7ffa..78b9f6ae53 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -26,8 +26,10 @@
> #include "target/arm/cpu.h"
> #include "hw/gpio/aspeed_gpio.h"
> #include "hw/sd/aspeed_sdhci.h"
> +#include "hw/usb/hcd-ehci.h"
>
> #define ASPEED_SPIS_NUM 2
> +#define ASPEED_EHCIS_NUM 2
> #define ASPEED_WDTS_NUM 4
> #define ASPEED_CPUS_NUM 2
> #define ASPEED_MACS_NUM 4
> @@ -50,6 +52,7 @@ typedef struct AspeedSoCState {
> AspeedXDMAState xdma;
> AspeedSMCState fmc;
> AspeedSMCState spi[ASPEED_SPIS_NUM];
> + EHCISysBusState ehci[ASPEED_EHCIS_NUM];
> AspeedSDMCState sdmc;
> AspeedWDTState wdt[ASPEED_WDTS_NUM];
> FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
> @@ -71,6 +74,7 @@ typedef struct AspeedSoCClass {
> uint32_t silicon_rev;
> uint64_t sram_size;
> int spis_num;
> + int ehcis_num;
> int wdts_num;
> int macs_num;
> const int *irqmap;
> @@ -94,6 +98,8 @@ enum {
> ASPEED_FMC,
> ASPEED_SPI1,
> ASPEED_SPI2,
> + ASPEED_EHCI1,
> + ASPEED_EHCI2,
> ASPEED_VIC,
> ASPEED_SDMC,
> ASPEED_SCU,
>
next prev parent reply other threads:[~2020-02-07 8:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-06 18:34 [PATCH] hw/arm: ast2400/ast2500: Wire up EHCI controllers Guenter Roeck
2020-02-07 8:16 ` Cédric Le Goater [this message]
2020-02-07 12:58 ` Guenter Roeck
2020-02-07 13:05 ` Cédric Le Goater
2020-02-07 13:09 ` Joel Stanley
2020-02-07 14:21 ` Guenter Roeck
2020-02-07 14:30 ` Cédric Le Goater
2020-02-07 13:40 ` Philippe Mathieu-Daudé
2020-02-13 11:58 ` Peter Maydell
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