Re: Qemu and ARM secure state.

[Jean-Christophe DUBOIS <jcd@tribudubois.net>]

Le 08/11/2021 à 15:50, Peter Maydell a écrit :
> On Sat, 6 Nov 2021 at 18:11, Jean-Christophe DUBOIS <jcd@tribudubois.net> wrote:
>> One small question/remark:
>>
>> According to the the "Arm Power State Coordinate Interface" (DEN0022D.b) document (chapter 5) PSCI calls can only be issued by "normal world" (EL1 or EL2). Therefore, should we be adding a test for the current secure state in the arm_is_psci_call() function? This would prevent calling the built-in Qemu PSCI function if SMC is issued  from secure state.
> This shouldn't matter, because if the machine model is configured
> to execute guest code in EL3 at all then it should not be enabling
> QEMU's internal PSCI support. The internal PSCI stuff is only
> there as a kind of "emulated firmware" for when we're running
> guest code that starts at EL2 (notably, when directly booting
> a Linux kernel).
>
> The problem seems to be that fsl_imx6ul_realize() and
> fsl_imx7_realize() unconditionally enable PSCI-via-SMC.
> The imx7 code also puts all the secondaries into
> PSCI-powered-off mode -- this should be checked to
> work out what the right thing is if we're not doing
> emulated PSCI and instead starting the guest at EL3.

OK, so one problem seems to be that PSCI-via-SMC is enabled on i.MX6UL 
when there is no built in PSCI related function on this processor.

According the Linux DTS, i.MX7 (solo and dual) processors have a 
somewhat PSCI related "entry-method" 
(https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/imx7s.dtsi). 
But it is not clear to me how this is used and this seems a bit strange 
as "entry-method" seems to be mostly used on arm64 and there is no other 
PSCI related information in the i.MX7 DTS files. As a matter of fact 
previous quad or dual i.MX6 were not supporting PSCI. Instead they were 
using a proprietary method through the internal SRC device (and i.MX7 
also has a similar internal SRC device). But let's assume Linux on i.mx7 
is actually using PSCI to handle processors.

Thinking about it, I guess this might be u-boot that sets an EL3 monitor 
software that is able to handle PSCI requests for the Linux kernel. If 
this is the case, it make sense that Qemu emulates the PSCI services 
normally provided by u-boot to be able to boot linux directly (without 
booting a real u-boot prior to linux). All  is well and nice.

But then if I want to boot and test the u-boot binary (or any trusted OS 
for the matter) on a Qemu emulated i.MX7 (to later boot an hypervisor or 
an OS), it would be rather strange that any PSCI related service 
requested by the hypervisor/OS  would be handled by Qemu directly and 
not by the u-boot code (or any other EL3 code) running on the processor. 
How is it supposed to work? How can I tell Qemu (dynamically?) if I want 
it to provide (or not) the PSCI services (and more generally SMC/HVC 
services). How can I tell it that I want to handle all SMC/EL3 services 
by myself even if the "psci-conduit" is already set to SMC in Qemu?

Am I missing something?

thanks.

JC

>
> -- PMM
>