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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [PATCH v1 2/6] riscv/sifive_u: Add QSPI memory region
Date: Thu, 19 Sep 2019 15:24:58 -0700	[thread overview]
Message-ID: <f72e3c4ebbfa0f8fb08b7c8cb0bafd48ca41cad5.1568931866.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1568931866.git.alistair.francis@wdc.com>

There doesn't seem to be details on what QSPI the HiFive Unleashed uses.
To allow boot firmware developers to use QEMU to target the Unleashed
let's add a chunk of memory to represent the QSPI. This can be targeted
using QEMU's -device loader command line option.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c         | 8 ++++++++
 include/hw/riscv/sifive_u.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index de6e197882..9c5d791320 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -71,6 +71,7 @@ static const struct MemmapEntry {
     [SIFIVE_U_UART0] =    { 0x10010000,     0x1000 },
     [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },
     [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },
+    [SIFIVE_U_FLASH0] =   { 0x20000000,  0x2000000 },
     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
     [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },
     [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },
@@ -313,6 +314,7 @@ static void riscv_sifive_u_init(MachineState *machine)
     SiFiveUState *s = g_new0(SiFiveUState, 1);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+    MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     int i;
 
     /* Initialize SoC */
@@ -328,6 +330,12 @@ static void riscv_sifive_u_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
                                 main_mem);
 
+    /* register QSPI0 Flash */
+    memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
+                           memmap[SIFIVE_U_FLASH0].size, &error_fatal);
+    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+                                flash0);
+
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 50e3620c02..2a08e2a5db 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -64,6 +64,7 @@ enum {
     SIFIVE_U_UART0,
     SIFIVE_U_UART1,
     SIFIVE_U_OTP,
+    SIFIVE_U_FLASH0,
     SIFIVE_U_DRAM,
     SIFIVE_U_GEM,
     SIFIVE_U_GEM_MGMT
-- 
2.23.0



  parent reply	other threads:[~2019-09-19 22:31 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-19 22:24 [PATCH v1 0/6] RISC-V: Add more machine memory Alistair Francis
2019-09-19 22:24 ` [PATCH v1 1/6] riscv/sifive_u: Add L2-LIM cache memory Alistair Francis
2019-09-20  5:15   ` Bin Meng
2019-09-19 22:24 ` Alistair Francis [this message]
2019-09-20  5:15   ` [PATCH v1 2/6] riscv/sifive_u: Add QSPI memory region Bin Meng
2019-09-19 22:25 ` [PATCH v1 3/6] riscv/sifive_u: Manually define the machine Alistair Francis
2019-09-20  5:15   ` Bin Meng
2019-09-19 22:25 ` [PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property Alistair Francis
2019-09-20  5:15   ` Bin Meng
2019-09-20 22:07     ` Alistair Francis
2019-09-22  2:19       ` Bin Meng
2019-09-23 17:51         ` Alistair Francis
2019-09-24  0:57           ` Bin Meng
2019-09-19 22:25 ` [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device Alistair Francis
2019-09-20  5:15   ` Bin Meng
2019-09-20 22:12     ` Alistair Francis
2019-09-22  2:15       ` Bin Meng
2019-09-23 20:08         ` Alistair Francis
2019-09-23 21:46       ` Peter Maydell
2019-09-24  9:32         ` Philippe Mathieu-Daudé
2019-09-24 17:12           ` Laszlo Ersek
2019-09-25  0:55           ` Alistair Francis
2019-09-25 11:15             ` Philippe Mathieu-Daudé
2019-09-25  0:54         ` Alistair Francis
2019-09-25  9:00           ` Markus Armbruster
2019-09-27 21:49             ` Alistair Francis
2019-09-19 22:25 ` [PATCH v1 6/6] riscv/virt: Jump to pflash if specified Alistair Francis
2019-09-20  5:15   ` Bin Meng
2019-09-23  9:09     ` Philippe Mathieu-Daudé
2019-09-20 22:40 ` [PATCH v1 0/6] RISC-V: Add more machine memory Palmer Dabbelt

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