From: Palmer Dabbelt <palmer@sifive.com> To: Alistair Francis <Alistair.Francis@wdc.com> Cc: qemu-riscv@nongnu.org, Anup Patel <Anup.Patel@wdc.com>, qemu-devel@nongnu.org, Atish Patra <Atish.Patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, alistair23@gmail.com Subject: Re: [PATCH v1 22/28] target/riscv: Allow specifying MMU stage Date: Thu, 03 Oct 2019 08:53:42 -0700 (PDT) Message-ID: <mhng-87129cf6-394a-4b08-bf67-a6bb60f86245@palmer-si-x1e> (raw) In-Reply-To: <4d84c887def558fc178c31e3adc52f1c4b2fb075.1566603412.git.alistair.francis@wdc.com> On Fri, 23 Aug 2019 16:38:47 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu_helper.c | 39 ++++++++++++++++++++++++++++++--------- > 1 file changed, 30 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 098873c83e..9aa6906acd 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -318,10 +318,19 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) > * > * Adapted from Spike's mmu_t::translate and mmu_t::walk > * > + * @env: CPURISCVState > + * @physical: This will be set to the calculated physical address > + * @prot: The returned protection attributes > + * @addr: The virtual address to be translated > + * @access_type: The type of MMU access > + * @mmu_idx: Indicates current privilege level > + * @first_stage: Are we in first stage translation? > + * Second stage is used for hypervisor guest translation > */ > static int get_physical_address(CPURISCVState *env, hwaddr *physical, > int *prot, target_ulong addr, > - int access_type, int mmu_idx) > + int access_type, int mmu_idx, > + bool first_stage) > { > /* NOTE: the env->pc value visible here will not be > * correct, but the value visible to the exception handler > @@ -518,13 +527,23 @@ restart: > } > > static void raise_mmu_exception(CPURISCVState *env, target_ulong address, > - MMUAccessType access_type, bool pmp_violation) > + MMUAccessType access_type, bool pmp_violation, > + bool first_stage) > { > CPUState *cs = env_cpu(env); > - int page_fault_exceptions = > - (env->priv_ver >= PRIV_VERSION_1_10_0) && > - get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && > - !pmp_violation; > + int page_fault_exceptions; > + if (first_stage) { > + page_fault_exceptions = > + (env->priv_ver >= PRIV_VERSION_1_10_0) && > + get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && > + !pmp_violation; > + riscv_cpu_set_force_hs_excep(env, CLEAR_HS_EXCEP); It might just be email, but the indentation looks wrong here. > + } else { > + page_fault_exceptions = > + get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE && > + !pmp_violation; > + riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); > + } > switch (access_type) { > case MMU_INST_FETCH: > cs->exception_index = page_fault_exceptions ? > @@ -551,7 +570,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > int prot; > int mmu_idx = cpu_mmu_index(&cpu->env, false); > > - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { > + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx, > + true)) { > return -1; > } > return phys_addr; > @@ -613,7 +633,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", > __func__, address, access_type, mmu_idx); > > - ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); > + ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, > + true); > > if (mode == PRV_M && access_type != MMU_INST_FETCH) { > if (get_field(*env->mstatus, MSTATUS_MPRV)) { > @@ -640,7 +661,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > } else if (probe) { > return false; > } else { > - raise_mmu_exception(env, address, access_type, pmp_violation); > + raise_mmu_exception(env, address, access_type, pmp_violation, true); > riscv_raise_exception(env, cs->exception_index, retaddr); > } > #else I don't think it makes sense to split off these two (23 and 24, that add the argument) out from the implementation.
next prev parent reply index Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-23 23:37 [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4 Alistair Francis 2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension Alistair Francis 2019-08-27 15:26 ` Chih-Min Chao 2019-09-10 13:43 ` Palmer Dabbelt 2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode Alistair Francis 2019-08-27 15:44 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao 2019-08-28 0:08 ` Alistair Francis 2019-09-10 13:44 ` [Qemu-devel] " Palmer Dabbelt 2019-09-16 15:57 ` Alistair Francis 2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode Alistair Francis 2019-08-27 15:46 ` Chih-Min Chao 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-10-16 20:56 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis 2019-08-27 15:50 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao 2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers Alistair Francis 2019-09-11 8:24 ` Palmer Dabbelt 2019-09-11 14:54 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens 2019-09-17 23:33 ` Alistair Francis 2019-09-18 1:59 ` Jonathan Behrens 2019-09-18 23:47 ` Alistair Francis 2019-09-19 14:50 ` Richard Henderson 2019-09-19 16:58 ` Jonathan Behrens 2019-10-25 20:28 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function Alistair Francis 2019-09-11 14:17 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting Alistair Francis 2019-09-14 20:30 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis 2019-09-14 20:30 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis 2019-09-14 20:30 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis 2019-09-14 20:32 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support Alistair Francis 2019-09-20 14:01 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support Alistair Francis 2019-10-01 18:33 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions Alistair Francis 2019-10-01 18:34 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status Alistair Francis 2019-10-01 18:34 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis 2019-10-01 18:34 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis 2019-10-02 23:52 ` Palmer Dabbelt 2019-10-16 21:01 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage Alistair Francis 2019-10-03 15:53 ` Palmer Dabbelt [this message] 2019-10-07 18:05 ` Alistair Francis 2019-10-16 19:02 ` Palmer Dabbelt 2019-10-16 21:25 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU Alistair Francis 2019-10-07 16:15 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis 2019-10-08 17:54 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis 2019-10-08 18:36 ` Palmer Dabbelt 2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis 2019-10-08 18:36 ` Palmer Dabbelt 2019-10-16 21:14 ` Alistair Francis 2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension Alistair Francis 2019-10-08 18:53 ` Palmer Dabbelt
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