From: Palmer Dabbelt <palmer@sifive.com> To: Alistair Francis <Alistair.Francis@wdc.com> Cc: qemu-riscv@nongnu.org, Anup Patel <Anup.Patel@wdc.com>, qemu-devel@nongnu.org, Atish Patra <Atish.Patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, alistair23@gmail.com Subject: Re: [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function Date: Wed, 11 Sep 2019 07:17:00 -0700 (PDT) Message-ID: <mhng-fe7f7960-29da-4b78-a6e1-37b03bc878b8@palmer-si-x1e> (raw) In-Reply-To: <ec79c985398944a8443eac5673d40bc0969f8380.1566603412.git.alistair.francis@wdc.com> On Fri, 23 Aug 2019 16:38:18 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.h | 24 ++++++++--- > target/riscv/cpu_bits.h | 7 ++++ > target/riscv/cpu_helper.c | 88 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 113 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 680592cb60..05957f32a8 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -125,15 +125,18 @@ struct CPURISCVState { > target_ulong *mstatus; > > /* > - * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously > - * by I/O threads. It should be read with atomic_read. It should be updated > - * using riscv_cpu_update_mip with the iothread mutex held. The iothread > - * mutex must be held because mip must be consistent with the CPU inturrept > - * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt > - * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. > + * CAUTION! Unlike the rest of this struct, mip and mip_novirt is accessed > + * asynchonously by I/O threads. It should be read with atomic_read. It should > + * be updated using riscv_cpu_update_mip with the iothread mutex held. The > + * iothread mutex must be held because mip must be consistent with the CPU > + * inturrept state. riscv_cpu_update_mip calls cpu_interrupt or > + * cpu_reset_interrupt wuth the invariant that CPU_INTERRUPT_HARD is set if > + * mip is non-zero. > * mip is 32-bits to allow atomic_read on 32-bit hosts. > */ > uint32_t mip; > + uint32_t mip_novirt; > + > uint32_t miclaim; > > target_ulong *mie; > @@ -179,6 +182,14 @@ struct CPURISCVState { > target_ulong vstval; > target_ulong vsatp; > > + /* HS Backup CSRs */ > + target_ulong stvec_hs; > + target_ulong sscratch_hs; > + target_ulong sepc_hs; > + target_ulong scause_hs; > + target_ulong stval_hs; > + target_ulong satp_hs; > + > target_ulong scounteren; > target_ulong mcounteren; > > @@ -306,6 +317,7 @@ void riscv_cpu_list(void); > #define cpu_mmu_index riscv_cpu_mmu_index > > #ifndef CONFIG_USER_ONLY > +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); > uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 78067901a2..5cee72b726 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -556,4 +556,11 @@ > #define SIP_STIP MIP_STIP > #define SIP_SEIP MIP_SEIP > > +/* MIE masks */ > +#define MIE_SEIE (1 << IRQ_S_EXT) > +#define MIE_UEIE (1 << IRQ_U_EXT) > +#define MIE_STIE (1 << IRQ_S_TIMER) > +#define MIE_UTIE (1 << IRQ_U_TIMER) > +#define MIE_SSIE (1 << IRQ_S_SOFT) > +#define MIE_USIE (1 << IRQ_U_SOFT) > #endif > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index c597523d74..41d4368128 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -81,6 +81,94 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) > return false; > } > > +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > +{ > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + uint32_t tmp; > + target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | > + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; > + target_ulong sie_mask = MIE_SEIE | MIE_STIE | MIE_SSIE | > + MIE_UEIE | MIE_UTIE | MIE_USIE; > + target_ulong mip_mask = MIP_SSIP | MIP_STIP | MIP_SEIP; > + bool current_virt = riscv_cpu_virt_enabled(env); > + > + g_assert(riscv_has_ext(env, RVH)); > + > +#if defined(TARGET_RISCV64) > + mstatus_mask |= MSTATUS64_UXL; > +#endif > + > + if (current_virt) { This worries me more than the pointer stuff: specifically, my worry is keeping V in sync with the register set in use. > + /* Current V=1 and we are about to change to V=0 */ > + env->mstatus = &env->mstatus_novirt; > + *env->mstatus &= mstatus_mask; > + *env->mstatus |= env->vsstatus & ~mstatus_mask; > + /* Ensure that vsstatus only holds the correct bits */ > + env->vsstatus &= mstatus_mask; > + > + env->mie = &env->mie_novirt; > + *env->mie &= sie_mask; > + *env->mie |= env->vsie & ~sie_mask; > + /* Ensure that vsie only holds the correct bits */ > + env->vsie &= sie_mask; > + > + env->vstvec = env->stvec; > + env->stvec = env->stvec_hs; > + > + env->vsscratch = env->sscratch; > + env->sscratch = env->sscratch_hs; > + > + env->vsepc = env->sepc; > + env->sepc = env->sepc_hs; > + > + env->vscause = env->scause; > + env->scause = env->scause_hs; > + > + env->vstval = env->sbadaddr; > + env->sbadaddr = env->stval_hs; > + > + env->vsatp = env->satp; > + env->satp = env->satp_hs; > + > + tmp = (uint32_t)atomic_read(&env->mip_novirt); > + tmp = riscv_cpu_update_mip(cpu, mip_mask, tmp); > + tmp &= mip_mask; > + atomic_set(&env->vsip, tmp); We talked about this in person, and Alistair is going to do the fake interrupt thing to avoid the atomicity requirements entirely. > + } else { > + /* Current V=0 and we are about to change to V=1 */ > + env->mstatus = &env->vsstatus; > + *env->mstatus &= mstatus_mask; > + *env->mstatus |= env->mstatus_novirt & ~mstatus_mask; > + > + env->mie = &env->vsie; > + *env->mie &= sie_mask; > + *env->mie |= env->mie_novirt & ~sie_mask; > + > + env->stvec_hs = env->stvec; > + env->stvec = env->vstvec; > + > + env->sscratch_hs = env->sscratch; > + env->sscratch = env->vsscratch; > + > + env->sepc_hs = env->sepc; > + env->sepc = env->vsepc; > + > + env->scause_hs = env->scause; > + env->scause = env->vscause; > + > + env->stval_hs = env->sbadaddr; > + env->sbadaddr = env->vstval; > + > + env->satp_hs = env->satp; > + env->satp = env->vsatp; > + > + tmp = (uint32_t)atomic_read(&env->vsip); > + tmp = riscv_cpu_update_mip(cpu, mip_mask, tmp); > + tmp &= mip_mask; > + atomic_set(&env->mip_novirt, tmp); > + } > +} > + > bool riscv_cpu_virt_enabled(CPURISCVState *env) > { > bool tmp;
next prev parent reply index Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-23 23:37 [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4 Alistair Francis 2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension Alistair Francis 2019-08-27 15:26 ` Chih-Min Chao 2019-09-10 13:43 ` Palmer Dabbelt 2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode Alistair Francis 2019-08-27 15:44 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao 2019-08-28 0:08 ` Alistair Francis 2019-09-10 13:44 ` [Qemu-devel] " Palmer Dabbelt 2019-09-16 15:57 ` Alistair Francis 2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode Alistair Francis 2019-08-27 15:46 ` Chih-Min Chao 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-10-16 20:56 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis 2019-08-27 15:50 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao 2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis 2019-09-10 14:48 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers Alistair Francis 2019-09-11 8:24 ` Palmer Dabbelt 2019-09-11 14:54 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens 2019-09-17 23:33 ` Alistair Francis 2019-09-18 1:59 ` Jonathan Behrens 2019-09-18 23:47 ` Alistair Francis 2019-09-19 14:50 ` Richard Henderson 2019-09-19 16:58 ` Jonathan Behrens 2019-10-25 20:28 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function Alistair Francis 2019-09-11 14:17 ` Palmer Dabbelt [this message] 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting Alistair Francis 2019-09-14 20:30 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis 2019-09-14 20:30 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis 2019-09-14 20:30 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis 2019-09-14 20:32 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support Alistair Francis 2019-09-20 14:01 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support Alistair Francis 2019-10-01 18:33 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions Alistair Francis 2019-10-01 18:34 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status Alistair Francis 2019-10-01 18:34 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis 2019-10-01 18:34 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis 2019-10-02 23:52 ` Palmer Dabbelt 2019-10-16 21:01 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage Alistair Francis 2019-10-03 15:53 ` Palmer Dabbelt 2019-10-07 18:05 ` Alistair Francis 2019-10-16 19:02 ` Palmer Dabbelt 2019-10-16 21:25 ` Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages Alistair Francis 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU Alistair Francis 2019-10-07 16:15 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis 2019-10-08 17:54 ` Palmer Dabbelt 2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis 2019-10-08 18:36 ` Palmer Dabbelt 2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis 2019-10-08 18:36 ` Palmer Dabbelt 2019-10-16 21:14 ` Alistair Francis 2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension Alistair Francis 2019-10-08 18:53 ` Palmer Dabbelt
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