From: Ivan Klokov <ivan.klokov@syntacore.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org,
pbonzini@redhat.com, eduardo@habkost.net,
marcel.apfelbaum@gmail.com, philmd@linaro.org,
wangyanan55@huawei.com, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com,
Ivan Klokov <ivan.klokov@syntacore.com>
Subject: [PATCH v3 2/2] target/riscv: Add RVV registers to log
Date: Mon, 10 Apr 2023 15:44:51 +0300 [thread overview]
Message-ID: <20230410124451.15929-3-ivan.klokov@syntacore.com> (raw)
In-Reply-To: <20230410124451.15929-1-ivan.klokov@syntacore.com>
Print RvV extesion register to log if VPU option is enabled.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
---
target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5bc0005cc7..cfd063a5dc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] = {
"f30/ft10", "f31/ft11"
};
+const char * const riscv_rvv_regnames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6",
+ "v7", "v8", "v9", "v10", "v11", "v12", "v13",
+ "v14", "v15", "v16", "v17", "v18", "v19", "v20",
+ "v21", "v22", "v23", "v24", "v25", "v26", "v27",
+ "v28", "v29", "v30", "v31"
+};
+
static const char * const riscv_excp_names[] = {
"misaligned_fetch",
"fault_fetch",
@@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- int i;
+ int i, j;
+ uint8_t *p;
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
@@ -506,6 +515,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
}
+ if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
+ static const int dump_rvv_csrs[] = {
+ CSR_VSTART,
+ CSR_VXSAT,
+ CSR_VXRM,
+ CSR_VCSR,
+ CSR_VL,
+ CSR_VTYPE,
+ CSR_VLENB,
+ };
+ for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
+ int csrno = dump_rvv_csrs[i];
+ target_ulong val = 0;
+ RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+ /*
+ * Rely on the smode, hmode, etc, predicates within csr.c
+ * to do the filtering of the registers that are present.
+ */
+ if (res == RISCV_EXCP_NONE) {
+ qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+ csr_ops[csrno].name, val);
+ }
+ }
+ uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+
+/*
+ * From vector_helper.c
+ * Note that vector data is stored in host-endian 64-bit chunks,
+ * so addressing bytes needs a host-endian fixup.
+ */
+#if HOST_BIG_ENDIAN
+#define BYTE(x) ((x) ^ 7)
+#else
+#define BYTE(x) (x)
+#endif
+ for (i = 0; i < 32; i++) {
+ qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
+ p = (uint8_t *)env->vreg;
+ for (j = vlenb - 1 ; j >= 0; j--) {
+ qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
+ }
+ qemu_fprintf(f, "\n");
+ }
+ }
}
static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
--
2.34.1
next prev parent reply other threads:[~2023-04-10 12:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-10 12:44 [PATCH v3 0/2] Support for print to log vector extension registers Ivan Klokov
2023-04-10 12:44 ` [PATCH v3 1/2] util/log: Add vector registers to log Ivan Klokov
2023-04-12 10:56 ` Alistair Francis
2023-04-10 12:44 ` Ivan Klokov [this message]
2023-04-12 10:57 ` [PATCH v3 2/2] target/riscv: Add RVV " Alistair Francis
2023-06-02 3:43 ` Alistair Francis
2023-06-02 10:20 ` Philippe Mathieu-Daudé
2023-06-02 3:40 ` [PATCH v3 0/2] Support for print to log vector extension registers Alistair Francis
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