* [PATCH v7 0/2] target/riscv: Fix pointer mask related support
@ 2023-05-24 1:59 Weiwei Li
2023-05-24 1:59 ` [PATCH v7 1/2] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-05-24 1:59 ` [PATCH v7 2/2] target/riscv: Update cur_pmmask/base when xl changes Weiwei Li
0 siblings, 2 replies; 3+ messages in thread
From: Weiwei Li @ 2023-05-24 1:59 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
This patchset tries to fix some problem in current implementation for pointer mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v7
v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
* Add patch 4 and 5 to use PC-relative translation for pointer mask for instruction fetch
v3:
* use target_pc temp instead of cpu_pc to store into badaddr in patch 3
* use dest_gpr instead of tcg_temp_new() for succ_pc in patch 4
* enable CF_PCREL for system mode in seperate patch 5
v4:
* Fix wrong pc_save value for conditional jump in patch 4
* Fix tcg_cflags overwrite problem to make CF_PCREL really work in new patch 5
* Fix tb mis-matched problem in new patch 6
v5:
* use gen_get_target_pc to compute target address of auipc and successor address of jalr in patch 4.
* separate tcg related fix patches(5, 6) from this patchset
v6:
* rename gen_get_target_pc as g in patch 3 and patch 4
* use gen_pc_plus_diff to compute successor address of jal in patch 4
* mov comments for patch 5 to patch 4
v7:
* separate support for PC-relative translation and pointer mask for instruction fetch (patch 3~6) out of this patchset
Weiwei Li (2):
target/riscv: Fix pointer mask transformation for vector address
target/riscv: Update cur_pmmask/base when xl changes
target/riscv/csr.c | 9 ++++++++-
target/riscv/vector_helper.c | 2 +-
2 files changed, 9 insertions(+), 2 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v7 1/2] target/riscv: Fix pointer mask transformation for vector address
2023-05-24 1:59 [PATCH v7 0/2] target/riscv: Fix pointer mask related support Weiwei Li
@ 2023-05-24 1:59 ` Weiwei Li
2023-05-24 1:59 ` [PATCH v7 2/2] target/riscv: Update cur_pmmask/base when xl changes Weiwei Li
1 sibling, 0 replies; 3+ messages in thread
From: Weiwei Li @ 2023-05-24 1:59 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8e6c99e573..7505f9470a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -169,7 +169,7 @@ static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
- return (addr & env->cur_pmmask) | env->cur_pmbase;
+ return (addr & ~env->cur_pmmask) | env->cur_pmbase;
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v7 2/2] target/riscv: Update cur_pmmask/base when xl changes
2023-05-24 1:59 [PATCH v7 0/2] target/riscv: Fix pointer mask related support Weiwei Li
2023-05-24 1:59 ` [PATCH v7 1/2] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
@ 2023-05-24 1:59 ` Weiwei Li
1 sibling, 0 replies; 3+ messages in thread
From: Weiwei Li @ 2023-05-24 1:59 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/csr.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cf7da4f87f..ad73691878 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1324,8 +1324,15 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
}
env->mstatus = mstatus;
- env->xl = cpu_recompute_xl(env);
+ /*
+ * Except in debug mode, UXL/SXL can only be modified by higher
+ * privilege mode. So xl will not be changed in normal mode.
+ */
+ if (env->debugger) {
+ env->xl = cpu_recompute_xl(env);
+ riscv_cpu_update_mask(env);
+ }
return RISCV_EXCP_NONE;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2023-05-24 1:59 [PATCH v7 0/2] target/riscv: Fix pointer mask related support Weiwei Li
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