[PATCH v2 0/7] target/riscv: Add support for PC-relative translation

[PATCH v2 0/7] target/riscv: Add support for PC-relative translation

[Weiwei Li]

This patchset tries to add support for PC-relative translation.

The existence of CF_PCREL can improve performance with the guest
kernel's address space randomization.  Each guest process maps libc.so
(et al) at a different virtual address, and this allows those
translations to be shared.

And support of PC-relative translation is the precondition to support
pointer mask for instruction.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pcrel-upstream-v2

v2:
 * rebase on upstream and add pc-relative translation for Zc* instructions

Weiwei Li (7):
  target/riscv: Fix target address to update badaddr
  target/riscv: Introduce cur_insn_len into DisasContext
  target/riscv: Change gen_goto_tb to work on displacements
  target/riscv: Change gen_set_pc_imm to gen_update_pc
  target/riscv: Use true diff for gen_pc_plus_diff
  target/riscv: Enable PC-relative translation
  target/riscv: Remove pc_succ_insn from DisasContext

 target/riscv/cpu.c                            | 31 ++++--
 .../riscv/insn_trans/trans_privileged.c.inc   |  2 +-
 target/riscv/insn_trans/trans_rvi.c.inc       | 43 ++++++---
 target/riscv/insn_trans/trans_rvv.c.inc       |  4 +-
 target/riscv/insn_trans/trans_rvzawrs.c.inc   |  2 +-
 target/riscv/insn_trans/trans_rvzce.c.inc     | 10 +-
 target/riscv/insn_trans/trans_xthead.c.inc    |  2 +-
 target/riscv/translate.c                      | 94 ++++++++++++-------
 8 files changed, 123 insertions(+), 65 deletions(-)

-- 
2.25.1

[PATCH v2 1/7] target/riscv: Fix target address to update badaddr

[Weiwei Li]

Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and restore cpu_pc to current pc if exception is triggered.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvi.c.inc   | 23 ++++++++++++++++-------
 target/riscv/insn_trans/trans_rvzce.c.inc |  4 ++--
 target/riscv/translate.c                  | 21 ++++++++++-----------
 3 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index c70c495fc5..0d52a80178 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -51,25 +51,30 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
     TCGLabel *misaligned = NULL;
+    TCGv target_pc = tcg_temp_new();
 
-    tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
-    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+    tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
+    tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
+
+    if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32s_tl(target_pc, target_pc);
+    }
 
-    gen_set_pc(ctx, cpu_pc);
     if (!ctx->cfg_ptr->ext_zca) {
         TCGv t0 = tcg_temp_new();
 
         misaligned = gen_new_label();
-        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+        tcg_gen_andi_tl(t0, target_pc, 0x2);
         tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
     }
 
     gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
+    tcg_gen_mov_tl(cpu_pc, target_pc);
     lookup_and_goto_ptr(ctx);
 
     if (misaligned) {
         gen_set_label(misaligned);
-        gen_exception_inst_addr_mis(ctx);
+        gen_exception_inst_addr_mis(ctx, target_pc);
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 
@@ -153,6 +158,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     TCGLabel *l = gen_new_label();
     TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
     TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
+    target_ulong next_pc;
 
     if (get_xl(ctx) == MXL_RV128) {
         TCGv src1h = get_gprh(ctx, a->rs1);
@@ -169,9 +175,12 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 
     gen_set_label(l); /* branch taken */
 
-    if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
+    next_pc = ctx->base.pc_next + a->imm;
+    if (!ctx->cfg_ptr->ext_zca && (next_pc & 0x3)) {
         /* misaligned */
-        gen_exception_inst_addr_mis(ctx);
+        TCGv target_pc = tcg_temp_new();
+        gen_pc_plus_diff(target_pc, ctx, next_pc);
+        gen_exception_inst_addr_mis(ctx, target_pc);
     } else {
         gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
     }
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index a727169a4b..5732d782f7 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -202,8 +202,8 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)
     }
 
     if (ret) {
-        TCGv ret_addr = get_gpr(ctx, xRA, EXT_NONE);
-        gen_set_pc(ctx, ret_addr);
+        TCGv ret_addr = get_gpr(ctx, xRA, EXT_SIGN);
+        tcg_gen_mov_tl(cpu_pc, ret_addr);
         tcg_gen_lookup_and_goto_ptr();
         ctx->base.is_jmp = DISAS_NORETURN;
     }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 928da0d3f0..1c9a667653 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -222,21 +222,18 @@ static void decode_save_opc(DisasContext *ctx)
     ctx->insn_start = NULL;
 }
 
-static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
+                             target_ulong dest)
 {
     if (get_xl(ctx) == MXL_RV32) {
         dest = (int32_t)dest;
     }
-    tcg_gen_movi_tl(cpu_pc, dest);
+    tcg_gen_movi_tl(target, dest);
 }
 
-static void gen_set_pc(DisasContext *ctx, TCGv dest)
+static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
 {
-    if (get_xl(ctx) == MXL_RV32) {
-        tcg_gen_ext32s_tl(cpu_pc, dest);
-    } else {
-        tcg_gen_mov_tl(cpu_pc, dest);
-    }
+    gen_pc_plus_diff(cpu_pc, ctx, dest);
 }
 
 static void generate_exception(DisasContext *ctx, int excp)
@@ -257,9 +254,9 @@ static void gen_exception_illegal(DisasContext *ctx)
     }
 }
 
-static void gen_exception_inst_addr_mis(DisasContext *ctx)
+static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target)
 {
-    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
+    tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr));
     generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
 }
 
@@ -551,7 +548,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     next_pc = ctx->base.pc_next + imm;
     if (!ctx->cfg_ptr->ext_zca) {
         if ((next_pc & 0x3) != 0) {
-            gen_exception_inst_addr_mis(ctx);
+            TCGv target_pc = tcg_temp_new();
+            gen_pc_plus_diff(target_pc, ctx, next_pc);
+            gen_exception_inst_addr_mis(ctx, target_pc);
             return;
         }
     }
-- 
2.25.1

[PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext

[Weiwei Li]

Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1c9a667653..d756866925 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -59,6 +59,7 @@ typedef struct DisasContext {
     DisasContextBase base;
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
+    target_ulong cur_insn_len;
     target_ulong priv_ver;
     RISCVMXL misa_mxl_max;
     RISCVMXL xl;
@@ -1114,8 +1115,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
     };
 
     ctx->virt_inst_excp = false;
+    ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
-    if (insn_len(opcode) == 2) {
+    if (ctx->cur_insn_len == 2) {
         ctx->opcode = opcode;
         ctx->pc_succ_insn = ctx->base.pc_next + 2;
         /*
-- 
2.25.1

Re: [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext

[Richard Henderson]

On 5/23/23 06:59, Weiwei Li wrote:
> Use cur_insn_len to store the length of the current instruction to
> prepare for PC-relative translation.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/translate.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext

[Alistair Francis]

On Wed, May 24, 2023 at 12:16 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Use cur_insn_len to store the length of the current instruction to
> prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 1c9a667653..d756866925 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -59,6 +59,7 @@ typedef struct DisasContext {
>      DisasContextBase base;
>      /* pc_succ_insn points to the instruction following base.pc_next */
>      target_ulong pc_succ_insn;
> +    target_ulong cur_insn_len;
>      target_ulong priv_ver;
>      RISCVMXL misa_mxl_max;
>      RISCVMXL xl;
> @@ -1114,8 +1115,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
>      };
>
>      ctx->virt_inst_excp = false;
> +    ctx->cur_insn_len = insn_len(opcode);
>      /* Check for compressed insn */
> -    if (insn_len(opcode) == 2) {
> +    if (ctx->cur_insn_len == 2) {
>          ctx->opcode = opcode;
>          ctx->pc_succ_insn = ctx->base.pc_next + 2;
>          /*
> --
> 2.25.1
>
>

[PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements

[Weiwei Li]

Reduce reliance on absolute value to prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
 target/riscv/translate.c                | 8 +++++---
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 0d52a80178..81ed0d200a 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -171,7 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     } else {
         tcg_gen_brcond_tl(cond, src1, src2, l);
     }
-    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+    gen_goto_tb(ctx, 1, ctx->cur_insn_len);
 
     gen_set_label(l); /* branch taken */
 
@@ -182,7 +182,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
         gen_pc_plus_diff(target_pc, ctx, next_pc);
         gen_exception_inst_addr_mis(ctx, target_pc);
     } else {
-        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+        gen_goto_tb(ctx, 0, a->imm);
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d756866925..8a371c0d75 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -281,8 +281,10 @@ static void exit_tb(DisasContext *ctx)
     tcg_gen_exit_tb(NULL, 0);
 }
 
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
 {
+    target_ulong dest = ctx->base.pc_next + diff;
+
      /*
       * Under itrigger, instruction executes one by one like singlestep,
       * direct block chain benefits will be small.
@@ -557,7 +559,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     }
 
     gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
-    gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
+    gen_goto_tb(ctx, 0, imm); /* must use this for safety */
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -1228,7 +1230,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 
     switch (ctx->base.is_jmp) {
     case DISAS_TOO_MANY:
-        gen_goto_tb(ctx, 0, ctx->base.pc_next);
+        gen_goto_tb(ctx, 0, 0);
         break;
     case DISAS_NORETURN:
         break;
-- 
2.25.1

Re: [PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements

[Richard Henderson]

On 5/23/23 06:59, Weiwei Li wrote:
> Reduce reliance on absolute value to prepare for PC-relative translation.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
>   target/riscv/translate.c                | 8 +++++---
>   2 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/tar

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements

[Alistair Francis]

On Wed, May 24, 2023 at 12:14 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Reduce reliance on absolute value to prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
>  target/riscv/translate.c                | 8 +++++---
>  2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 0d52a80178..81ed0d200a 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -171,7 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>      } else {
>          tcg_gen_brcond_tl(cond, src1, src2, l);
>      }
> -    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
> +    gen_goto_tb(ctx, 1, ctx->cur_insn_len);
>
>      gen_set_label(l); /* branch taken */
>
> @@ -182,7 +182,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>          gen_pc_plus_diff(target_pc, ctx, next_pc);
>          gen_exception_inst_addr_mis(ctx, target_pc);
>      } else {
> -        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
> +        gen_goto_tb(ctx, 0, a->imm);
>      }
>      ctx->base.is_jmp = DISAS_NORETURN;
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d756866925..8a371c0d75 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -281,8 +281,10 @@ static void exit_tb(DisasContext *ctx)
>      tcg_gen_exit_tb(NULL, 0);
>  }
>
> -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
>  {
> +    target_ulong dest = ctx->base.pc_next + diff;
> +
>       /*
>        * Under itrigger, instruction executes one by one like singlestep,
>        * direct block chain benefits will be small.
> @@ -557,7 +559,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>      }
>
>      gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
> -    gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
> +    gen_goto_tb(ctx, 0, imm); /* must use this for safety */
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
>
> @@ -1228,7 +1230,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
>
>      switch (ctx->base.is_jmp) {
>      case DISAS_TOO_MANY:
> -        gen_goto_tb(ctx, 0, ctx->base.pc_next);
> +        gen_goto_tb(ctx, 0, 0);
>          break;
>      case DISAS_NORETURN:
>          break;
> --
> 2.25.1
>
>

[PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc

[Weiwei Li]

Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_privileged.c.inc |  2 +-
 target/riscv/insn_trans/trans_rvi.c.inc        |  6 +++---
 target/riscv/insn_trans/trans_rvv.c.inc        |  4 ++--
 target/riscv/insn_trans/trans_rvzawrs.c.inc    |  2 +-
 target/riscv/insn_trans/trans_xthead.c.inc     |  2 +-
 target/riscv/translate.c                       | 10 +++++-----
 6 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 7c2837194c..3760fb4393 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -112,7 +112,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 {
 #ifndef CONFIG_USER_ONLY
     decode_save_opc(ctx);
-    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    gen_update_pc(ctx, ctx->cur_insn_len);
     gen_helper_wfi(cpu_env);
     return true;
 #else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 81ed0d200a..f9f4d25cda 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -776,7 +776,7 @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
      * PAUSE is a no-op in QEMU,
      * end the TB and return to main loop
      */
-    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    gen_update_pc(ctx, ctx->cur_insn_len);
     exit_tb(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
 
@@ -800,7 +800,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
      * FENCE_I is a no-op in QEMU,
      * however we need to end the translation block
      */
-    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    gen_update_pc(ctx, ctx->cur_insn_len);
     exit_tb(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
@@ -811,7 +811,7 @@ static bool do_csr_post(DisasContext *ctx)
     /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
     decode_save_opc(ctx);
     /* We may have changed important cpu state -- exit to main loop. */
-    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    gen_update_pc(ctx, ctx->cur_insn_len);
     exit_tb(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c07eebc52..c2f7527f53 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -169,7 +169,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
 
-    gen_set_pc_imm(s, s->pc_succ_insn);
+    gen_update_pc(s, s->cur_insn_len);
     lookup_and_goto_ptr(s);
     s->base.is_jmp = DISAS_NORETURN;
     return true;
@@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
-    gen_set_pc_imm(s, s->pc_succ_insn);
+    gen_update_pc(s, s->cur_insn_len);
     lookup_and_goto_ptr(s);
     s->base.is_jmp = DISAS_NORETURN;
 
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index 8254e7dfe2..32efbff4d5 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -33,7 +33,7 @@ static bool trans_wrs(DisasContext *ctx)
     /* Clear the load reservation  (if any).  */
     tcg_gen_movi_tl(load_res, -1);
 
-    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    gen_update_pc(ctx, ctx->cur_insn_len);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
 
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index 3e13b1d74d..da093a4cec 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -999,7 +999,7 @@ static void gen_th_sync_local(DisasContext *ctx)
      * Emulate out-of-order barriers with pipeline flush
      * by exiting the translation block.
      */
-    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    gen_update_pc(ctx, ctx->cur_insn_len);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8a371c0d75..b01aa48f04 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -232,14 +232,14 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
     tcg_gen_movi_tl(target, dest);
 }
 
-static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+static void gen_update_pc(DisasContext *ctx, target_long diff)
 {
-    gen_pc_plus_diff(cpu_pc, ctx, dest);
+    gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
 }
 
 static void generate_exception(DisasContext *ctx, int excp)
 {
-    gen_set_pc_imm(ctx, ctx->base.pc_next);
+    gen_update_pc(ctx, 0);
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
@@ -291,10 +291,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
       */
     if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
         tcg_gen_goto_tb(n);
-        gen_set_pc_imm(ctx, dest);
+        gen_update_pc(ctx, diff);
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
-        gen_set_pc_imm(ctx, dest);
+        gen_update_pc(ctx, diff);
         lookup_and_goto_ptr(ctx);
     }
 }
-- 
2.25.1

Re: [PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc

[Richard Henderson]

On 5/23/23 06:59, Weiwei Li wrote:
> Reduce reliance on absolute values(by passing pc difference) to
> prepare for PC-relative translation.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/insn_trans/trans_privileged.c.inc |  2 +-
>   target/riscv/insn_trans/trans_rvi.c.inc        |  6 +++---
>   target/riscv/insn_trans/trans_rvv.c.inc        |  4 ++--
>   target/riscv/insn_trans/trans_rvzawrs.c.inc    |  2 +-
>   target/riscv/insn_trans/trans_xthead.c.inc     |  2 +-
>   target/riscv/translate.c                       | 10 +++++-----
>   6 files changed, 13 insertions(+), 13 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc

[Alistair Francis]

On Wed, May 24, 2023 at 12:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Reduce reliance on absolute values(by passing pc difference) to
> prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_privileged.c.inc |  2 +-
>  target/riscv/insn_trans/trans_rvi.c.inc        |  6 +++---
>  target/riscv/insn_trans/trans_rvv.c.inc        |  4 ++--
>  target/riscv/insn_trans/trans_rvzawrs.c.inc    |  2 +-
>  target/riscv/insn_trans/trans_xthead.c.inc     |  2 +-
>  target/riscv/translate.c                       | 10 +++++-----
>  6 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
> index 7c2837194c..3760fb4393 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -112,7 +112,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
>  {
>  #ifndef CONFIG_USER_ONLY
>      decode_save_opc(ctx);
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      gen_helper_wfi(cpu_env);
>      return true;
>  #else
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 81ed0d200a..f9f4d25cda 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -776,7 +776,7 @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
>       * PAUSE is a no-op in QEMU,
>       * end the TB and return to main loop
>       */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      exit_tb(ctx);
>      ctx->base.is_jmp = DISAS_NORETURN;
>
> @@ -800,7 +800,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
>       * FENCE_I is a no-op in QEMU,
>       * however we need to end the translation block
>       */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      exit_tb(ctx);
>      ctx->base.is_jmp = DISAS_NORETURN;
>      return true;
> @@ -811,7 +811,7 @@ static bool do_csr_post(DisasContext *ctx)
>      /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
>      decode_save_opc(ctx);
>      /* We may have changed important cpu state -- exit to main loop. */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      exit_tb(ctx);
>      ctx->base.is_jmp = DISAS_NORETURN;
>      return true;
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6c07eebc52..c2f7527f53 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -169,7 +169,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
>      gen_set_gpr(s, rd, dst);
>      mark_vs_dirty(s);
>
> -    gen_set_pc_imm(s, s->pc_succ_insn);
> +    gen_update_pc(s, s->cur_insn_len);
>      lookup_and_goto_ptr(s);
>      s->base.is_jmp = DISAS_NORETURN;
>      return true;
> @@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
>      gen_helper_vsetvl(dst, cpu_env, s1, s2);
>      gen_set_gpr(s, rd, dst);
>      mark_vs_dirty(s);
> -    gen_set_pc_imm(s, s->pc_succ_insn);
> +    gen_update_pc(s, s->cur_insn_len);
>      lookup_and_goto_ptr(s);
>      s->base.is_jmp = DISAS_NORETURN;
>
> diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> index 8254e7dfe2..32efbff4d5 100644
> --- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> @@ -33,7 +33,7 @@ static bool trans_wrs(DisasContext *ctx)
>      /* Clear the load reservation  (if any).  */
>      tcg_gen_movi_tl(load_res, -1);
>
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      tcg_gen_exit_tb(NULL, 0);
>      ctx->base.is_jmp = DISAS_NORETURN;
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
> index 3e13b1d74d..da093a4cec 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -999,7 +999,7 @@ static void gen_th_sync_local(DisasContext *ctx)
>       * Emulate out-of-order barriers with pipeline flush
>       * by exiting the translation block.
>       */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      tcg_gen_exit_tb(NULL, 0);
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 8a371c0d75..b01aa48f04 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -232,14 +232,14 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
>      tcg_gen_movi_tl(target, dest);
>  }
>
> -static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
> +static void gen_update_pc(DisasContext *ctx, target_long diff)
>  {
> -    gen_pc_plus_diff(cpu_pc, ctx, dest);
> +    gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
>  }
>
>  static void generate_exception(DisasContext *ctx, int excp)
>  {
> -    gen_set_pc_imm(ctx, ctx->base.pc_next);
> +    gen_update_pc(ctx, 0);
>      gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
> @@ -291,10 +291,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
>        */
>      if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
>          tcg_gen_goto_tb(n);
> -        gen_set_pc_imm(ctx, dest);
> +        gen_update_pc(ctx, diff);
>          tcg_gen_exit_tb(ctx->base.tb, n);
>      } else {
> -        gen_set_pc_imm(ctx, dest);
> +        gen_update_pc(ctx, diff);
>          lookup_and_goto_ptr(ctx);
>      }
>  }
> --
> 2.25.1
>
>

[PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff

[Weiwei Li]

Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvi.c.inc   |  6 ++----
 target/riscv/insn_trans/trans_rvzce.c.inc |  2 +-
 target/riscv/translate.c                  | 13 ++++++-------
 3 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index f9f4d25cda..d6eef67b45 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -158,7 +158,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     TCGLabel *l = gen_new_label();
     TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
     TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
-    target_ulong next_pc;
 
     if (get_xl(ctx) == MXL_RV128) {
         TCGv src1h = get_gprh(ctx, a->rs1);
@@ -175,11 +174,10 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 
     gen_set_label(l); /* branch taken */
 
-    next_pc = ctx->base.pc_next + a->imm;
-    if (!ctx->cfg_ptr->ext_zca && (next_pc & 0x3)) {
+    if (!ctx->cfg_ptr->ext_zca && (a->imm & 0x3)) {
         /* misaligned */
         TCGv target_pc = tcg_temp_new();
-        gen_pc_plus_diff(target_pc, ctx, next_pc);
+        gen_pc_plus_diff(target_pc, ctx, a->imm);
         gen_exception_inst_addr_mis(ctx, target_pc);
     } else {
         gen_goto_tb(ctx, 0, a->imm);
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index 5732d782f7..450b79dcbc 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -297,7 +297,7 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
      * Update pc to current for the non-unwinding exception
      * that might come from cpu_ld*_code() in the helper.
      */
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_update_pc(ctx, 0);
     gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index));
 
     /* c.jt vs c.jalt depends on the index. */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b01aa48f04..c6ae489788 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -224,8 +224,10 @@ static void decode_save_opc(DisasContext *ctx)
 }
 
 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
-                             target_ulong dest)
+                             target_long diff)
 {
+    target_ulong dest = ctx->base.pc_next + diff;
+
     if (get_xl(ctx) == MXL_RV32) {
         dest = (int32_t)dest;
     }
@@ -234,7 +236,7 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
 
 static void gen_update_pc(DisasContext *ctx, target_long diff)
 {
-    gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
+    gen_pc_plus_diff(cpu_pc, ctx, diff);
 }
 
 static void generate_exception(DisasContext *ctx, int excp)
@@ -545,14 +547,11 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
 
 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 {
-    target_ulong next_pc;
-
     /* check misaligned: */
-    next_pc = ctx->base.pc_next + imm;
     if (!ctx->cfg_ptr->ext_zca) {
-        if ((next_pc & 0x3) != 0) {
+        if ((imm & 0x3) != 0) {
             TCGv target_pc = tcg_temp_new();
-            gen_pc_plus_diff(target_pc, ctx, next_pc);
+            gen_pc_plus_diff(target_pc, ctx, imm);
             gen_exception_inst_addr_mis(ctx, target_pc);
             return;
         }
-- 
2.25.1

Re: [PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff

[Richard Henderson]

On 5/23/23 06:59, Weiwei Li wrote:
> Reduce reliance on absolute values by using true pc difference for
> gen_pc_plus_diff() to prepare for PC-relative translation.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/insn_trans/trans_rvi.c.inc   |  6 ++----
>   target/riscv/insn_trans/trans_rvzce.c.inc |  2 +-
>   target/riscv/translate.c                  | 13 ++++++-------
>   3 files changed, 9 insertions(+), 12 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff

[Alistair Francis]

On Wed, May 24, 2023 at 12:14 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Reduce reliance on absolute values by using true pc difference for
> gen_pc_plus_diff() to prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvi.c.inc   |  6 ++----
>  target/riscv/insn_trans/trans_rvzce.c.inc |  2 +-
>  target/riscv/translate.c                  | 13 ++++++-------
>  3 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index f9f4d25cda..d6eef67b45 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -158,7 +158,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>      TCGLabel *l = gen_new_label();
>      TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
>      TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
> -    target_ulong next_pc;
>
>      if (get_xl(ctx) == MXL_RV128) {
>          TCGv src1h = get_gprh(ctx, a->rs1);
> @@ -175,11 +174,10 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>
>      gen_set_label(l); /* branch taken */
>
> -    next_pc = ctx->base.pc_next + a->imm;
> -    if (!ctx->cfg_ptr->ext_zca && (next_pc & 0x3)) {
> +    if (!ctx->cfg_ptr->ext_zca && (a->imm & 0x3)) {
>          /* misaligned */
>          TCGv target_pc = tcg_temp_new();
> -        gen_pc_plus_diff(target_pc, ctx, next_pc);
> +        gen_pc_plus_diff(target_pc, ctx, a->imm);
>          gen_exception_inst_addr_mis(ctx, target_pc);
>      } else {
>          gen_goto_tb(ctx, 0, a->imm);
> diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
> index 5732d782f7..450b79dcbc 100644
> --- a/target/riscv/insn_trans/trans_rvzce.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzce.c.inc
> @@ -297,7 +297,7 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
>       * Update pc to current for the non-unwinding exception
>       * that might come from cpu_ld*_code() in the helper.
>       */
> -    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> +    gen_update_pc(ctx, 0);
>      gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index));
>
>      /* c.jt vs c.jalt depends on the index. */
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index b01aa48f04..c6ae489788 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -224,8 +224,10 @@ static void decode_save_opc(DisasContext *ctx)
>  }
>
>  static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
> -                             target_ulong dest)
> +                             target_long diff)
>  {
> +    target_ulong dest = ctx->base.pc_next + diff;
> +
>      if (get_xl(ctx) == MXL_RV32) {
>          dest = (int32_t)dest;
>      }
> @@ -234,7 +236,7 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
>
>  static void gen_update_pc(DisasContext *ctx, target_long diff)
>  {
> -    gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
> +    gen_pc_plus_diff(cpu_pc, ctx, diff);
>  }
>
>  static void generate_exception(DisasContext *ctx, int excp)
> @@ -545,14 +547,11 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
>
>  static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>  {
> -    target_ulong next_pc;
> -
>      /* check misaligned: */
> -    next_pc = ctx->base.pc_next + imm;
>      if (!ctx->cfg_ptr->ext_zca) {
> -        if ((next_pc & 0x3) != 0) {
> +        if ((imm & 0x3) != 0) {
>              TCGv target_pc = tcg_temp_new();
> -            gen_pc_plus_diff(target_pc, ctx, next_pc);
> +            gen_pc_plus_diff(target_pc, ctx, imm);
>              gen_exception_inst_addr_mis(ctx, target_pc);
>              return;
>          }
> --
> 2.25.1
>
>

[PATCH v2 6/7] target/riscv: Enable PC-relative translation

[Weiwei Li]

Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c                        | 31 ++++++++++-----
 target/riscv/insn_trans/trans_rvi.c.inc   | 12 +++++-
 target/riscv/insn_trans/trans_rvzce.c.inc |  4 +-
 target/riscv/translate.c                  | 47 +++++++++++++++++++----
 4 files changed, 74 insertions(+), 20 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db0875fb43..e4606c0b2e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -690,16 +690,18 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
                                           const TranslationBlock *tb)
 {
-    RISCVCPU *cpu = RISCV_CPU(cs);
-    CPURISCVState *env = &cpu->env;
-    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+    if (!(tb_cflags(tb) & CF_PCREL)) {
+        RISCVCPU *cpu = RISCV_CPU(cs);
+        CPURISCVState *env = &cpu->env;
+        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 
-    tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
 
-    if (xl == MXL_RV32) {
-        env->pc = (int32_t) tb->pc;
-    } else {
-        env->pc = tb->pc;
+        if (xl == MXL_RV32) {
+            env->pc = (int32_t) tb->pc;
+        } else {
+            env->pc = tb->pc;
+        }
     }
 }
 
@@ -725,11 +727,18 @@ static void riscv_restore_state_to_opc(CPUState *cs,
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
     RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+    target_ulong pc;
+
+    if (tb_cflags(tb) & CF_PCREL) {
+        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+    } else {
+        pc = data[0];
+    }
 
     if (xl == MXL_RV32) {
-        env->pc = (int32_t)data[0];
+        env->pc = (int32_t)pc;
     } else {
-        env->pc = data[0];
+        env->pc = pc;
     }
     env->bins = data[1];
 }
@@ -1246,6 +1255,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
 
 #ifndef CONFIG_USER_ONLY
+    cs->tcg_cflags |= CF_PCREL;
+
     if (cpu->cfg.ext_sstc) {
         riscv_timer_init(cpu);
     }
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d6eef67b45..28fe69c34b 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -38,7 +38,9 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
 
 static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
 {
-    gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
+    TCGv target_pc = dest_gpr(ctx, a->rd);
+    gen_pc_plus_diff(target_pc, ctx, a->imm);
+    gen_set_gpr(ctx, a->rd, target_pc);
     return true;
 }
 
@@ -52,6 +54,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
     TCGLabel *misaligned = NULL;
     TCGv target_pc = tcg_temp_new();
+    TCGv succ_pc = dest_gpr(ctx, a->rd);
 
     tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
     tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
@@ -68,7 +71,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
         tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
     }
 
-    gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
+    gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
+    gen_set_gpr(ctx, a->rd, succ_pc);
+
     tcg_gen_mov_tl(cpu_pc, target_pc);
     lookup_and_goto_ptr(ctx);
 
@@ -158,6 +163,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     TCGLabel *l = gen_new_label();
     TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
     TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
+    target_ulong orig_pc_save = ctx->pc_save;
 
     if (get_xl(ctx) == MXL_RV128) {
         TCGv src1h = get_gprh(ctx, a->rs1);
@@ -171,6 +177,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
         tcg_gen_brcond_tl(cond, src1, src2, l);
     }
     gen_goto_tb(ctx, 1, ctx->cur_insn_len);
+    ctx->pc_save = orig_pc_save;
 
     gen_set_label(l); /* branch taken */
 
@@ -182,6 +189,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     } else {
         gen_goto_tb(ctx, 0, a->imm);
     }
+    ctx->pc_save = -1;
     ctx->base.is_jmp = DISAS_NORETURN;
 
     return true;
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index 450b79dcbc..8d8a64f493 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -302,7 +302,9 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
 
     /* c.jt vs c.jalt depends on the index. */
     if (a->index >= 32) {
-        gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
+        TCGv succ_pc = dest_gpr(ctx, xRA);
+        gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
+        gen_set_gpr(ctx, xRA, succ_pc);
     }
 
     tcg_gen_lookup_and_goto_ptr();
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c6ae489788..538187f93b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -60,6 +60,7 @@ typedef struct DisasContext {
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
     target_ulong cur_insn_len;
+    target_ulong pc_save;
     target_ulong priv_ver;
     RISCVMXL misa_mxl_max;
     RISCVMXL xl;
@@ -228,15 +229,24 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
 {
     target_ulong dest = ctx->base.pc_next + diff;
 
-    if (get_xl(ctx) == MXL_RV32) {
-        dest = (int32_t)dest;
+    assert(ctx->pc_save != -1);
+    if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+        tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save);
+        if (get_xl(ctx) == MXL_RV32) {
+            tcg_gen_ext32s_tl(target, target);
+        }
+    } else {
+        if (get_xl(ctx) == MXL_RV32) {
+            dest = (int32_t)dest;
+        }
+        tcg_gen_movi_tl(target, dest);
     }
-    tcg_gen_movi_tl(target, dest);
 }
 
 static void gen_update_pc(DisasContext *ctx, target_long diff)
 {
     gen_pc_plus_diff(cpu_pc, ctx, diff);
+    ctx->pc_save = ctx->base.pc_next + diff;
 }
 
 static void generate_exception(DisasContext *ctx, int excp)
@@ -292,8 +302,21 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
       * direct block chain benefits will be small.
       */
     if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
-        tcg_gen_goto_tb(n);
-        gen_update_pc(ctx, diff);
+        /*
+         * For pcrel, the pc must always be up-to-date on entry to
+         * the linked TB, so that it can use simple additions for all
+         * further adjustments.  For !pcrel, the linked TB is compiled
+         * to know its full virtual address, so we can delay the
+         * update to pc to the unlinked path.  A long chain of links
+         * can thus avoid many updates to the PC.
+         */
+        if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+            gen_update_pc(ctx, diff);
+            tcg_gen_goto_tb(n);
+        } else {
+            tcg_gen_goto_tb(n);
+            gen_update_pc(ctx, diff);
+        }
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
         gen_update_pc(ctx, diff);
@@ -547,6 +570,8 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
 
 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 {
+    TCGv succ_pc = dest_gpr(ctx, rd);
+
     /* check misaligned: */
     if (!ctx->cfg_ptr->ext_zca) {
         if ((imm & 0x3) != 0) {
@@ -557,7 +582,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
         }
     }
 
-    gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
+    gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
+    gen_set_gpr(ctx, rd, succ_pc);
+
     gen_goto_tb(ctx, 0, imm); /* must use this for safety */
     ctx->base.is_jmp = DISAS_NORETURN;
 }
@@ -1154,6 +1181,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     RISCVCPU *cpu = RISCV_CPU(cs);
     uint32_t tb_flags = ctx->base.tb->flags;
 
+    ctx->pc_save = ctx->base.pc_first;
     ctx->pc_succ_insn = ctx->base.pc_first;
     ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
     ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
@@ -1189,8 +1217,13 @@ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
+    target_ulong pc_next = ctx->base.pc_next;
+
+    if (tb_cflags(dcbase->tb) & CF_PCREL) {
+        pc_next &= ~TARGET_PAGE_MASK;
+    }
 
-    tcg_gen_insn_start(ctx->base.pc_next, 0);
+    tcg_gen_insn_start(pc_next, 0);
     ctx->insn_start = tcg_last_op();
 }
 
-- 
2.25.1

Re: [PATCH v2 6/7] target/riscv: Enable PC-relative translation

[Richard Henderson]

On 5/23/23 06:59, Weiwei Li wrote:
> Add a base pc_save for PC-relative translation(CF_PCREL).
> Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
> Use gen_pc_plus_diff to get the pc-relative address.
> Enable CF_PCREL in System mode.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/cpu.c                        | 31 ++++++++++-----
>   target/riscv/insn_trans/trans_rvi.c.inc   | 12 +++++-
>   target/riscv/insn_trans/trans_rvzce.c.inc |  4 +-
>   target/riscv/translate.c                  | 47 +++++++++++++++++++----
>   4 files changed, 74 insertions(+), 20 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 6/7] target/riscv: Enable PC-relative translation

[Alistair Francis]

On Wed, May 24, 2023 at 12:12 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Add a base pc_save for PC-relative translation(CF_PCREL).
> Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
> Use gen_pc_plus_diff to get the pc-relative address.
> Enable CF_PCREL in System mode.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c                        | 31 ++++++++++-----
>  target/riscv/insn_trans/trans_rvi.c.inc   | 12 +++++-
>  target/riscv/insn_trans/trans_rvzce.c.inc |  4 +-
>  target/riscv/translate.c                  | 47 +++++++++++++++++++----
>  4 files changed, 74 insertions(+), 20 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db0875fb43..e4606c0b2e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -690,16 +690,18 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
>  static void riscv_cpu_synchronize_from_tb(CPUState *cs,
>                                            const TranslationBlock *tb)
>  {
> -    RISCVCPU *cpu = RISCV_CPU(cs);
> -    CPURISCVState *env = &cpu->env;
> -    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> +    if (!(tb_cflags(tb) & CF_PCREL)) {
> +        RISCVCPU *cpu = RISCV_CPU(cs);
> +        CPURISCVState *env = &cpu->env;
> +        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
>
> -    tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> +        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
>
> -    if (xl == MXL_RV32) {
> -        env->pc = (int32_t) tb->pc;
> -    } else {
> -        env->pc = tb->pc;
> +        if (xl == MXL_RV32) {
> +            env->pc = (int32_t) tb->pc;
> +        } else {
> +            env->pc = tb->pc;
> +        }
>      }
>  }
>
> @@ -725,11 +727,18 @@ static void riscv_restore_state_to_opc(CPUState *cs,
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;
>      RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> +    target_ulong pc;
> +
> +    if (tb_cflags(tb) & CF_PCREL) {
> +        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
> +    } else {
> +        pc = data[0];
> +    }
>
>      if (xl == MXL_RV32) {
> -        env->pc = (int32_t)data[0];
> +        env->pc = (int32_t)pc;
>      } else {
> -        env->pc = data[0];
> +        env->pc = pc;
>      }
>      env->bins = data[1];
>  }
> @@ -1246,6 +1255,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>
>
>  #ifndef CONFIG_USER_ONLY
> +    cs->tcg_cflags |= CF_PCREL;
> +
>      if (cpu->cfg.ext_sstc) {
>          riscv_timer_init(cpu);
>      }
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index d6eef67b45..28fe69c34b 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -38,7 +38,9 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
>
>  static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
>  {
> -    gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> +    TCGv target_pc = dest_gpr(ctx, a->rd);
> +    gen_pc_plus_diff(target_pc, ctx, a->imm);
> +    gen_set_gpr(ctx, a->rd, target_pc);
>      return true;
>  }
>
> @@ -52,6 +54,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
>  {
>      TCGLabel *misaligned = NULL;
>      TCGv target_pc = tcg_temp_new();
> +    TCGv succ_pc = dest_gpr(ctx, a->rd);
>
>      tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
>      tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
> @@ -68,7 +71,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
>          tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
>      }
>
> -    gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
> +    gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
> +    gen_set_gpr(ctx, a->rd, succ_pc);
> +
>      tcg_gen_mov_tl(cpu_pc, target_pc);
>      lookup_and_goto_ptr(ctx);
>
> @@ -158,6 +163,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>      TCGLabel *l = gen_new_label();
>      TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
>      TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
> +    target_ulong orig_pc_save = ctx->pc_save;
>
>      if (get_xl(ctx) == MXL_RV128) {
>          TCGv src1h = get_gprh(ctx, a->rs1);
> @@ -171,6 +177,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>          tcg_gen_brcond_tl(cond, src1, src2, l);
>      }
>      gen_goto_tb(ctx, 1, ctx->cur_insn_len);
> +    ctx->pc_save = orig_pc_save;
>
>      gen_set_label(l); /* branch taken */
>
> @@ -182,6 +189,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>      } else {
>          gen_goto_tb(ctx, 0, a->imm);
>      }
> +    ctx->pc_save = -1;
>      ctx->base.is_jmp = DISAS_NORETURN;
>
>      return true;
> diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
> index 450b79dcbc..8d8a64f493 100644
> --- a/target/riscv/insn_trans/trans_rvzce.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzce.c.inc
> @@ -302,7 +302,9 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
>
>      /* c.jt vs c.jalt depends on the index. */
>      if (a->index >= 32) {
> -        gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
> +        TCGv succ_pc = dest_gpr(ctx, xRA);
> +        gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
> +        gen_set_gpr(ctx, xRA, succ_pc);
>      }
>
>      tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index c6ae489788..538187f93b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -60,6 +60,7 @@ typedef struct DisasContext {
>      /* pc_succ_insn points to the instruction following base.pc_next */
>      target_ulong pc_succ_insn;
>      target_ulong cur_insn_len;
> +    target_ulong pc_save;
>      target_ulong priv_ver;
>      RISCVMXL misa_mxl_max;
>      RISCVMXL xl;
> @@ -228,15 +229,24 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
>  {
>      target_ulong dest = ctx->base.pc_next + diff;
>
> -    if (get_xl(ctx) == MXL_RV32) {
> -        dest = (int32_t)dest;
> +    assert(ctx->pc_save != -1);
> +    if (tb_cflags(ctx->base.tb) & CF_PCREL) {
> +        tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save);
> +        if (get_xl(ctx) == MXL_RV32) {
> +            tcg_gen_ext32s_tl(target, target);
> +        }
> +    } else {
> +        if (get_xl(ctx) == MXL_RV32) {
> +            dest = (int32_t)dest;
> +        }
> +        tcg_gen_movi_tl(target, dest);
>      }
> -    tcg_gen_movi_tl(target, dest);
>  }
>
>  static void gen_update_pc(DisasContext *ctx, target_long diff)
>  {
>      gen_pc_plus_diff(cpu_pc, ctx, diff);
> +    ctx->pc_save = ctx->base.pc_next + diff;
>  }
>
>  static void generate_exception(DisasContext *ctx, int excp)
> @@ -292,8 +302,21 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
>        * direct block chain benefits will be small.
>        */
>      if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
> -        tcg_gen_goto_tb(n);
> -        gen_update_pc(ctx, diff);
> +        /*
> +         * For pcrel, the pc must always be up-to-date on entry to
> +         * the linked TB, so that it can use simple additions for all
> +         * further adjustments.  For !pcrel, the linked TB is compiled
> +         * to know its full virtual address, so we can delay the
> +         * update to pc to the unlinked path.  A long chain of links
> +         * can thus avoid many updates to the PC.
> +         */
> +        if (tb_cflags(ctx->base.tb) & CF_PCREL) {
> +            gen_update_pc(ctx, diff);
> +            tcg_gen_goto_tb(n);
> +        } else {
> +            tcg_gen_goto_tb(n);
> +            gen_update_pc(ctx, diff);
> +        }
>          tcg_gen_exit_tb(ctx->base.tb, n);
>      } else {
>          gen_update_pc(ctx, diff);
> @@ -547,6 +570,8 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
>
>  static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>  {
> +    TCGv succ_pc = dest_gpr(ctx, rd);
> +
>      /* check misaligned: */
>      if (!ctx->cfg_ptr->ext_zca) {
>          if ((imm & 0x3) != 0) {
> @@ -557,7 +582,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>          }
>      }
>
> -    gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
> +    gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
> +    gen_set_gpr(ctx, rd, succ_pc);
> +
>      gen_goto_tb(ctx, 0, imm); /* must use this for safety */
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
> @@ -1154,6 +1181,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      uint32_t tb_flags = ctx->base.tb->flags;
>
> +    ctx->pc_save = ctx->base.pc_first;
>      ctx->pc_succ_insn = ctx->base.pc_first;
>      ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
>      ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
> @@ -1189,8 +1217,13 @@ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
>  static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
>  {
>      DisasContext *ctx = container_of(dcbase, DisasContext, base);
> +    target_ulong pc_next = ctx->base.pc_next;
> +
> +    if (tb_cflags(dcbase->tb) & CF_PCREL) {
> +        pc_next &= ~TARGET_PAGE_MASK;
> +    }
>
> -    tcg_gen_insn_start(ctx->base.pc_next, 0);
> +    tcg_gen_insn_start(pc_next, 0);
>      ctx->insn_start = tcg_last_op();
>  }
>
> --
> 2.25.1
>
>

[PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext

[Weiwei Li]

pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/translate.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 538187f93b..37d731f9c5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -57,8 +57,6 @@ typedef enum {
 
 typedef struct DisasContext {
     DisasContextBase base;
-    /* pc_succ_insn points to the instruction following base.pc_next */
-    target_ulong pc_succ_insn;
     target_ulong cur_insn_len;
     target_ulong pc_save;
     target_ulong priv_ver;
@@ -1147,7 +1145,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
     /* Check for compressed insn */
     if (ctx->cur_insn_len == 2) {
         ctx->opcode = opcode;
-        ctx->pc_succ_insn = ctx->base.pc_next + 2;
         /*
          * The Zca extension is added as way to refer to instructions in the C
          * extension that do not include the floating-point loads and stores
@@ -1161,7 +1158,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                              translator_lduw(env, &ctx->base,
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
-        ctx->pc_succ_insn = ctx->base.pc_next + 4;
 
         for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
             if (decoders[i].guard_func(ctx) &&
@@ -1182,7 +1178,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     uint32_t tb_flags = ctx->base.tb->flags;
 
     ctx->pc_save = ctx->base.pc_first;
-    ctx->pc_succ_insn = ctx->base.pc_first;
     ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
     ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
     ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
@@ -1235,7 +1230,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 
     ctx->ol = ctx->xl;
     decode_opc(env, ctx, opcode16);
-    ctx->base.pc_next = ctx->pc_succ_insn;
+    ctx->base.pc_next += ctx->cur_insn_len;
 
     /* Only the first insn within a TB is allowed to cross a page boundary. */
     if (ctx->base.is_jmp == DISAS_NEXT) {
-- 
2.25.1

Re: [PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext

[Richard Henderson]

On 5/23/23 06:59, Weiwei Li wrote:
> pc_succ_insn is no longer useful after the introduce of cur_insn_len
> and all pc related value use diff value instead of absolute value.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/translate.c | 7 +------
>   1 file changed, 1 insertion(+), 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext

[Alistair Francis]

On Wed, May 24, 2023 at 12:07 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> pc_succ_insn is no longer useful after the introduce of cur_insn_len
> and all pc related value use diff value instead of absolute value.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 538187f93b..37d731f9c5 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -57,8 +57,6 @@ typedef enum {
>
>  typedef struct DisasContext {
>      DisasContextBase base;
> -    /* pc_succ_insn points to the instruction following base.pc_next */
> -    target_ulong pc_succ_insn;
>      target_ulong cur_insn_len;
>      target_ulong pc_save;
>      target_ulong priv_ver;
> @@ -1147,7 +1145,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
>      /* Check for compressed insn */
>      if (ctx->cur_insn_len == 2) {
>          ctx->opcode = opcode;
> -        ctx->pc_succ_insn = ctx->base.pc_next + 2;
>          /*
>           * The Zca extension is added as way to refer to instructions in the C
>           * extension that do not include the floating-point loads and stores
> @@ -1161,7 +1158,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
>                               translator_lduw(env, &ctx->base,
>                                               ctx->base.pc_next + 2));
>          ctx->opcode = opcode32;
> -        ctx->pc_succ_insn = ctx->base.pc_next + 4;
>
>          for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
>              if (decoders[i].guard_func(ctx) &&
> @@ -1182,7 +1178,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      uint32_t tb_flags = ctx->base.tb->flags;
>
>      ctx->pc_save = ctx->base.pc_first;
> -    ctx->pc_succ_insn = ctx->base.pc_first;
>      ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
>      ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
>      ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
> @@ -1235,7 +1230,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>
>      ctx->ol = ctx->xl;
>      decode_opc(env, ctx, opcode16);
> -    ctx->base.pc_next = ctx->pc_succ_insn;
> +    ctx->base.pc_next += ctx->cur_insn_len;
>
>      /* Only the first insn within a TB is allowed to cross a page boundary. */
>      if (ctx->base.is_jmp == DISAS_NEXT) {
> --
> 2.25.1
>
>

Re: [PATCH v2 0/7] target/riscv: Add support for PC-relative translation

[Alistair Francis]

On Wed, May 24, 2023 at 12:15 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset tries to add support for PC-relative translation.
>
> The existence of CF_PCREL can improve performance with the guest
> kernel's address space randomization.  Each guest process maps libc.so
> (et al) at a different virtual address, and this allows those
> translations to be shared.
>
> And support of PC-relative translation is the precondition to support
> pointer mask for instruction.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-pcrel-upstream-v2
>
> v2:
>  * rebase on upstream and add pc-relative translation for Zc* instructions
>
> Weiwei Li (7):
>   target/riscv: Fix target address to update badaddr
>   target/riscv: Introduce cur_insn_len into DisasContext
>   target/riscv: Change gen_goto_tb to work on displacements
>   target/riscv: Change gen_set_pc_imm to gen_update_pc
>   target/riscv: Use true diff for gen_pc_plus_diff
>   target/riscv: Enable PC-relative translation
>   target/riscv: Remove pc_succ_insn from DisasContext

Thanks for the patches.

Do you mind rebasing on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next ?

Alistair

>
>  target/riscv/cpu.c                            | 31 ++++--
>  .../riscv/insn_trans/trans_privileged.c.inc   |  2 +-
>  target/riscv/insn_trans/trans_rvi.c.inc       | 43 ++++++---
>  target/riscv/insn_trans/trans_rvv.c.inc       |  4 +-
>  target/riscv/insn_trans/trans_rvzawrs.c.inc   |  2 +-
>  target/riscv/insn_trans/trans_rvzce.c.inc     | 10 +-
>  target/riscv/insn_trans/trans_xthead.c.inc    |  2 +-
>  target/riscv/translate.c                      | 94 ++++++++++++-------
>  8 files changed, 123 insertions(+), 65 deletions(-)
>
> --
> 2.25.1
>
>