messages from 2023-05-10 13:51:01 to 2023-05-25 02:43:20 UTC [more...]
[PATCH v4 0/3] Implement the watchdog timer of HiFive 1 rev b
2023-05-25 2:42 UTC (5+ messages)
` [PATCH v4 1/3] hw/misc: sifive_e_aon: Support "
` [PATCH v4 2/3] hw/riscv: sifive_e: "
` [PATCH v4 3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e
[PATCH 0/2] Refresh the dynamic CSR xml after updating the state of the cpu
2023-05-25 2:33 UTC (13+ messages)
` [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml
` [PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu
[PATCH v5] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-05-25 2:24 UTC (2+ messages)
[PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState
2023-05-25 2:21 UTC (17+ messages)
` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions
` [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
` [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
` [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition
` [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size
[PATCH v3] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
2023-05-24 17:33 UTC (3+ messages)
[PATCH v7 0/2] target/riscv: Fix pointer mask related support
2023-05-24 1:59 UTC (3+ messages)
` [PATCH v7 1/2] target/riscv: Fix pointer mask transformation for vector address
` [PATCH v7 2/2] target/riscv: Update cur_pmmask/base when xl changes
[PATCH v2 0/7] target/riscv: Add support for PC-relative translation
2023-05-23 20:43 UTC (14+ messages)
` [PATCH v2 1/7] target/riscv: Fix target address to update badaddr
` [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext
` [PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements
` [PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc
` [PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff
` [PATCH v2 6/7] target/riscv: Enable PC-relative translation
` [PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext
[PATCH v2 0/8] Add support for extension specific disas
2023-05-23 12:15 UTC (10+ messages)
` [PATCH v2 1/8] disas: Change type of disassemble_info.target_info to pointer
` [PATCH v2 2/8] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
` [PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
` [PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions
` [PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions
` [PATCH v2 6/8] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
` [PATCH v2 7/8] disas/riscv.c: Fix lines with over 80 characters
` [PATCH v2 8/8] disas/riscv.c: Remove redundant parentheses
[PATCH v2] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
2023-05-23 9:58 UTC (21+ messages)
[PTACH v2 0/6] Add RISC-V KVM AIA Support
2023-05-23 9:51 UTC (6+ messages)
` [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support
[PATCH v3 0/3] Implement the watchdog timer of HiFive 1 rev b
2023-05-23 7:59 UTC (7+ messages)
` [PATCH v3 1/3] hw/misc: sifive_e_aon: Support "
` [PATCH v3 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e
[PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support
2023-05-22 17:18 UTC (11+ messages)
` [PATCH 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie
` [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST
` [PATCH 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
` [PATCH 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip
` [PATCH 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support
` [PATCH 6/6] target/riscv: Add HS-mode "
[PATCH 0/7] Add support for extension specific disas
2023-05-22 14:30 UTC (20+ messages)
` [PATCH 1/7] disas: Change type of disassemble_info.target_info to pointer
` [PATCH 2/7] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
` [PATCH 3/7] disas/riscv.c: Support disas for Zcm* extensions
` [PATCH 4/7] disas/riscv.c: Support disas for Z*inx extensions
` [PATCH 5/7] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
` [PATCH 6/7] disas/riscv.c: Fix lines with over 80 characters
` [PATCH 7/7] disas/riscv.c: Remove redundant parentheses
[PATCH v3 0/4] target/riscv: Add Smrnmi support
2023-05-22 13:11 UTC (5+ messages)
` [PATCH v3 1/4] target/riscv: Add Smrnmi cpu extension
` [PATCH v3 2/4] target/riscv: Add Smrnmi CSRs
` [PATCH v3 3/4] target/riscv: Handle Smrnmi interrupt and exception
` [PATCH v3 4/4] target/riscv: Add Smrnmi mnret instruction
[PATCH v5 00/11] RISC-V Add the OpenTitan Machine
2023-05-19 17:15 UTC (3+ messages)
` [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
` [PATCH v5 6/11] "
[PATCH v1] dt-bindings: riscv: deprecate riscv,isa
2023-05-18 21:42 UTC (10+ messages)
[PATCH v5 0/3] Smstateen FCSR
2023-05-18 17:50 UTC (4+ messages)
` [PATCH v5 1/3] target/riscv: smstateen check for fcsr
` [PATCH v5 2/3] target/riscv: Reuse tb->flags.FS
` [PATCH v5 3/3] target/riscv: smstateen knobs
[PATCH v6 00/12] target/riscv: Fix PMP related problem
2023-05-18 9:46 UTC (14+ messages)
` [PATCH v6 01/12] target/riscv: Update pmp_get_tlb_size()
` [PATCH v6 02/12] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
` [PATCH v6 03/12] target/riscv: Make the short cut really work in pmp_hart_has_privs
` [PATCH v6 04/12] target/riscv: Change the return type of pmp_hart_has_privs() to bool
` [PATCH v6 05/12] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
` [PATCH v6 06/12] target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
` [PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are changed
` [PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_write()
` [PATCH v6 09/12] target/riscv: Flush TLB when pmpaddr is updated
` [PATCH v6 10/12] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
` [PATCH v6 11/12] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
` [PATCH v6 12/12] target/riscv: Deny access if access is partially inside the PMP entry
[PATCH v9 00/11] target/riscv: rework CPU extension validation
2023-05-18 9:45 UTC (14+ messages)
` [PATCH v9 01/11] target/riscv/cpu.c: add riscv_cpu_validate_v()
` [PATCH v9 02/11] target/riscv/cpu.c: remove set_vext_version()
` [PATCH v9 03/11] target/riscv/cpu.c: remove set_priv_version()
` [PATCH v9 04/11] target/riscv: add PRIV_VERSION_LATEST
` [PATCH v9 05/11] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
` [PATCH v9 06/11] target/riscv: Update check for Zca/Zcf/Zcd
` [PATCH v9 07/11] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
` [PATCH v9 08/11] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
` [PATCH v9 09/11] target/riscv/cpu.c: validate extensions before riscv_timer_init()
` [PATCH v9 10/11] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
` [PATCH v9 11/11] target/riscv: rework write_misa()
[PATCH v4 0/3] Smstateen FCSR
2023-05-18 4:48 UTC (5+ messages)
` [PATCH v4 1/3] target/riscv: smstateen check for fcsr
[PATCH v8 00/11] target/riscv: rework CPU extension validation
2023-05-17 9:43 UTC (8+ messages)
` [PATCH v8 11/11] target/riscv: rework write_misa()
[PATCH v4] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-05-17 4:58 UTC (2+ messages)
[PATCH v5 0/3] NUMA: Apply cluster-NUMA-node boundary for aarch64 and riscv machines
2023-05-17 3:40 UTC (3+ messages)
` [PATCH v5 3/3] hw/riscv: Validate cluster and NUMA node boundary
[PATCH] target/riscv: Move zc* out of the experimental properties
2023-05-17 2:25 UTC (2+ messages)
[PATCH v5 00/13] target/riscv: Fix PMP related problem
2023-05-17 2:23 UTC (21+ messages)
` [PATCH v5 01/13] target/riscv: Update pmp_get_tlb_size()
` [PATCH v5 02/13] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
` [PATCH v5 03/13] target/riscv: Make the short cut really work in pmp_hart_has_privs
` [PATCH v5 04/13] target/riscv: Change the return type of pmp_hart_has_privs() to bool
` [PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
` [PATCH v5 06/13] target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
` [PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are changed
` [PATCH v5 08/13] target/riscv: Update the next rule addr in pmpaddr_csr_write()
` [PATCH v5 12/13] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
` [PATCH v5 13/13] target/riscv: Deny access if access is partially inside the PMP entry
[PATCH v3] hw/riscv/virt: Add a second UART for secure world
2023-05-15 5:14 UTC (4+ messages)
[PATCH v3] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-05-12 12:53 UTC (2+ messages)
Recall: [PATCH v3] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-05-12 7:58 UTC
[PATCH v3] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-05-12 7:56 UTC
[PATCH v2] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-05-12 7:05 UTC (2+ messages)
[PATCH v5 00/30] tcg: Simplify calls to load/store helpers
2023-05-10 14:02 UTC (17+ messages)
` [PATCH v5 23/30] tcg/mips: Simplify constraints on qemu_ld/st
` [PATCH v5 24/30] tcg/ppc: Reorg tcg_out_tlb_read
` [PATCH v5 25/30] tcg/ppc: Adjust constraints on qemu_ld/st
` [PATCH v5 26/30] tcg/ppc: Remove unused constraints A, B, C, D
` [PATCH v5 27/30] tcg/ppc: Remove unused constraint J
` [PATCH v5 28/30] tcg/riscv: Simplify constraints on qemu_ld/st
` [PATCH v5 29/30] tcg/s390x: Use ALGFR in constructing softmmu host address
` [PATCH v5 30/30] tcg/s390x: Simplify constraints on qemu_ld/st
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