* [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState
@ 2023-05-20 5:45 Philippe Mathieu-Daudé
2023-05-20 5:45 ` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions Philippe Mathieu-Daudé
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-20 5:45 UTC (permalink / raw)
To: qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza,
Philippe Mathieu-Daudé
Hi,
This series fix a QOM issue with the OpenTitanState
structure, noticed while auditing QOM relations globally.
All patches are trivial to review.
Regards,
Phil.
Philippe Mathieu-Daudé (5):
hw/riscv/opentitan: Rename machine_[class]_init() functions
hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
hw/riscv/opentitan: Explicit machine type definition
hw/riscv/opentitan: Correct OpenTitanState parent type/size
include/hw/riscv/opentitan.h | 6 +++++-
hw/riscv/opentitan.c | 38 +++++++++++++++++++-----------------
2 files changed, 25 insertions(+), 19 deletions(-)
--
2.38.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions
2023-05-20 5:45 [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Philippe Mathieu-Daudé
@ 2023-05-20 5:45 ` Philippe Mathieu-Daudé
2023-05-22 13:21 ` Daniel Henrique Barboza
2023-05-25 2:13 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
` (4 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-20 5:45 UTC (permalink / raw)
To: qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza,
Philippe Mathieu-Daudé
Follow QOM style which declares FOO_init() as instance
initializer and FOO_class_init() as class initializer:
rename the OpenTitan machine class/instance init()
accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/riscv/opentitan.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index bc678766e7..2d21ee39c5 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -75,7 +75,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
-static void opentitan_board_init(MachineState *machine)
+static void opentitan_machine_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const MemMapEntry *memmap = ibex_memmap;
@@ -108,17 +108,17 @@ static void opentitan_board_init(MachineState *machine)
}
}
-static void opentitan_machine_init(MachineClass *mc)
+static void opentitan_machine_class_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with OpenTitan";
- mc->init = opentitan_board_init;
+ mc->init = opentitan_machine_init;
mc->max_cpus = 1;
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
mc->default_ram_id = "riscv.lowrisc.ibex.ram";
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
-DEFINE_MACHINE("opentitan", opentitan_machine_init)
+DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
static void lowrisc_ibex_soc_init(Object *obj)
{
--
2.38.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
2023-05-20 5:45 [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Philippe Mathieu-Daudé
2023-05-20 5:45 ` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions Philippe Mathieu-Daudé
@ 2023-05-20 5:45 ` Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:15 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Philippe Mathieu-Daudé
` (3 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-20 5:45 UTC (permalink / raw)
To: qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza,
Philippe Mathieu-Daudé
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination. This
is in preparation of adding the OpenTitan machine type to
this array in a pair of commits.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/riscv/opentitan.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 2d21ee39c5..294955eeea 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -320,17 +320,14 @@ static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
-static const TypeInfo lowrisc_ibex_soc_type_info = {
- .name = TYPE_RISCV_IBEX_SOC,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(LowRISCIbexSoCState),
- .instance_init = lowrisc_ibex_soc_init,
- .class_init = lowrisc_ibex_soc_class_init,
+static const TypeInfo open_titan_types[] = {
+ {
+ .name = TYPE_RISCV_IBEX_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(LowRISCIbexSoCState),
+ .instance_init = lowrisc_ibex_soc_init,
+ .class_init = lowrisc_ibex_soc_class_init,
+ }
};
-static void lowrisc_ibex_soc_register_types(void)
-{
- type_register_static(&lowrisc_ibex_soc_type_info);
-}
-
-type_init(lowrisc_ibex_soc_register_types)
+DEFINE_TYPES(open_titan_types)
--
2.38.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
2023-05-20 5:45 [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Philippe Mathieu-Daudé
2023-05-20 5:45 ` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions Philippe Mathieu-Daudé
2023-05-20 5:45 ` [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
@ 2023-05-20 5:45 ` Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:16 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition Philippe Mathieu-Daudé
` (2 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-20 5:45 UTC (permalink / raw)
To: qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza,
Philippe Mathieu-Daudé
QOM type names are usually defined as TYPE_FOO.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index c40b05052a..fd70226ed8 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -53,6 +53,8 @@ struct LowRISCIbexSoCState {
MemoryRegion flash_alias;
};
+#define TYPE_OPENTITAN_MACHINE "opentitan"
+
typedef struct OpenTitanState {
/*< private >*/
SysBusDevice parent_obj;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 294955eeea..7d7159ea30 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -118,7 +118,7 @@ static void opentitan_machine_class_init(MachineClass *mc)
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
-DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
+DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
static void lowrisc_ibex_soc_init(Object *obj)
{
--
2.38.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition
2023-05-20 5:45 [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2023-05-20 5:45 ` [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Philippe Mathieu-Daudé
@ 2023-05-20 5:45 ` Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:18 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size Philippe Mathieu-Daudé
2023-05-25 2:21 ` [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Alistair Francis
5 siblings, 2 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-20 5:45 UTC (permalink / raw)
To: qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza,
Philippe Mathieu-Daudé
Expand the DEFINE_MACHINE() macro, converting the class_init()
handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/riscv/opentitan.h | 3 ++-
hw/riscv/opentitan.c | 10 +++++++---
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index fd70226ed8..806ff73528 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -24,6 +24,7 @@
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "hw/ssi/ibex_spi_host.h"
+#include "hw/boards.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@@ -53,7 +54,7 @@ struct LowRISCIbexSoCState {
MemoryRegion flash_alias;
};
-#define TYPE_OPENTITAN_MACHINE "opentitan"
+#define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
typedef struct OpenTitanState {
/*< private >*/
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 7d7159ea30..9535308197 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -108,8 +108,10 @@ static void opentitan_machine_init(MachineState *machine)
}
}
-static void opentitan_machine_class_init(MachineClass *mc)
+static void opentitan_machine_class_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "RISC-V Board compatible with OpenTitan";
mc->init = opentitan_machine_init;
mc->max_cpus = 1;
@@ -118,8 +120,6 @@ static void opentitan_machine_class_init(MachineClass *mc)
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
-DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
-
static void lowrisc_ibex_soc_init(Object *obj)
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
@@ -327,6 +327,10 @@ static const TypeInfo open_titan_types[] = {
.instance_size = sizeof(LowRISCIbexSoCState),
.instance_init = lowrisc_ibex_soc_init,
.class_init = lowrisc_ibex_soc_class_init,
+ }, {
+ .name = TYPE_OPENTITAN_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = opentitan_machine_class_init,
}
};
--
2.38.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size
2023-05-20 5:45 [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2023-05-20 5:45 ` [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition Philippe Mathieu-Daudé
@ 2023-05-20 5:45 ` Philippe Mathieu-Daudé
2023-05-22 13:27 ` Daniel Henrique Barboza
2023-05-25 2:20 ` Alistair Francis
2023-05-25 2:21 ` [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Alistair Francis
5 siblings, 2 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-20 5:45 UTC (permalink / raw)
To: qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza,
Philippe Mathieu-Daudé
OpenTitanState is the 'machine' (or 'board') state: it isn't
a SysBus device, but inherits from the MachineState type.
Correct the instance size.
Doing so we avoid leaking an OpenTitanState pointer in
opentitan_machine_init().
Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/riscv/opentitan.h | 3 ++-
hw/riscv/opentitan.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 806ff73528..609473d07b 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -55,10 +55,11 @@ struct LowRISCIbexSoCState {
};
#define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
+OBJECT_DECLARE_SIMPLE_TYPE(OpenTitanState, OPENTITAN_MACHINE)
typedef struct OpenTitanState {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent_obj;
/*< public >*/
LowRISCIbexSoCState soc;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 9535308197..6a2fcc4ade 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -78,8 +78,8 @@ static const MemMapEntry ibex_memmap[] = {
static void opentitan_machine_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
+ OpenTitanState *s = OPENTITAN_MACHINE(machine);
const MemMapEntry *memmap = ibex_memmap;
- OpenTitanState *s = g_new0(OpenTitanState, 1);
MemoryRegion *sys_mem = get_system_memory();
if (machine->ram_size != mc->default_ram_size) {
@@ -330,6 +330,7 @@ static const TypeInfo open_titan_types[] = {
}, {
.name = TYPE_OPENTITAN_MACHINE,
.parent = TYPE_MACHINE,
+ .instance_size = sizeof(OpenTitanState),
.class_init = opentitan_machine_class_init,
}
};
--
2.38.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions
2023-05-20 5:45 ` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions Philippe Mathieu-Daudé
@ 2023-05-22 13:21 ` Daniel Henrique Barboza
2023-05-25 2:13 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-05-22 13:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv
On 5/20/23 02:45, Philippe Mathieu-Daudé wrote:
> Follow QOM style which declares FOO_init() as instance
> initializer and FOO_class_init() as class initializer:
> rename the OpenTitan machine class/instance init()
> accordingly.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/riscv/opentitan.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index bc678766e7..2d21ee39c5 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -75,7 +75,7 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
> };
>
> -static void opentitan_board_init(MachineState *machine)
> +static void opentitan_machine_init(MachineState *machine)
> {
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = ibex_memmap;
> @@ -108,17 +108,17 @@ static void opentitan_board_init(MachineState *machine)
> }
> }
>
> -static void opentitan_machine_init(MachineClass *mc)
> +static void opentitan_machine_class_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Board compatible with OpenTitan";
> - mc->init = opentitan_board_init;
> + mc->init = opentitan_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> mc->default_ram_id = "riscv.lowrisc.ibex.ram";
> mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> -DEFINE_MACHINE("opentitan", opentitan_machine_init)
> +DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
>
> static void lowrisc_ibex_soc_init(Object *obj)
> {
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
2023-05-20 5:45 ` [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
@ 2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:15 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-05-22 13:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv
On 5/20/23 02:45, Philippe Mathieu-Daudé wrote:
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. Replace
> the type_init() / type_register_static() combination. This
> is in preparation of adding the OpenTitan machine type to
> this array in a pair of commits.
I wonder whether we should forbid type_init()/type_register_static() and
force everyone to use DEFINE_TYPES(). We need less options when dealing
with QOM.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/riscv/opentitan.c | 21 +++++++++------------
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 2d21ee39c5..294955eeea 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -320,17 +320,14 @@ static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
> }
>
> -static const TypeInfo lowrisc_ibex_soc_type_info = {
> - .name = TYPE_RISCV_IBEX_SOC,
> - .parent = TYPE_DEVICE,
> - .instance_size = sizeof(LowRISCIbexSoCState),
> - .instance_init = lowrisc_ibex_soc_init,
> - .class_init = lowrisc_ibex_soc_class_init,
> +static const TypeInfo open_titan_types[] = {
> + {
> + .name = TYPE_RISCV_IBEX_SOC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(LowRISCIbexSoCState),
> + .instance_init = lowrisc_ibex_soc_init,
> + .class_init = lowrisc_ibex_soc_class_init,
> + }
> };
>
> -static void lowrisc_ibex_soc_register_types(void)
> -{
> - type_register_static(&lowrisc_ibex_soc_type_info);
> -}
> -
> -type_init(lowrisc_ibex_soc_register_types)
> +DEFINE_TYPES(open_titan_types)
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
2023-05-20 5:45 ` [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Philippe Mathieu-Daudé
@ 2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:16 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-05-22 13:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv
On 5/20/23 02:45, Philippe Mathieu-Daudé wrote:
> QOM type names are usually defined as TYPE_FOO.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> include/hw/riscv/opentitan.h | 2 ++
> hw/riscv/opentitan.c | 2 +-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index c40b05052a..fd70226ed8 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -53,6 +53,8 @@ struct LowRISCIbexSoCState {
> MemoryRegion flash_alias;
> };
>
> +#define TYPE_OPENTITAN_MACHINE "opentitan"
> +
> typedef struct OpenTitanState {
> /*< private >*/
> SysBusDevice parent_obj;
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 294955eeea..7d7159ea30 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -118,7 +118,7 @@ static void opentitan_machine_class_init(MachineClass *mc)
> mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> -DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
> +DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
>
> static void lowrisc_ibex_soc_init(Object *obj)
> {
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition
2023-05-20 5:45 ` [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition Philippe Mathieu-Daudé
@ 2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:18 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-05-22 13:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv
On 5/20/23 02:45, Philippe Mathieu-Daudé wrote:
> Expand the DEFINE_MACHINE() macro, converting the class_init()
> handler.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> include/hw/riscv/opentitan.h | 3 ++-
> hw/riscv/opentitan.c | 10 +++++++---
> 2 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index fd70226ed8..806ff73528 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -24,6 +24,7 @@
> #include "hw/char/ibex_uart.h"
> #include "hw/timer/ibex_timer.h"
> #include "hw/ssi/ibex_spi_host.h"
> +#include "hw/boards.h"
> #include "qom/object.h"
>
> #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
> @@ -53,7 +54,7 @@ struct LowRISCIbexSoCState {
> MemoryRegion flash_alias;
> };
>
> -#define TYPE_OPENTITAN_MACHINE "opentitan"
> +#define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
>
> typedef struct OpenTitanState {
> /*< private >*/
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 7d7159ea30..9535308197 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -108,8 +108,10 @@ static void opentitan_machine_init(MachineState *machine)
> }
> }
>
> -static void opentitan_machine_class_init(MachineClass *mc)
> +static void opentitan_machine_class_init(ObjectClass *oc, void *data)
> {
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> mc->desc = "RISC-V Board compatible with OpenTitan";
> mc->init = opentitan_machine_init;
> mc->max_cpus = 1;
> @@ -118,8 +120,6 @@ static void opentitan_machine_class_init(MachineClass *mc)
> mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> -DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
> -
> static void lowrisc_ibex_soc_init(Object *obj)
> {
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
> @@ -327,6 +327,10 @@ static const TypeInfo open_titan_types[] = {
> .instance_size = sizeof(LowRISCIbexSoCState),
> .instance_init = lowrisc_ibex_soc_init,
> .class_init = lowrisc_ibex_soc_class_init,
> + }, {
> + .name = TYPE_OPENTITAN_MACHINE,
> + .parent = TYPE_MACHINE,
> + .class_init = opentitan_machine_class_init,
> }
> };
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size
2023-05-20 5:45 ` [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size Philippe Mathieu-Daudé
@ 2023-05-22 13:27 ` Daniel Henrique Barboza
2023-05-25 2:20 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-05-22 13:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv
On 5/20/23 02:45, Philippe Mathieu-Daudé wrote:
> OpenTitanState is the 'machine' (or 'board') state: it isn't
> a SysBus device, but inherits from the MachineState type.
> Correct the instance size.
> Doing so we avoid leaking an OpenTitanState pointer in
> opentitan_machine_init().
>
> Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> include/hw/riscv/opentitan.h | 3 ++-
> hw/riscv/opentitan.c | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 806ff73528..609473d07b 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -55,10 +55,11 @@ struct LowRISCIbexSoCState {
> };
>
> #define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
> +OBJECT_DECLARE_SIMPLE_TYPE(OpenTitanState, OPENTITAN_MACHINE)
>
> typedef struct OpenTitanState {
> /*< private >*/
> - SysBusDevice parent_obj;
> + MachineState parent_obj;
>
> /*< public >*/
> LowRISCIbexSoCState soc;
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 9535308197..6a2fcc4ade 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -78,8 +78,8 @@ static const MemMapEntry ibex_memmap[] = {
> static void opentitan_machine_init(MachineState *machine)
> {
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> + OpenTitanState *s = OPENTITAN_MACHINE(machine);
> const MemMapEntry *memmap = ibex_memmap;
> - OpenTitanState *s = g_new0(OpenTitanState, 1);
> MemoryRegion *sys_mem = get_system_memory();
>
> if (machine->ram_size != mc->default_ram_size) {
> @@ -330,6 +330,7 @@ static const TypeInfo open_titan_types[] = {
> }, {
> .name = TYPE_OPENTITAN_MACHINE,
> .parent = TYPE_MACHINE,
> + .instance_size = sizeof(OpenTitanState),
> .class_init = opentitan_machine_class_init,
> }
> };
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions
2023-05-20 5:45 ` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions Philippe Mathieu-Daudé
2023-05-22 13:21 ` Daniel Henrique Barboza
@ 2023-05-25 2:13 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2023-05-25 2:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Follow QOM style which declares FOO_init() as instance
> initializer and FOO_class_init() as class initializer:
> rename the OpenTitan machine class/instance init()
> accordingly.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/opentitan.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index bc678766e7..2d21ee39c5 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -75,7 +75,7 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
> };
>
> -static void opentitan_board_init(MachineState *machine)
> +static void opentitan_machine_init(MachineState *machine)
> {
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = ibex_memmap;
> @@ -108,17 +108,17 @@ static void opentitan_board_init(MachineState *machine)
> }
> }
>
> -static void opentitan_machine_init(MachineClass *mc)
> +static void opentitan_machine_class_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Board compatible with OpenTitan";
> - mc->init = opentitan_board_init;
> + mc->init = opentitan_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> mc->default_ram_id = "riscv.lowrisc.ibex.ram";
> mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> -DEFINE_MACHINE("opentitan", opentitan_machine_init)
> +DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
>
> static void lowrisc_ibex_soc_init(Object *obj)
> {
> --
> 2.38.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
2023-05-20 5:45 ` [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
@ 2023-05-25 2:15 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2023-05-25 2:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza
On Sat, May 20, 2023 at 3:46 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. Replace
> the type_init() / type_register_static() combination. This
> is in preparation of adding the OpenTitan machine type to
> this array in a pair of commits.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/opentitan.c | 21 +++++++++------------
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 2d21ee39c5..294955eeea 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -320,17 +320,14 @@ static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
> }
>
> -static const TypeInfo lowrisc_ibex_soc_type_info = {
> - .name = TYPE_RISCV_IBEX_SOC,
> - .parent = TYPE_DEVICE,
> - .instance_size = sizeof(LowRISCIbexSoCState),
> - .instance_init = lowrisc_ibex_soc_init,
> - .class_init = lowrisc_ibex_soc_class_init,
> +static const TypeInfo open_titan_types[] = {
> + {
> + .name = TYPE_RISCV_IBEX_SOC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(LowRISCIbexSoCState),
> + .instance_init = lowrisc_ibex_soc_init,
> + .class_init = lowrisc_ibex_soc_class_init,
> + }
> };
>
> -static void lowrisc_ibex_soc_register_types(void)
> -{
> - type_register_static(&lowrisc_ibex_soc_type_info);
> -}
> -
> -type_init(lowrisc_ibex_soc_register_types)
> +DEFINE_TYPES(open_titan_types)
> --
> 2.38.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
2023-05-20 5:45 ` [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
@ 2023-05-25 2:16 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2023-05-25 2:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza
On Sat, May 20, 2023 at 3:46 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> QOM type names are usually defined as TYPE_FOO.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/riscv/opentitan.h | 2 ++
> hw/riscv/opentitan.c | 2 +-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index c40b05052a..fd70226ed8 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -53,6 +53,8 @@ struct LowRISCIbexSoCState {
> MemoryRegion flash_alias;
> };
>
> +#define TYPE_OPENTITAN_MACHINE "opentitan"
> +
> typedef struct OpenTitanState {
> /*< private >*/
> SysBusDevice parent_obj;
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 294955eeea..7d7159ea30 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -118,7 +118,7 @@ static void opentitan_machine_class_init(MachineClass *mc)
> mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> -DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
> +DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
>
> static void lowrisc_ibex_soc_init(Object *obj)
> {
> --
> 2.38.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition
2023-05-20 5:45 ` [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
@ 2023-05-25 2:18 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2023-05-25 2:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Expand the DEFINE_MACHINE() macro, converting the class_init()
> handler.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/riscv/opentitan.h | 3 ++-
> hw/riscv/opentitan.c | 10 +++++++---
> 2 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index fd70226ed8..806ff73528 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -24,6 +24,7 @@
> #include "hw/char/ibex_uart.h"
> #include "hw/timer/ibex_timer.h"
> #include "hw/ssi/ibex_spi_host.h"
> +#include "hw/boards.h"
> #include "qom/object.h"
>
> #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
> @@ -53,7 +54,7 @@ struct LowRISCIbexSoCState {
> MemoryRegion flash_alias;
> };
>
> -#define TYPE_OPENTITAN_MACHINE "opentitan"
> +#define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
>
> typedef struct OpenTitanState {
> /*< private >*/
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 7d7159ea30..9535308197 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -108,8 +108,10 @@ static void opentitan_machine_init(MachineState *machine)
> }
> }
>
> -static void opentitan_machine_class_init(MachineClass *mc)
> +static void opentitan_machine_class_init(ObjectClass *oc, void *data)
> {
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> mc->desc = "RISC-V Board compatible with OpenTitan";
> mc->init = opentitan_machine_init;
> mc->max_cpus = 1;
> @@ -118,8 +120,6 @@ static void opentitan_machine_class_init(MachineClass *mc)
> mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
> }
>
> -DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
> -
> static void lowrisc_ibex_soc_init(Object *obj)
> {
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
> @@ -327,6 +327,10 @@ static const TypeInfo open_titan_types[] = {
> .instance_size = sizeof(LowRISCIbexSoCState),
> .instance_init = lowrisc_ibex_soc_init,
> .class_init = lowrisc_ibex_soc_class_init,
> + }, {
> + .name = TYPE_OPENTITAN_MACHINE,
> + .parent = TYPE_MACHINE,
> + .class_init = opentitan_machine_class_init,
> }
> };
>
> --
> 2.38.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size
2023-05-20 5:45 ` [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size Philippe Mathieu-Daudé
2023-05-22 13:27 ` Daniel Henrique Barboza
@ 2023-05-25 2:20 ` Alistair Francis
1 sibling, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2023-05-25 2:20 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> OpenTitanState is the 'machine' (or 'board') state: it isn't
> a SysBus device, but inherits from the MachineState type.
> Correct the instance size.
> Doing so we avoid leaking an OpenTitanState pointer in
> opentitan_machine_init().
>
> Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/riscv/opentitan.h | 3 ++-
> hw/riscv/opentitan.c | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 806ff73528..609473d07b 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -55,10 +55,11 @@ struct LowRISCIbexSoCState {
> };
>
> #define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
> +OBJECT_DECLARE_SIMPLE_TYPE(OpenTitanState, OPENTITAN_MACHINE)
>
> typedef struct OpenTitanState {
> /*< private >*/
> - SysBusDevice parent_obj;
> + MachineState parent_obj;
>
> /*< public >*/
> LowRISCIbexSoCState soc;
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 9535308197..6a2fcc4ade 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -78,8 +78,8 @@ static const MemMapEntry ibex_memmap[] = {
> static void opentitan_machine_init(MachineState *machine)
> {
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> + OpenTitanState *s = OPENTITAN_MACHINE(machine);
> const MemMapEntry *memmap = ibex_memmap;
> - OpenTitanState *s = g_new0(OpenTitanState, 1);
> MemoryRegion *sys_mem = get_system_memory();
>
> if (machine->ram_size != mc->default_ram_size) {
> @@ -330,6 +330,7 @@ static const TypeInfo open_titan_types[] = {
> }, {
> .name = TYPE_OPENTITAN_MACHINE,
> .parent = TYPE_MACHINE,
> + .instance_size = sizeof(OpenTitanState),
> .class_init = opentitan_machine_class_init,
> }
> };
> --
> 2.38.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState
2023-05-20 5:45 [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2023-05-20 5:45 ` [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size Philippe Mathieu-Daudé
@ 2023-05-25 2:21 ` Alistair Francis
5 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2023-05-25 2:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Liu Zhiwei, Palmer Dabbelt, Weiwei Li, Bin Meng,
Alistair Francis, qemu-riscv, Daniel Henrique Barboza
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Hi,
>
> This series fix a QOM issue with the OpenTitanState
> structure, noticed while auditing QOM relations globally.
>
> All patches are trivial to review.
>
> Regards,
>
> Phil.
>
> Philippe Mathieu-Daudé (5):
> hw/riscv/opentitan: Rename machine_[class]_init() functions
> hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
> hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
> hw/riscv/opentitan: Explicit machine type definition
> hw/riscv/opentitan: Correct OpenTitanState parent type/size
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> include/hw/riscv/opentitan.h | 6 +++++-
> hw/riscv/opentitan.c | 38 +++++++++++++++++++-----------------
> 2 files changed, 25 insertions(+), 19 deletions(-)
>
> --
> 2.38.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
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2023-05-20 5:45 [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Philippe Mathieu-Daudé
2023-05-20 5:45 ` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions Philippe Mathieu-Daudé
2023-05-22 13:21 ` Daniel Henrique Barboza
2023-05-25 2:13 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:15 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:16 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition Philippe Mathieu-Daudé
2023-05-22 13:26 ` Daniel Henrique Barboza
2023-05-25 2:18 ` Alistair Francis
2023-05-20 5:45 ` [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size Philippe Mathieu-Daudé
2023-05-22 13:27 ` Daniel Henrique Barboza
2023-05-25 2:20 ` Alistair Francis
2023-05-25 2:21 ` [PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState Alistair Francis
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