messages from 2023-05-18 14:06:55 to 2023-05-30 13:19:14 UTC [more...]
[PATCH 0/9] disas/riscv: Add vendor extension support
2023-05-30 13:18 UTC (2+ messages)
` [PATCH 2/9] target/riscv: Factor out RISCVCPUConfig from cpu.h
[PATCH 0/4] target/riscv: Fix mstatus related problems
2023-05-29 12:17 UTC (5+ messages)
` [PATCH 1/4] target/riscv: Make MPV only work when MPP != PRV_M
` [PATCH 2/4] target/riscv: Remove check on mode for MPRV
` [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
` [PATCH 4/4] target/riscv: Remove redundant assignment to SXL
[PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support
2023-05-26 16:30 UTC (9+ messages)
` [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST
` [PATCH 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
` [PATCH 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support
[PATCH v2 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support
2023-05-26 16:23 UTC (7+ messages)
` [PATCH v2 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie
` [PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST
` [PATCH v2 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
` [PATCH v2 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip
` [PATCH v2 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support
` [PATCH v2 6/6] target/riscv: Add HS-mode "
[PATCH v5 0/3] hw/riscv/virt: pflash improvements
2023-05-26 14:04 UTC (7+ messages)
` [PATCH v5 1/3] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
` [PATCH v5 2/3] riscv/virt: Support using pflash via -blockdev option
` [PATCH v5 3/3] docs/system: riscv: Add pflash usage details
[PATCH v4 0/3] hw/riscv/virt: pflash improvements
2023-05-26 10:20 UTC (14+ messages)
` [PATCH v4 1/3] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
` [PATCH v4 2/3] riscv/virt: Support using pflash via -blockdev option
` [PATCH v4 3/3] docs/system: riscv: Add pflash usage details
[PATCH v3 0/7] target/riscv: Add support for PC-relative translation
2023-05-26 7:21 UTC (8+ messages)
` [PATCH v3 1/7] target/riscv: Fix target address to update badaddr
` [PATCH v3 2/7] target/riscv: Introduce cur_insn_len into DisasContext
` [PATCH v3 3/7] target/riscv: Change gen_goto_tb to work on displacements
` [PATCH v3 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc
` [PATCH v3 5/7] target/riscv: Use true diff for gen_pc_plus_diff
` [PATCH v3 6/7] target/riscv: Enable PC-relative translation
` [PATCH v3 7/7] target/riscv: Remove pc_succ_insn from DisasContext
[PATCH v3] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
2023-05-26 6:47 UTC (9+ messages)
[PATCH v3 0/6] Add RISC-V KVM AIA Support
2023-05-26 6:25 UTC (7+ messages)
` [PATCH v3 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support placeholder
` [PATCH v3 2/6] target/riscv: support the AIA device emulation with KVM enabled
` [PATCH v3 3/6] target/riscv: check the in-kernel irqchip support
` [PATCH v3 4/6] target/riscv: Create an KVM AIA irqchip
` [PATCH v3 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA
` [PATCH v3 6/6] target/riscv: select KVM AIA in riscv virt machine
[PATCH v2 0/7] target/riscv: Add support for PC-relative translation
2023-05-26 3:38 UTC (21+ messages)
` [PATCH v2 1/7] target/riscv: Fix target address to update badaddr
` [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext
` [PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements
` [PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc
` [PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff
` [PATCH v2 6/7] target/riscv: Enable PC-relative translation
` [PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext
[PATCH v2 0/8] Add support for extension specific disas
2023-05-26 1:35 UTC (19+ messages)
` [PATCH v2 1/8] disas: Change type of disassemble_info.target_info to pointer
` [PATCH v2 2/8] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
` [PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
` [PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions
` [PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions
` [PATCH v2 6/8] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
` [PATCH v2 7/8] disas/riscv.c: Fix lines with over 80 characters
` [PATCH v2 8/8] disas/riscv.c: Remove redundant parentheses
[PATCH v5 0/3] Smstateen FCSR
2023-05-26 1:13 UTC (7+ messages)
` [PATCH v5 1/3] target/riscv: smstateen check for fcsr
` [PATCH v5 2/3] target/riscv: Reuse tb->flags.FS
` [PATCH v5 3/3] target/riscv: smstateen knobs
[PATCH v3 0/4] target/riscv: Add Smrnmi support
2023-05-25 12:50 UTC (9+ messages)
` [PATCH v3 1/4] target/riscv: Add Smrnmi cpu extension
` [PATCH v3 2/4] target/riscv: Add Smrnmi CSRs
` [PATCH v3 3/4] target/riscv: Handle Smrnmi interrupt and exception
` [PATCH v3 4/4] target/riscv: Add Smrnmi mnret instruction
[PATCH v4 0/3] Implement the watchdog timer of HiFive 1 rev b
2023-05-25 12:06 UTC (8+ messages)
` [PATCH v4 1/3] hw/misc: sifive_e_aon: Support "
` [PATCH v4 2/3] hw/riscv: sifive_e: "
` [PATCH v4 3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e
[PATCH 0/2] Refresh the dynamic CSR xml after updating the state of the cpu
2023-05-25 2:33 UTC (13+ messages)
` [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml
` [PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu
[PATCH v5] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-05-25 2:24 UTC (2+ messages)
[PATCH 0/5] hw/riscv/opentitan: Correct QOM type/size of OpenTitanState
2023-05-25 2:21 UTC (17+ messages)
` [PATCH 1/5] hw/riscv/opentitan: Rename machine_[class]_init() functions
` [PATCH 2/5] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
` [PATCH 3/5] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
` [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition
` [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size
[PATCH v7 0/2] target/riscv: Fix pointer mask related support
2023-05-24 1:59 UTC (3+ messages)
` [PATCH v7 1/2] target/riscv: Fix pointer mask transformation for vector address
` [PATCH v7 2/2] target/riscv: Update cur_pmmask/base when xl changes
[PATCH v2] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
2023-05-23 9:58 UTC (19+ messages)
[PTACH v2 0/6] Add RISC-V KVM AIA Support
2023-05-23 9:51 UTC (6+ messages)
` [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support
[PATCH v3 0/3] Implement the watchdog timer of HiFive 1 rev b
2023-05-23 7:59 UTC (7+ messages)
` [PATCH v3 1/3] hw/misc: sifive_e_aon: Support "
` [PATCH v3 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e
[PATCH 0/7] Add support for extension specific disas
2023-05-22 14:30 UTC (20+ messages)
` [PATCH 1/7] disas: Change type of disassemble_info.target_info to pointer
` [PATCH 2/7] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
` [PATCH 3/7] disas/riscv.c: Support disas for Zcm* extensions
` [PATCH 4/7] disas/riscv.c: Support disas for Z*inx extensions
` [PATCH 5/7] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
` [PATCH 6/7] disas/riscv.c: Fix lines with over 80 characters
` [PATCH 7/7] disas/riscv.c: Remove redundant parentheses
[PATCH v5 00/11] RISC-V Add the OpenTitan Machine
2023-05-19 17:15 UTC (3+ messages)
` [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
` [PATCH v5 6/11] "
[PATCH v1] dt-bindings: riscv: deprecate riscv,isa
2023-05-18 21:42 UTC (8+ messages)
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